JP2681342B2 - Table update method for gateway device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gateway device for connecting networks, and particularly to a gateway device for updating a cache table in which a correspondence relationship between a destination address of a packet to be frequently transferred and a destination of the packet is registered. Of the table update method.

[0002]

2. Description of the Related Art With the recent increase in the speed of information communication, it has been required to improve the processing speed of gateway devices. Generally, in a gateway device, a destination is determined and packet transfer processing is performed by searching a correspondence table between a destination address and a sending network prepared in advance, using the destination address of the arrived packet as a key. However, since this correspondence table must hold the correspondence relationship between the destination address and the transmission destination for all the combinations, there is a problem that the table size is large and it takes time to search. Therefore, a table (hereinafter referred to as a cache table) in which only the correspondence relationship between the destination addresses that are transferred to a certain extent and the destinations is registered
First, the cache table is searched, and if the destination is determined, the table search holding all combinations can be omitted, so that the transfer processing can be speeded up.

In the conventional gateway device, software is used to search the cache table and update the registered contents (deleting or overwriting the correspondence between the destination address and the destination). Generally, when the cache table is full-entry and the update process for new registration contents is required, the registration contents that have not been received for a certain period of time or the oldest received contents among the registered contents. The updated ones are subject to update. In this case, the timer value of each registered content is serially compared by the software, and the entry that has passed the predetermined time or the entry that is received earliest is determined as the target of the update processing.

[0004]

As described above, in the conventional gateway device, the timer value indicating the elapsed time after the packet having the registered destination address is once received is serially compared by the software. Since the update target has been determined, it takes a lot of processing time, and the next processing cannot be performed until the update processing is completed, which causes a waiting time, which lowers the processing capability of the gateway device as a whole. there were.
The present invention has been made to solve the above problems,
An object of the present invention is to provide a table updating method capable of realizing speeding up of updating processing.

[0005]

According to the present invention, in a table search unit of a gateway device, there is provided a timer unit for generating a timer monitoring signal having a predetermined time period, a destination address and destination information corresponding thereto. All-entry mismatch detection unit that outputs all-entry mismatch signal when the destination address of the received packet does not match the destination address registered in each entry unit Each entry unit monitors whether or not a packet having a registered destination address is received during the period of the timer monitoring signal, and if not received, the registered contents are updated and in this state. When the all-entry disagreement signal is input, the destination address of the packet that received the registration contents and the corresponding transmission It is intended to update the information.

Further, the table search unit of the gateway device is provided with a plurality of entry units and an all-entity mismatch detection unit, and each entry unit monitors the reception frequency of packets having the registered destination address and If the value is low, the registered contents are updated, and when the all-entry disagreement signal is input in this state, the registered contents are updated to the destination address of the received packet and the destination information corresponding thereto.

A FIFO memory that stores the entry number assigned to each entry portion when the entry number is input, and outputs the stored entry numbers in the order in which they are stored when the all-entry mismatch signal is input. Each entry unit has its own entry number output to the FIFO memory when the registered content becomes updatable, and
The registered contents are updated only when the user's own entry number is input from the O memory.

[0008]

According to the present invention, each entry unit monitors whether a packet having the registered destination address is received during the period of the timer monitoring signal, and if not received, the registered contents can be updated. In this state, the registered content is updated when the all-entry mismatch signal is input, so that the cache table update process is performed in parallel by each entry unit. Also, each entry part monitors the reception frequency of packets having the registered destination address, and if the reception frequency is low, the registered contents are updated, and when the all-entry mismatch signal is input in this state. Since the registered contents are updated, the cache table update processing is processed in parallel by each entry unit.

Further, each entry section outputs its own entry number when the registered contents are updatable, and F
The IFO memory stores. And the FIFO memory is
When the all-entry disagreement signal is input, the stored entry numbers are output in the order in which they are stored, and each entry section outputs F
The registered content is updated only when the user's own entry number is input from the IFO memory.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a table search unit for realizing a table updating method according to an embodiment of the present invention. 1
Is the destination address AD1 extracted from the received packet
A table search unit of a gateway device that searches a cache table to be described later based on the above to find a destination of a packet, 2 is a timer unit that generates a timer monitoring signal TW having a predetermined time period, and 3a to 3n are destination addresses. It is an entry unit that stores the registered contents including the destination information corresponding to this.

Reference numeral 4 denotes an all-entry mismatch detection unit that outputs an all-entry mismatch signal NC when the destination address AD1 of the received packet does not match the destination address registered in each entry unit. When a given entry number is input, it is stored, and when an all-entry mismatch signal NC is input, the stored entry numbers are output in the order in which they are stored in a FIFO (First-In
First-Out) memory.

Further, 21 is a timer cycle setting register for storing an entry update time ET for setting the above-mentioned predetermined time, 22 is a counter for generating a timer monitoring signal TW based on the time ET, 30a is a destination address AD2 and this. 31a for storing destination information corresponding to
Is a comparison unit that compares the destination address AD1 of the received packet with the destination address AD2 stored in the register unit 30a, and outputs a comparison match signal CCa when they match. Reference numeral 32a denotes a reset pulse generation unit that monitors whether a packet having an address AD1 that matches the destination address AD2 is received during the period of the timer monitoring signal TW based on the signal CCa, and if not received, the register unit 30a. Output a register reset signal LR for making the update possible.

Reference numeral 33a is a status signal generator which outputs a register status signal ST indicating whether the register 30a is in the updatable state. Reference numeral 34a denotes a write pulse generation unit, which receives the status signal ST indicating that it can be updated, and when the entry number ID output from the FIFO memory 5 matches its own entry number, the all-entry mismatch signal NC. When is input, the write pulse signal WP for updating the contents of the register unit 30a is output. Reference numeral 35a is an entry ID sending buffer which outputs its own entry number when a status signal ST indicating that it can be updated is input.

Reference numeral 40a is a timer including, for example, a flip-flop, which sets an output when the comparison match signal CCa or the write pulse signal WP is input, and when the timer monitoring signal TW is input in this set state. Reset the output. 41a and 42a are OR circuits, 4
3a is a shift circuit for delaying the output of the OR circuit 42a by a fixed time, PN1 is packet destination information, TR is a timer reset signal for resetting the timer 40a,
IDa and IDn are entry numbers assigned to the entry parts 3a and 3n, respectively.

The table search section 1 of this embodiment has a plurality of entry sections 3a to 3n, and the entry sections other than 3a have the same internal structure as the entry section 3a, and are assigned to each entry section. The only difference is the entry number and the registered contents of each register. In this embodiment, the entry units 3a to 3n (more accurately, the register unit in each entry unit) form a cache table.

Next, the operation of the table search unit 1 will be described. FIG. 2 is a timing chart for explaining the operation of the table search unit 1, and PN2 is destination information stored in the register unit 30a. The entry update time ET is set by the user in the timer cycle setting register 21 of the timer unit 2. Then, the counter 22 sets the entry update time E set in the register 21.
2 having a period of T and synchronized with the input clock CK.
The "L" level timer monitoring signal TW as shown in (a) is generated.

The register section 30a in the entry section 3a is
The destination address AD1 extracted from the received packet and the destination information PN1 corresponding thereto are stored as the destination address AD2 and the destination information PN2, respectively. In this embodiment, a MAC address, which is an address for identifying a node in a MAC (Media Access Control) layer that is a protocol defined by the IEEE standard, is used as an example of a destination address, and an output port is used as destination information. Numbers are used.

The comparing unit 31a compares the destination address AD1 of the received packet with the destination address AD2 stored in the register unit 30a, and when they match,
"L" level comparison match signal CCa as shown in FIG.
Is output. When the signal CCa becomes “L”, the timer 40a in the reset pulse generator 32a operates as shown in FIG.
As shown in (c), the output Q is set to the “H” level (see FIG. 2).
Timing A).

The output bar Q of the timer 40a is at the "L" level which is the inverted output Q. Therefore, OR
The output of the circuit 42a becomes "H" level when the timer monitoring signal TW returns to "H".

When the timer monitoring signal TW becomes "L" again in such a state, the OR circuit 42a is caused by this signal TW.
Output changes from "H" to "L". And this OR
Since the output of the circuit 42a is delayed by the shift circuit 43a for a fixed time, the "L" level timer reset signal TR is added to the timer 40a. As a result, the output Q of the timer 40a is reset to the "L" level as shown in FIG. 2C (timing B in FIG. 2).

Next, when the output Q of the timer 40a is "L",
When the timer monitoring signal TW becomes "L", the register unit 30a is reset and the registered contents are deleted. This is the destination address AD2 stored in the register unit 30a.
The packet having the address AD1 that matches with is not received (the output Q remains “L”), and the signal TW is “L”.
When it becomes, it is determined that the predetermined time has elapsed, and the register unit 30a is set to the updatable state.

That is, the output Q is "L" and the signal TW is
Is "L", the register reset signal LR of "L" level is output from the output of the OR circuit 41a as shown in FIG. 2D (timing C in FIG. 2), and the destination address stored in the register unit 30a. AD2 and destination information PN2 are shown in FIG.
As shown in (e) and (f), it is reset (all registered contents are 0).

Further, when the reset signal LR becomes "L", the status signal generator 33a can update the register status signal ST which has been kept at the "H" level because the registered contents cannot be updated until the present time. Assuming that there is, it is set to the “L” level as shown in FIG. This "L"
In response to the level status signal ST, the entry ID sending buffer 35a is enabled (output enabled) and sends the stored entry number IDa to the FIFO memory 5.

Thus, as the updatable entry, the entry number IDa of the entry part 3a is the FIFO memory 5
Will be stored in In FIG. 2, the entry section 3
Although only the operation of a has been described, FIGS. 2 (a) to 2 (g)
The same operation as the above is performed in each entry section, and as soon as the entry section 3a can be updated like the entry section 3a by satisfying the above condition, the entry number of this entry section is stored in the FIFO memory 5.

Next, the all-entry mismatch detection unit 4 outputs the comparison match signals CCa to CCn each time a timing (not shown) indicating packet reception (comparison is performed by the comparison unit 31a at this timing) is input. If the comparison match signals are all at "H" level at this timing, all comparison mismatches, that is, the destination address AD of the received packet
It is determined that there is no match between 1 and the destination address registered in the entry parts 3a to 3n, and the "L" level all entry mismatch signal NC as shown in FIG. 2 (h) is output.

The FIFO memory 5 outputs the entry number stored earliest as the entry number ID when the all-entry mismatch signal NC becomes "L". The write pulse generator 34a uses the register unit 30 in its entry unit.
When a is updatable (status signal ST is “L”) and the entry number output from the FIFO memory 5 matches the number of its own entry part, if the all-entry mismatch signal NC becomes “L”, "L" as in Figure 2 (i)
A level write pulse signal WP is output (timing D in FIG. 2).

Due to this "L" level signal WP, the destination address AD1 of the received packet and the corresponding destination information PN1 corresponding to the new destination address are stored in the register unit 30a as shown in FIGS. 2 (e) and 2 (f). It is written as AD2 and destination information PN2. Then, since the registered contents of the own entry section are updated, the status signal generation section 3
3a sets the status signal ST to "H" level in response to the "L" level signal WP to indicate that updating is not possible, and the timer 40a also sets the output Q. As described above, the registered content of the entry part 3a is updated.

As described above, the present embodiment monitors whether or not the packet having the destination address registered in the register section of each entry section is received during the cycle designated by the entry update time ET, and is received. If not, the entry number of this entry part is registered in the FIFO memory 5 as an updatable entry part. Then, when the packet having the destination address AD1 that does not match the addresses registered in all the entry parts is received, the destination address and the corresponding destination information are written in the register of the updatable entry part.

At this time, by determining the update entry by using the FIFO memory 5, even when there are a plurality of updatable entry parts, the update processing is not biased only to a specific entry part. Although the present embodiment does not describe the operation of the table search for obtaining the transmission destination from the cache table (register section) based on the destination address of the received packet, this operation is not shown in the table search section. By means.

Further, in this embodiment, the contents of the register part are deleted when the entry part becomes the updatable state, but the registered contents can be held until the actual updating (in this case, However, the register reset signal LR may be input only to the status signal generator 33a.

FIG. 3 is a block diagram of a table search unit which realizes a table updating method according to another embodiment of the present invention, and the same components as those in FIG. 1 are designated by the same reference numerals. 1
1 is a table search unit, 13a to 13n are entry units, 3
Reference numeral 6a is a comparison unit that outputs the comparison match signal CCa as in the comparison unit 31a, and outputs the comparison mismatch signal CNC when there is a mismatch. Further, 37a is a status signal generation unit for outputting the register status signal ST similar to the example of FIG. 1, and sets the signal ST according to the write pulse signal WP or the comparison match signal CCa and according to the register reset signal LR. Reset the signal ST.

Reference numeral 38a denotes a count control section which, when the comparison match signal CCa is inputted, outputs an initial value set signal FS for setting the counter value of a down counter, which will be described later, to an initial value, and a comparison disagreement signal CNC. Is input, a countdown signal CD for reducing the counter value by 1 is output, and when the counter value is "0" and the all entry mismatch signal NC is input, a signal FS is output. Reference numeral 39a is a 2-bit quaternary down counter, which sets an internal counter value to an initial value 3 when a set signal FS is input, and decrements the counter value by 1 when a countdown signal CD is input. When it becomes "0", the register reset signal LR is output.

Next, the operation of such a table search unit will be described. FIG. 4 is a timing chart for explaining the operation of the table search unit 11, where PH is the timing of packet reception and DVC is the down counter 3.
9a is the internal counter value. In this embodiment,
An IP address, which is a network address for identifying a node in the IP (Internet Protocol) layer, is used as an example of a destination address.

The comparing unit 36a receives the destination address AD1 of the received packet and the destination address AD of the register unit 30a.
2 is compared, and when they match, a comparison match signal CCa as shown in FIG. 4B is output, and if they do not match, the “L” level comparison mismatch signal as shown in FIG. 4C. Output CNC. The count controller 38a uses the signal CC
When "a" becomes "L", an initial value setting signal FS (not shown in FIG. 4) is output, which causes the down counter 39a.
Sets the counter value DVC to the initial value 3 as shown in FIG. 4D (timing A in FIG. 4).

Then, the count controller 38a outputs the signal C
When NC becomes "L", a countdown signal CD (not shown in FIG. 4) is output, whereby the down counter 39a is output.
Reduces the counter value DVC by 1 as shown in FIG. 4 (d) (timing B in FIG. 4). When such a countdown continuously occurs due to the continuous output of the comparison disagreement signal CNC and the counter value DVC becomes "0", the down counter 39a outputs the register reset signal LR as shown in FIG. 4 (e). (Timing C in FIG. 4). However, after the counter value DVC becomes "0", the comparison disagreement signal CN
Even if C becomes "L", the counter value DVC is held as "0".

In the example of FIG. 1, the contents of the register unit 30a are deleted by the reset signal LR, but in the present embodiment, the reset signal LR is input to the register unit 30a in order to hold the registered contents as long as possible. Since it does not, the contents are still retained at this point. And
When the reset signal LR becomes "L", the status signal generator 37a sets the status signal ST to "L" level as shown in FIG. 2 (i).

When the signal ST becomes "L", the entry ID sending buffer 35a sends the stored entry number IDa to the FIFO memory 5, as in the example of FIG.
In this way, as the updatable entry, the entry unit 13
This means that the entry number IDa of a is stored in the FIFO memory 5. Note that the same operation as in FIGS. 4A to 4I is performed in each entry part, and as soon as the entry part 13a can be updated, the entry number of this entry part becomes F.
The storage in the IFO memory 5 is the same as in the example of FIG.

Next, the all entry mismatch detection section 4, the FIF
The O memory 5 performs exactly the same operation as in the example of FIG. Then, the write pulse generator 34a also outputs the write pulse signal WP as shown in FIG. 4 (k) under exactly the same conditions as in the example of FIG. 1 (timing D in FIG. 4). By this "L" level signal WP, the register unit 30a receives the signal shown in FIG.
As shown in (g), new destination address AD2 and destination information PN2 are written. Then, since the signal WP has become "L", the status signal generator 37a sets the register status signal ST to "H" level as shown in FIG. 4 (i).

Since the count value of the down counter 39a is "0" and the all-entry mismatch signal NC of "L" level is input, the count control section 38a outputs the initial value set signal FS. Thus, the down counter 39a sets the counter value DVC to the initial value 3 as shown in FIG. As described above, the entry unit 13
The registered content of a is updated.

The update process does not occur while the counter value DVC is "0", and the comparison match signal CCa of "L" level is generated.
Occurs (that is, it indicates that the packet having the registered destination address is received again), the counter control unit 38a responds to the signal CCa to set the signal FS.
Is output, and the counter value DVC is set to the initial value 3 (timing E in FIG. 4).

As described above, in this embodiment, the reception frequency of the packet having the destination address registered in the register section of each entry section is monitored by the counter value DVC, and when the reception frequency is low (the counter value DVC is the initial value). When the value is set to 3 and there is no reception 3 times), the entry number of this entry part is registered in the FIFO memory 5 as an updatable entry part.

As a result, the target of the update process can be determined based on the reception amount instead of the time as in the example of FIG. Although the contents of the register unit are overwritten in the present embodiment, the contents of the register unit can be deleted when the entry unit becomes updatable by inputting the register reset signal LR to the register unit. It goes without saying that you can do it.

[0043]

According to the present invention, each entry unit monitors whether a packet having a registered destination address is received during the period of the timer monitoring signal, and if not received, updates the registered content. Since the registered contents are updated when the non-matching signal for all entries is input in this enabled state, the cache table update process can be processed in parallel by each entry unit. Therefore, when the registration contents need to be updated, the processing can be performed instantaneously, the waiting time for the next processing does not occur, and the processing capacity of the gateway device is not reduced.

Further, each entry part monitors the reception frequency of the packet having the registered destination address, and when the reception frequency is low, the registered contents are made updateable. In this state, the all entry mismatch signal is input. Since the registered contents are updated at this time, the cache table update processing can be processed in parallel by each entry unit. Therefore, when the registration contents need to be updated, the processing can be performed instantaneously, the waiting time for the next processing does not occur, and the processing capacity of the gateway device is not reduced. Moreover, since the target of the update process is determined based on the received amount, the update process can be performed appropriately corresponding to the communication status.

Further, by providing a FIFO memory for sequentially outputting the stored entry numbers, the entry portion to be updated is determined by this FIFO memory.
Even when there are a plurality of updatable entry parts, the updating process is not biased to a specific entry part.

[Brief description of the drawings]

FIG. 1 is a block diagram of a table search unit that realizes a table updating method according to an embodiment of the present invention.

FIG. 2 is a timing chart diagram for explaining the operation of the table search unit of FIG.

FIG. 3 is a block diagram of a table search unit that realizes a table updating method according to another embodiment of the present invention.

FIG. 4 is a timing chart diagram for explaining the operation of the table search unit of FIG.

[Explanation of symbols]

1, 11 ... Table search unit, 2 ... Timer unit, 3a to 3a
n, 13a to 13n ... Entry section, 4 ... All entry mismatch detection section, 5 ... FIFO memory, 30a ... Register section,
31a, 36a ... Comparison unit, 32a ... Reset pulse generation unit, 33a, 37a ... Status signal generation unit, 34a ...
Write pulse generator, 35a ... Entry ID sending buffer, 38a ... Count controller, 39a ... Down counter.

Continuation of front page (56) Reference JP-A-7-202930 (JP, A) JP-A-6-338907 (JP, A) JP-A-6-261078 (JP, A) JP-A-6-152655 (JP , A) IEEE INFOCOM'91 P. 1228-1236 IEEE INFOCOM'88 P. 298-307 IPSJ Research Report DPS-74- 34

Claims (3)

(57) [Claims] 1. A table search unit of a gateway device that obtains a destination of a packet based on the destination address of a received packet from a cache table in which the correspondence between the destination address of a packet that is frequently transferred and the destination of the packet is registered. A timer section for generating a timer monitoring signal having a predetermined period of time, a plurality of entry sections serving as the cache table for storing registration contents including a destination address and destination information corresponding thereto, and a received packet Of the gateway device for updating the registered content, which includes an all-entry inconsistency detection unit that outputs an all-entry inconsistency signal when the destination address of each entry does not match the destination address registered in each entry unit. Each entry part has a packet with a registered destination address. Is received during the period of the timer monitoring signal, and if it is not received, the registered content is updated, and when the all-entry mismatch signal is input in this state, the registered content is received. A table updating method for a gateway device, characterized in that a destination address of a packet and destination information corresponding thereto are updated. 2. A table search unit of a gateway device that obtains a destination of a packet based on a destination address of a received packet from a cache table in which a correspondence relation between a destination address of a packet that is frequently transferred and a destination of the packet is registered. In addition, a plurality of entry parts that are the cache table that stores the registered contents consisting of the destination address and the transmission destination information corresponding to this, the destination address of the received packet and the destination address registered in each entry part match. A table updating method of a gateway device that performs an updating process of the registered contents, which is provided with an all-entry mismatch detection unit that outputs an all-entry mismatch signal when each entry unit does not register the registered destination address. Monitor the reception frequency of the packets you have, and if the reception frequency is low, update the registered contents. The gateway device is characterized in that the registration contents are updated to the destination address of the received packet and the destination information corresponding thereto when the all-entry disagreement signal is input in this state. Table update method. 3. The table updating method for a gateway device according to claim 1, wherein when an entry number assigned to each entry part is input, it is stored, and when an all-entry disagreement signal is input, It has a FIFO memory that outputs the stored entry numbers in the order in which they are stored, and each entry unit outputs its own entry number to the FIFO memory when the registered content becomes updatable and from the FIFO memory. A table updating method for a gateway device, characterized in that the registered contents are updated only when the user's own entry number is entered.