JP2679502B2 - Timing circuit for digital transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing circuit of a self-timing type optical receiving circuit, and more particularly to a timing for a digital transmission system which automatically (or presets) an optimal timing format according to the magnitude of jitter in a transmission code string. Regarding the circuit.

[0002]

2. Description of the Related Art In recent years, BPF (bandpass filter) type timing circuits (hereinafter abbreviated as A type) and PLL (phase lock loop) type timing circuits (hereinafter B type) have been generally used as self-timing methods for optical receiving circuits. Is abbreviated) and the like are used. In the A type, the equivalent Q value of BPF is about 500 to 2000, whereas in the B type, it is as large as about 10,000 or more. Therefore, in the transmission system shown in FIG. 2, which is composed of only type A, the jitter accumulation is large, but the jitter tolerance is also large, and the characteristics in the case of multi-repeater transmission are good. On the other hand, in the transmission system configured only by the B type, the jitter tolerance is small, but the jitter tolerance is also small, and the characteristics in the case of multi-relay transmission as in the A type are good.

However, in the case of a transmission system composed of a combination of A and B types, especially after a multi-relay system of A type, B
When receiving with the type, since the jitter tolerance is small, a code error occurs and it cannot be applied.

In recent years, in a transmission method requiring long-distance and large-capacity transmission, there is an increasing demand for multi-vendor (device facing between different types of transmission equipment manufacturers) in consideration of multilateral connection, and international standardization is progressing ( As an example, G.958 (S) that defines an SDH (Synchronous Digital Hierarchy) optical transmission system in CCITT (International Telegraph and Telephone Advisory Committee)
DH optical fiber transmission system))).

In such a case, a plurality of specifications may be recommended in order to increase the degree of freedom of design among manufacturers in each country.
Recommendation G. Also in 958, two types of specifications corresponding to the above-mentioned A type and B type are described side by side as timing formats applied to the optical receiving circuit. Therefore, it is expected that optical transmission systems having the characteristics of these two types of timing circuits will coexist in the future, and the need for the timing circuit according to the present invention is increasing in order to cope with this.

[0006]

According to the conventional method, as shown in FIG.
In the case of the BPF type timing circuit in which the transmitting terminal station device 201 and the intermediate repeater 202 shown in FIG. 2 are A type, the photoelectric converter OE from the receiving terminal station device 203 needs to be of A type timing format. There is. The transmitting terminal device 2
01, when the receiving end station device 203 is a different company vendor, the vendor supplying the receiving end station device 203 needs to match the timing format.

[0007]

It is an object of the present invention to improve the disadvantages of the conventional example, and in particular, in a digital signal transmission system of either the band pass filter type timing circuit section or the PLL type timing circuit section It is an object of the present invention to provide a timing circuit for a digital transmission system which can be adapted to a transmission system.

[0008]

According to the present invention, there is provided a BPF type tag.
At least an imming method and a PLL type timing method
Digi installed in the receiving terminal station of the optical transmission system that adopts one
Optical transmission line in timing circuit for digital transmission system
BPF type timing input the data string sent from
Output to the BPF type timing circuit
PLL type timing circuit section which is in phase synchronization with
BPF type timing circuit section and PL
Timing signal from either one of L-type timing circuit
And a switching circuit section for outputting Of these, switching times
The path portion is a BPF type timing circuit to which a data string is input.
A jitter amount detection circuit that detects the amount of jitter from the output of the unit,
If the output voltage of this jitter amount detection circuit is higher than the specified voltage,
If it is, the timing signal is output from the BPF type timing circuit section.
Output voltage of the jitter amount detection circuit is lower than the specified voltage.
If not, send a timing signal from the PLL timing circuit.
A differential output type comparator for outputting is included. This aims to achieve the above-mentioned object.

[0009]

The operation of the switching circuit 6 will now be described.
The amount of jitter generated in the output of the BPF type timing circuit 4 is
It can be detected by the jitter amount detection circuit 12 including a frequency discriminator and a circuit for detecting the output rms value. Since the DC voltage value outputted from the jitter detection circuit 12 is proportional to the jitter amount, is greater than a value V _R to select the timing circuit of the A type, selecting the timing circuit of type B is smaller than V _R To do. V _R is P as a switching threshold
It is set in advance according to the jitter tolerance of the LL type optical receiver.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the invention will be described below with reference to FIG. The embodiment shown in FIG. 1 is a timing circuit for a digital transmission system installed in a receiving terminal station, and includes a bandpass filter type timing circuit section 4 and a PLL.
Type timing circuit unit 5 and a switching circuit unit 6 for switching and operating either the bandpass filter type timing circuit unit 4 or the PLL type timing circuit unit 5 depending on the amount of jitter in the transmitted data sequence. doing. PLL
The timing circuit section 5 is configured to be phase-synchronized with the output of the bandpass filter type timing circuit section.

More specifically, the BPF type timing circuit 4 includes a timing extraction circuit 7 for generating a timing component by performing a non-linear operation (for example, differential folding) from a data string (for example, NRZ waveform), and a bandpass filter 8.
(For example, dielectric filter, SAW filter, MCF, etc.)
And a limiter 9 that obtains a constant amplitude irrespective of the pattern variation of the pulse train, and constitutes a timing system with a relatively low Q value. On the other hand, the PLL timing circuit 5 controls the voltage controlled oscillator (VCO) 10 and the VCO output frequency by BP.
It comprises a phase comparator 11 for phase-locking with the timing signal from the F-type timing circuit 4, and has a considerably high Q.
Configure the value timing system. The switching circuit unit 6 uses the BPF type timing circuit 4 depending on the amount of jitter in the data string.
Alternatively, it has a function of switching the timing output of the PLL timing circuit 5. That is, the jitter amount from the BPF type timing circuit 4 is detected by the jitter amount detection circuit 12, and if the output voltage is higher than V _R , the comparator 13 outputs AN.
A timing signal is output from the output of the OR circuit 16 by operating the D gate 14. If the output voltage of the jitter amount detection circuit 12 is lower than V _R , the comparator 13 AND
The gate 15 is operated and the timing signal is output from the OR circuit 16. The switching circuit 12 is automatically (or by preset) by the set value of V _R can operate.

The circuit composed of 4, 5 and 6 can be integrated into an IC except for the bandpass filter 8, and the cost increase by this structure is slight.

[0013]

As described above, according to the present invention,
By having both a bandpass filter type timing circuit and a PLL type timing circuit, both timing circuits also have a switching circuit for automatically (or by presetting) switching depending on the amount of jitter in the data string. It is possible to provide an unprecedented excellent timing circuit for a digital transmission system, which can cope with any timing formation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an entire multistage repeater type optical transmission system which is a background art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Optical / electrical conversion device 2 Automatic gain control type amplifier 3 Discriminator 4 Band pass filter type timing circuit 5 PLL type timing circuit 6 Switching circuit 201 Transmitting terminal station device 202 Intermediate repeater 203 Receiving terminal station device

Claims (2)

(57) [Claims] 1. A BPF type timing system and a PLL type device.
In a timing circuit for a digital transmission system installed in a receiving terminal station of an optical transmission system that employs at least one of the imming systems, a BP for inputting a data string sent from the optical transmission line.
F type timing circuit section and this BPF type timing circuit
A PLL type timing circuit unit that is phase-synchronized with the output of the unit,
Any one of the data the BPF type timing circuit portion in amount of jitter magnitude in a column and the PLL type timing circuitry
Bei a switching circuit section for outputting a timing signal from the person
The switching circuit section is a BPF type to which the data string is input.
Jitter that detects the amount of jitter from the output of the timing circuit section
The amount detection circuit and the output voltage of this jitter amount detection circuit
If the voltage is higher than the voltage, the BPF type timing circuit block
The output signal of the jitter amount detection circuit is output.
If the pressure is lower than a predetermined voltage, the PLL timing circuit
Differential output type comparator that outputs timing signals from the road
And a timing circuit for a digital transmission system , which includes: 2. The timing circuit for a digital transmission system according to claim 1, wherein the PLL type timing circuit section is configured to be phase-synchronized with an output of the bandpass filter type timing circuit section.