JP2678266B2 - Control device for high-frequency high-voltage power supply - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for controlling the electric power supplied to a load in a high frequency high voltage power supply used in a corona discharge treatment device or the like.

[0002]

2. Description of the Related Art As described in Japanese Patent Application Laid-Open No. 1-218356, the applicant of the present invention rectifies electric power from a commercial AC power source by a rectifier circuit and switches the DC power by an inverter to a high voltage transformer. In a high-frequency high-voltage power supply that boosts voltage, a switching semiconductor element was connected between a DC power supply and a high-voltage transformer, and a method for adjusting the high-frequency output power from the high-voltage transformer by changing the switching excitation frequency was previously proposed. There is.

[0003]

By the way, when a high voltage from a high frequency high voltage power source is applied to a discharge electrode to surface-treat a plastic film or the like by corona discharge, when viewed from the inverter of the high frequency high voltage power source, a high voltage transformer is used. The discharge electrode and the high-voltage wiring portion form a series resonance circuit and serve as a resonance load. Therefore, in a general semiconductor element, unless switching operation in the vicinity of zero, which is always synchronized with the resonance current, is performed, heat generation and element destruction may occur due to switching loss. Discloses only a general method of changing the switching excitation frequency, and does not take such problems into consideration. Further, the output power adjustment is also lacking in concreteness, and continuous adjustment over a wide range cannot be concretely realized.

Therefore, an object of the present invention is to eliminate switching loss by ensuring that the switching operation in the vicinity of zero, which is synchronized with the resonance current, can be eliminated, and at the same time, the synchronous operation can be performed. It does not become discontinuous, and the output power can be easily adjusted over a wide range. Therefore, when performing corona discharge treatment, it is possible to perform precise adjustment over a wide range from weak treatment to strong treatment.
It is to provide a control device for a high frequency high voltage power supply.

[0005]

In order to achieve such an object, the control device according to the present invention comprises the following means. A current detecting means for detecting a resonance current flowing between the high frequency inverter of the high frequency high voltage power supply and the high voltage transformer, that is, the resonance circuit. It includes a phase comparator and a voltage controlled oscillator, a phase comparator
Is the detection current of the current detection means and the output signal of the voltage controlled oscillator
The voltage controlled oscillator outputs a voltage corresponding to the phase difference between
Outputs a signal with a frequency according to the output voltage of the phase comparator
P that outputs the output signal of the voltage controlled oscillator
LL (Phase Locked Loop) circuit. Pulse density modulation (Pulse Density Modularity) that changes the ratio of HIGH and LOW by inputting the output signal of this PLL circuit and thinning it out
The pulse density modulation circuit (hereinafter, referred to as PDM circuit) which outputs a pulse having a zero voltage output period of a set length in synchronism with this output signal. A gate signal generation circuit which inputs a pulse from the PDM circuit and outputs a gate signal to a switching semiconductor element of a high frequency inverter. A voltage storage means for storing the input voltage of the voltage controlled oscillator before the zero voltage output period and inputting the stored voltage to the voltage controlled oscillator even during the zero voltage output period.

As a switching semiconductor element of a high frequency inverter, an insulated gate bipolar transistor (Insulated Gat) which is a high speed switching element is used.
eBipolar Transistor. Below, IG
It is referred to as BT. Is preferred. The voltage storage means can be composed of a sample hold circuit.

[0007]

[Operation] The resonance current of the resonance circuit is detected by the current detection means,
The PLL circuit locks at a frequency in phase with the resonance current to obtain a synchronized pulse. This pulse is thinned by a pulse modulation circuit to obtain a pulse having a zero voltage output period of a set length, thereby changing the gate signal pattern for the switching semiconductor element to adjust the output power. When the zero voltage output period is formed, the current detection unit cannot detect the current during that period, but the input voltage of the voltage controlled oscillator before this period is stored in the voltage storage unit, and the stored voltage is used as the voltage. By continuing the oscillation of the controlled oscillator, the voltage controlled oscillator continuously oscillates the signal of the same frequency. Therefore, P
The operation of the LL circuit does not become discontinuous, and moreover, it continues stable operation accurately synchronized with the resonance circuit even during the zero voltage output period. Since the PDM circuit can continuously change the pulse density by continuously changing the PDM command value, the output power can be continuously and arbitrarily adjusted.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. As shown in FIG. 1, the high-frequency high-voltage power supply is rectified by a diode bridge rectifier circuit 2 for rectifying an AC voltage from a three-phase 200V commercial AC power supply 1, a smoothing circuit 5 including a DC reactor 3 and a capacitor 4, as shown in FIG. A high frequency inverter 6 for converting direct current into a high frequency and a high voltage transformer 7 for boosting the high frequency voltage are applied, and a high frequency high voltage is applied to the discharge electrode 8. High frequency inverter 6
Seen from, between the high voltage transformer 7 and the discharge electrode 8,
Leakage inductance and stray capacitance of the high-voltage transformer 7,
An RCL series resonance circuit is formed by the capacitance of the discharge electrode 8 and the wiring resistance, and an external reactor and a capacitor are unnecessary.

The high frequency inverter 6 is two-in this example.
Two in-one type insulated gate bipolar transistor modules are used, and four IGBTs 9a.9 are used.
A full bridge configuration is formed by b.9c.9d and two coupling capacitors 10. Each IGBT has a freewheeling diode 11 for preventing switching loss at turn-on, and a snubber capacitor for suppressing a rise in collector-emitter voltage at turn-off and bypassing the collector current to reduce switching loss. 12 are connected in parallel. In this example, as shown in (1) and (2) of FIG. 3, the output current I ₀ is always delayed by the phase angle β with respect to the output voltage V ₀ of the high frequency inverter 6 as described later. Control.

In such a high-frequency high-voltage power supply, the control device according to the present invention detects the resonance current flowing between the high-frequency inverter 6 and the high-voltage transformer 7 by the current detector 13, and inputs the current to the control circuit 14. Then this control circuit 1
4 outputs a gate signal in synchronization with the resonance current, and this gate signal controls the on / off of the IGBTs 9a, 9b, 9c, 9d, and the density of the pulse serving as the gate signal is arbitrarily modulated to obtain a high-frequency signal. The power supply of the voltage power supply is controlled, and FIG. 2 shows a configuration example of the control circuit 14.

The control circuit 14 is roughly divided into a PLL circuit 15 and a PDM circuit 16. P in this embodiment
The LL circuit 15 has a basic closed-loop circuit configuration including a phase comparator 18, a low-pass filter 19, a voltage-controlled oscillator 20, and a comparator 21, and further includes a zero-cross comparator 17 on the input side of the phase comparator 18, and a low-pass comparator. A sample hold circuit 28, which is a voltage storage means, is provided between the filter 19 and the voltage controlled oscillator 20.
The zero-cross comparator 17 is for converting the resonance current detected by the current detector 13 into a rectangular wave as shown in (3) of FIG. 3, and its output is output from the comparator 21 in the phase comparator 18. The output shown in (4) of 3 is compared with the rising phase. The output of the phase comparator 18 is passed through the low-pass filter 19 ((4)
The sample and hold circuit 2 becomes a rectangular wave like -1).
8 is input.

As is well known, the sample and hold circuit 28 comprises a buffer amplifier, a holding capacitor, a switch and a drive circuit for the switch, and the switch has a (4-
As shown in 2), the output voltage of the low-pass filter 19 is sampled every time it is turned on, and the voltage is held. The voltage controlled oscillator 20 receives the output voltage from the sample hold circuit 28 and generates a signal having a frequency corresponding to the voltage. The voltage controlled oscillator 20 in this example is (5) in FIG.
A triangular wave signal having a frequency corresponding to the input voltage as shown in is output. This triangular wave signal is compared with the phase angle command signal from the operation unit (not shown) by the comparator 21, and a pulse deviated by the phase angle β due to the phase angle command signal is output from the comparator 21 as shown in (4) of FIG. This pulse is phase-compared with the output shown in (3) from the zero-cross comparator 17 in the phase comparator 18 as described above. Therefore, the PLL circuit 15 includes the comparator 1
The output of 7 and the output of the comparator 21 are in phase with each other and locked at a frequency corresponding to the input voltage of the voltage controlled oscillator 20.

The PDM circuit 16 comprises a comparator 22, an AND circuit 23, a latch circuit 24, a comparator 25, an integrator 26 and a dead time circuit 27.
The comparator 22 converts the triangular wave signal from the voltage controlled oscillator 20 into two systems of inverted pulses as shown in (6) and (7) of FIG. In this case, the pulse is
Due to the above-described operation in the PLL circuit 15, the output of the comparator 21, that is, the resonance current I ₀ , is advanced by β from the resonance current I ₀ .

One pulse from the comparator 22 is
As shown in (8) of FIG. 3, it is input to the latch circuit 24 as a reference signal (clock pulse). The output shown in (9) of FIG. 3 from the latch circuit 24 is input to the sample hold circuit 28 as a switch control signal, and the switch of the sample hold circuit 28 is turned on every time the output of (9) becomes HIGH. And low-pass filter 19
The output voltage of (3) is sampled and held, and this voltage is continuously held even when the output of (9) is LOW. The output of (9) is input to the integrator 26 as shown in (10) of FIG.
The waveform is as shown in 1). The integrated output is compared with the PDM command signal from the operation unit by the comparator 25,
The comparator 25 outputs a pulse with a different ratio of HIGH and LOW as shown in (12) of FIG.
The PDM loop is formed by inputting the modulated (pulse density modulation) pulse again to the latch circuit 24. Then, the output of this loop is logically ANDed with the output pulse (reference signal) of the two systems of the comparator 22 by the AND circuit 23 to create a zero voltage output period while synchronizing with the resonance current. In this case, as shown in (13) and (14) of FIG. 3, the output of the A / B2 system from the AND circuit 23 is such that after A becomes HIGH, B continuously becomes HIGH, which is the PDM command. It is repeated at the time interval set in. That is, the HIGH portion of the output pulse of the two systems of the comparator 22 is thinned out for the period when the output of the latch circuit 24 is LOW, and the thinning-out number can be arbitrarily adjusted by the PDM command. Figure 3 shows 5 pulses per 6
FIG. 4 shows the case of thinning one by one, and FIG. 4 shows the case of thinning one by three.

The A / B2 system output from the AND circuit 23 is input to a dead time circuit 27 which is also a gate signal generating circuit for turning on / off the IGBTs 9a, 9b, 9c, 9d, and the dead time circuit 27 3 of (1
As shown in 5), (16), (17), and (18), the signals are output as four-system gate signals delayed by a constant dead time d. Then, the output of (15) in the figure is to the IGBT 9a in FIG. 1, the output of (16) is to the IGBT 9b,
The output of (17) is to the IGBT 9c, the output of (18) is I
It is input to the GBT 9d as a gate signal. That is, the same pulse as the gate pulse J for the IGBT 9a is input to the IGBT 9d and the same pulse as the gate pulse for the IGBT 9c is input to the IGBT 9b, respectively, and after the IGBTs 9a and 9d are turned on, the IGBT 9c must be turned on.・ Turn on 9b. In the zero voltage output period, all the IGBTs 9a, 9b, 9c, 9d
Be sure to turn off.

As described above, before the zero voltage output period is reached,
By holding the input voltage by the sample hold circuit 28 in the PLL circuit 15 as described above, the voltage controlled oscillator 28 continuously generates a signal of the same frequency. Therefore, the operation of the PLL circuit 15 does not become discontinuous, and moreover, it is possible to continue the stable operation accurately synchronized with the resonance circuit even in the zero voltage output period. Further, since the PDM circuit 18 can continuously change the PDM command value, the pulse density also continuously changes, and the zero voltage output period can be arbitrarily adjusted. Since the discharge power is proportional to the square of the voltage, it is impossible to finely adjust the power at any low level in the state where the PDM is 0, that is, in the high frequency high voltage power supply without the zero voltage output period, but this control According to the high frequency high voltage power supply equipped with the device, the discharge power can be continuously and arbitrarily adjusted from 100% to slightly less than 1%.

A prototype device was manufactured based on the above structure and tested. The maximum rating of the IGBT module used is a collector-emitter voltage of 500 V and a collector current of 50 A, and the resulting high-frequency inverter 6 has a steady frequency of 30 KHz and power of 5 KW. The dead time d in the dead time circuit 27 is 1.5 μse.
c, the turn ratio of the high-voltage transformer 7 is 30: 600. Experimental results are shown in FIGS. 5 and 6.

FIG. 5 shows the high frequency inverter 6 in FIG.
DC input voltage is 200V, current 9.6A, power 19
At 20 W, the pulse ratio by the PDM circuit 16 of FIG. 2 is 8 /
9 shows voltage waveforms and current waveforms on the secondary side of the high voltage transformer 7 when thinning out one pulse out of eight pulses. Further, in FIG. 6, the DC input of the frequency inverter 6 is
0V, current 4.5A, power 900W, PDM circuit 16
2 shows a voltage waveform and a current waveform on the secondary side of the high-voltage transformer 7 when the pulse ratio is 2/3, that is, one pulse is thinned out every two pulses.

In the embodiment shown in FIG. 1, the high frequency inverter 6 has a full-bridge structure with four IGBTs, but as shown in FIG. 7, it has a half-bridge structure with two IGBTs 9a and 9b and a capacitor 28 is used. It may be connected to the high voltage transformer 7. High frequency inverter 6
If it is composed of a GBT, it can be a high-speed reliable inverter, but it may be composed of an FET, and if the required frequency is not so high, it may be another general switching semiconductor element. I don't mind.

In the above embodiment, the PLL circuit 15 uses the sample-hold circuit for analog storage as the voltage storage means for storing the input voltage before the zero voltage output period. It is also possible to use a memory that stores digitally. Further, the PDM circuit 16 can also have a digital circuit configuration instead of the above analog circuit configuration. In this case, a signal from the PLL circuit 15 is converted into digital data by a counter, and then a pulse having an arbitrary pattern is read from a memory in which various pulse patterns are stored in advance according to the data from the counter. And
The read pulse is synchronized with the pulse from the PLL circuit to obtain the gate signal for the high frequency inverter.

[0021]

As described above, according to the present invention, the resonance current of the resonance circuit is detected by the current detector, and the PLL circuit locks and synchronizes at the frequency at which the resonance current and the phase match each other. Since the switching semiconductor element of the high-frequency inverter is controlled to be turned on / off by the generated pulse, the switching loss can be reduced. Further, by forming the zero voltage output period of the set length for the pulse of the PLL circuit,
The output power is adjusted by changing the pattern of the gate signal for the switching semiconductor element, but the input voltage before this period is stored in the voltage storage means, and the voltage-controlled oscillator is continued at the stored voltage. Since it oscillates, this voltage controlled oscillator continuously oscillates a signal of the same frequency.
Therefore, the operation of the PLL circuit does not become discontinuous, and moreover, it is possible to continue the stable operation accurately synchronized with the resonance circuit even during the zero voltage output period.

Further, since the PDM circuit can continuously and finely change the pulse density by continuously changing the PDM command value, the output power is from 100% at the maximum output to 1% or less. It can be adjusted continuously over a wide range. Therefore, when the corona discharge treatment is performed, it is possible to precisely adjust in a wide range from weak treatment to strong treatment.

According to the second aspect of the present invention, the high frequency inverter can be a reliable inverter which operates at high speed, so that a stable high frequency output can be obtained. According to claim 3, the PLL
In the circuit, the voltage storage means for storing the input voltage of the voltage controlled oscillator can be easily and inexpensively constructed by a ready-made sample hold circuit.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram of an example of a high frequency high voltage power supply.

FIG. 2 is a block diagram of an example of a control device according to the present invention for controlling the high-frequency high-voltage power supply.

FIG. 3 is an operation timing chart of the control device.

FIG. 4 is an operation timing chart when the pulse thinning condition is changed from the case of FIG.

FIG. 5 is a waveform diagram of the voltage and current on the secondary side of the high-voltage transformer, which is the result of an experiment using the prototype device of the control device.

6 is a waveform diagram of voltage and current on the secondary side of the high-voltage transformer when conditions are changed from the case of FIG.

FIG. 7 is an electric circuit diagram of a high-frequency high-voltage power supply having a high-frequency inverter having a half-bridge configuration with two IGBTs.

[Explanation of symbols]

1 Commercial AC Power Supply 2 Smoothing Circuit 6 High Frequency Inverter 7 High Voltage Transformer 8 Discharge Electrode 9a ・ 9b ・ 9c ・ 9d Insulated Gate Bipolar Transistor 13 Current Detector 14 Control Circuit 15 PLL Circuit 16 Pulse Density Modulation Circuit (PDM Circuit) 27 Dead Time Circuit (gate signal generation circuit) 28 Sample and hold circuit (voltage storage means)

Claims (3)

(57) [Claims] 1. An AC voltage from a commercial AC power supply is rectified to a DC by a rectifying circuit, converted into a high frequency by a high frequency inverter having a switching semiconductor element bridge-connected, and then boosted by a high voltage transformer, and the voltage from the high voltage transformer to a load is increased. There in the high frequency high voltage power source to form a resonant circuit with respect to high-frequency inverter, comprising: a current detecting means for detecting a current flowing between the high-voltage transformer and the high-frequency inverter, a phase comparator and a voltage controlled oscillator, the phase The comparator is the above
The detection current of the current detection means and the output signal of the voltage controlled oscillator
Output a voltage corresponding to the phase difference from the signal
The oscillator is a signal of a frequency corresponding to the output voltage of the phase comparator.
The output signal of the voltage controlled oscillator
And a pulse density modulation circuit which outputs a pulse having a zero voltage output period of a set length in synchronization with the PLL circuit by inputting and thinning out the output signal of the PLL circuit, A gate signal generation circuit that inputs a pulse from the pulse density modulation circuit and outputs a gate signal to the switching semiconductor element of the high-frequency inverter, and stores the input voltage of the voltage controlled oscillator before the zero voltage output period. And a voltage storage means for inputting the stored voltage to a voltage controlled oscillator even during a zero voltage output period. 2. The control device for a high frequency high voltage power supply according to claim 1, wherein the switching semiconductor element is an insulated gate bipolar transistor. 3. The high frequency high voltage power supply controller according to claim 1, wherein said voltage storage means is a sample hold circuit.