JP2674420B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a field effect transistor using a compound semiconductor material which performs well in a microwave and millimeter wave region which cannot operate with a Si material device. The present invention relates to a wafer laminated structure of a two-dimensional electron gas field effect transistor that operates using a two-dimensional electron gas formed as a channel.

[0002]

2. Description of the Related Art In recent years, three-dimensional and quaternary mixed crystal semiconductors such as InGaAs and InGaAsP have attracted attention. Among them, InGaAs lattice-matched to an InP substrate is used not only for optical devices but also for various field effect transistor materials. In particular, field-effect transistors using a two-dimensional electron gas at a hetero interface with InP or InAlAs are being actively researched. The reason why InGaAs is also promising as an electron transport device is that Ga
When compared with As and the like, (1) the electron peak velocity is high, (2) the electron low electric field mobility is high, (3) the ohmic electrode is easy to take, and the contact resistance is low, (4).
You can expect a larger overshoot of electron velocity,
(5) Noise caused by valley scattering is small, (6) Interfacial characteristics with an insulator are relatively good, and the fact that the above-mentioned two-dimensional electron gas device can be realized is one of the major reasons. Is one.

At present, the field-effect transistor using the two-dimensional electron gas at the InGaAs / InAlAs interface is regarded as a promising high-performance microwave millimeter-wave device, and researches and developments have been made in various fields. In particular, its effectiveness as a low noise element has been confirmed at an experimental level, and for example, IEE Microwave and Guided Wave Letters, Vol. 1, No. 7, p. 114 (IEEE) MICROWAVE AND GUIDE
D WAVE LETTERS, VOL. 1, NO.
5, p. 114) in Doo et al. (KH Duh et.
al. ), At room temperature, at 94 GHz.
, A noise figure of 1.2 dB and an accompanying gain of 7.2 dB have been confirmed.

FIG. 10 shows the structure and FIG. 11 shows the band diagram of the conduction band. These lattice-matched on an InP substrate system, namely _{In 0. 5 3 Ga 0.} 4 7 As
/ In _0. In _{5 2} Al _{0. 4 8} material system which defines the In composition so that As has been making a device. In ₀ In this _{system. 5 3} Ga _{0. 4 7} Although As layer in the two-dimensional electron gas is formed, Incidentally intended to further improve characteristics, for example, eye E. E. E. Electron Device Letters , Vol. 10, No. 3, p. 114 (IEEEEELC
TRON DEVICE LETTERS, VOL. 1
0, NO. 3, p. 114) Ning et al. (GING)
et al. ), An attempt has been made to improve the device characteristics by setting the In composition in this portion to a value of 0.53 or more. However, the InP substrate and InGaAs having an In composition of 0.53 or more have a lattice mismatch, and the film thickness that can be grown for crystal growth is limited by the In composition ratio, so the thickness of the InGaAs channel is limited. The structure is shown in FIG. 12 and the band diagram is shown in FIG.

Further, InAs is formed in an InGaAs channel.
A device intended to form a two-dimensional electronic layer having a high confinement effect by inserting a thin layer of the above is reported by Akasaki et al. In IEICE Technical Report 91, 321, page 13. There is.

[0006]

SUMMARY OF THE INVENTION InA described in the conventional example
The 1As / InGaAs heterojunction two-dimensional electron gas transistor uses an InGaAs layer as a channel. The In composition in InGaAs is 0.53 when lattice-matched to the InP substrate, but strain is introduced into the crystal within the film thickness range where misfit transition does not occur in the crystal even if set to 0.53 or more. Good crystals are obtained in the prepared form. InGaAs
The effective mass of traveling electrons inside becomes smaller as the In composition increases. In order to reduce the electron effective mass of the channel electrons as much as possible, it is effective to increase the In composition as much as possible within the range where transition does not occur. However, the critical film thickness where transition does not occur becomes thinner as the In composition increases, and depending on the composition, a sufficient two-dimensional electron gas density for obtaining good device characteristics cannot be obtained. Further, the band gap of the channel becomes smaller as the proportion of In becomes larger, and the probability of collision ionization occurring under a high electric field increases, resulting in a hindrance to the high speed. InGaAs as shown in the conventional example
In the structure in which the InAs layer is inserted in the channel, the electrons in the InAs become hot electrons during high electric field operation, and impact ionization easily occurs. That is, for example, the drain conductance may be increased, which may hinder the improvement of the device performance.

[0007]

The present invention solves the above problems and provides a device structure which provides good device characteristics. The specific intent of the present invention is that InAlAs / In
In a GaAs-based two-dimensional electron gas field effect transistor, when the transistor operates, the In composition of the region where the channel electrons have the largest distribution probability in the quantum well is increased to increase the effective drift velocity of the channel traveling electrons. It is an attempt to improve. However, under a high electric field, it is necessary to realize an In composition ratio such that the effect of impact ionization is not so remarkable.

The field effect transistor according to the present invention is a field effect transistor in which a buffer layer, a non-doped channel layer, and an electron supply layer doped with an n-type impurity are stacked in this order on a semi-insulating InP substrate. The non-doped channel layer is an In _x Ga _{1 -x} As layer (0.4 <x
<0.9), and the In composition ratio x changes stepwise in the layer thickness direction. By setting the In composition at a desired position to be large, the channel electrons in the device can travel. It is intended to achieve improved properties.

[0009]

The two-dimensional electrons in the channel are not uniformly distributed in the quantum well, and the probability of the existence of electrons inevitably becomes low near both the electron supply layer and the substrate side interface as seen from the channel. Therefore, the In composition in the vicinity does not significantly affect the two-dimensional electron gas concentration or the effective drift velocity of electrons even if it is not intentionally increased.

In the present invention, by increasing the In composition near the center of the channel layer as compared with the In composition on the surface side and the substrate side of the channel InGaAs layer, the electron concentration of the channel is improved and the entire channel travels. This makes it possible to improve the average drift velocity of electrons. That is, an effect equivalent to increasing the effective In composition of the channel InGaAs layer can be obtained.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a sectional view showing an example of the structure of a semiconductor device of the present invention (claim 1).

Non-doped I on the semi-insulating InP substrate 11
n _{0. 5 2} Al _0. In _{4 2} As layer 12 is 800nm thick, a first undoped _{In 0. 6 Ga 0. 4} As layer 13
a is 5 nm thick and the second undoped In _0.8 Ga
_0. In ₂ As layer 13b is 5nm thick, the third non-doped _{In 0. 6 Ga 0. 4} As layer 13c is 5nm thick, non-doped _{In 0. 5 2 Al 0.} 4 8 As layer 14 The n-type S has a thickness of 3 nm and a concentration of 2 × 10 ¹⁸ cm ^−3.
i doped an In _0. In _{5 2} Al _{0. 4 8} As the thickness of the electron supply layer 15 is 30 nm, a non-doped In _{0. 5 2} A
_. l ₀ in _{4 8} As Schottky layer 16 is 20nm thick, 5 × 10 ^{1 8} cm ^- is In ₀ which is Si-doped n-type to a concentration of _{³ 5} ³ Ga _{0 4 7} As cap layer _17.. Three
Crystals are sequentially grown with a thickness of 0 nm.

A source electrode 18 and a drain electrode 19 which are ohmic electrodes are formed on the n-type InGaAs cap layer 17.
Is formed by vapor deposition of AuGe and Ni and subsequent heat treatment alloy, and the Schottky composed of Ti, Pt, and Au is formed in the recess region etched and removed halfway through the non-doped InAlAs Schottky layer 16 between the ohmic electrodes. The gate electrode 20 is formed.

In the field effect transistor of this embodiment, a two-dimensional electron gas is mainly formed in the quantum well formed by the first, second and third non-doped InGaAs layers 13a, 13b and 13c, respectively. The two-dimensional electron gas operates as a channel. The two-dimensional electron gas exists in the quantum well extending over these three layers with a certain distribution, but the center of the electron distribution exists in the second non-doped InGaAs layer 13b which is near the center of the channel as compared with the vicinity of both interfaces.

The In composition of the second non-doped InGaAs layer 13b has the In composition of the first non-doped InGaAs layer 13
It is 0.8, which exceeds 0.6, which is the In composition of a and the third non-doped InGaAs layer 13c. Therefore, most of the traveling electrons operate at high speed reflecting this In concentration and contribute to the improvement of device characteristics. . FIG. 2 shows the energy band diagram of the conduction band just below the gate and the distribution state of electrons in the device structure of this example in association with the In composition ratio in the channel.

The In composition of the InGaAs layers 13a, 13b, 13c used for the channel is set to 0.6 in the present embodiment, and the first and third non-doped InGa are set.
An InGaAs layer having a setting of 0.8 between the As layers is used for the second non-doped channel layer 13b, but the present invention limits the In composition ratio in the second non-doped InGaAs layer 13b to this value. Instead, it is possible to further increase the In composition ratio in the range where the misfit transition does not occur as the strained layer.

Similarly, the first and third non-doped InGa
It is possible to change the In composition of the As layers 13a and 13c as well, so that the In.
You may choose 53. In particular, regarding the first and third non-doped InGaAs layers 13a and 13c, the In
Conversely, the composition ratio may be selected to a value smaller than 0.53. By doing so, the strain of the channel of the channel layer is relaxed, the critical film thickness is increased, and the total channel film thickness can be increased.

Embodiment 2 FIG. 3 is a sectional view showing an example of the structure of a semiconductor device according to (claim 2) of the present invention.

The semi-insulating InP substrate 111 on the undoped In _{0 in.} In _{5 2} Al _{0. 4 8} As layer 112 is 800nm thick, a first undoped In _{0. 6} Ga _{0. 4} As layer 113a is 3 nm, Second non-doped In _0.8 Ga
_{0. 2} As layer 113b is 5nm thick, a third undoped In _{0. 7} Ga _0. In ₃ As layer 113c is 4nm thick, a fourth non-doped _{In 0. 6 Ga 0. 4} As layer 1
13d is a thickness of 3 nm, a non-doped In _{0. 5 2} As
_0. In _{4 8} As layer 114 is 3nm thick, 2 × 10 ^{1 8}
cm _^-. In ₀ which is Si-doped n-type to a concentration of ³ _{5 2}
Al _{0. 4 8} In As electron supply layer 115 is 30nm thick, non-doped _{In 0. 5 2 Al 0.} 4 8 As Schottky layer 116 is 20nm thick, 5 × 10 ^{1 8} cm
_^-. A concentration of ³ were Si doped n-type an In _{0 5 3} Ga
_The 0.47 As cap layer 117 is successively grown to a thickness of 30 nm.

A source electrode 118 and a drain electrode 119 are formed of AuGe and Ni on the n-type InGaAs cap layer 117.
It is formed by alloying by vapor deposition and heat treatment of
A Schottky gate electrode 120 made of Ti, Pt, and Au is formed between the ohmic electrodes in a recess etched and removed halfway through the non-doped InAlAs Schottky layer 116.

In the field effect transistor of this embodiment, the first, second, third and fourth non-doped InGaA are used.
s layers 113a, 113b, 113c, 113d
A two-dimensional electron gas is formed in the quantum well formed by
The two-dimensional electron gas operates as a channel. The two-dimensional electron gas has a certain distribution in the quantum wells extending over these four layers, but in the second non-doped InGaAs layer 113b to the third non-doped InGaAs layer 113c, which is near the center of the channel as compared with the vicinity of both interfaces. The center of electron distribution exists.

Third non-doped InGaAs layer 113c
In composition in the first non-doped InGaAs layer 1
13a and the In composition of the fourth non-doped InGaAs layer 113d are 0.7, which exceeds the In composition of 0.6.
The In composition of the non-doped InGaAs layer 113b is set to 0.8, which exceeds it. By making the structure of the quantum well in this way, the center of the channel electrons accumulated therein shifts to the substrate side of the channel, and the electron distribution becomes effective when the operating bias of the device operates near the pinch-off. Most of the traveling electrons are In
It operates at high speed by reflecting the concentration distribution and guarantees improvement of device characteristics. FIG. 4 shows a band diagram immediately below the gate and a distribution state of electrons in the device structure of this example in association with the In composition ratio in the channel.

The In composition of the InGaAs layers 113a, 113b, 113c, 113d used for the channel is set to 0.6 in this embodiment, and the In composition is set to 0.7 between the first and fourth non-doped InGaAs layers. Setting InGaA
s layer as the third non-doped channel layer 113c and 0.
Although the InGaAs layer of 8 settings is used for the second non-doped channel layer 113b, the present invention does not limit the In composition ratio in these non-doped InGaAs layers to this value, but the In composition ratio of each layer. x1, x2,
The magnitude relationship of x3 and x4 x1 <x2 and x4 <x3 <x2
Is guaranteed, the In composition ratio can be appropriately changed within the range where misfit transition does not occur in the strained layer.

Similarly, first and fourth non-doped InGa
The In composition of the As layers 113a and 113d can be changed, and 0.53 that lattice-matches the InP material may be selected. In particular, the In composition ratio of the first and fourth non-doped InGaAs layers 113a and 113d may be conversely selected to be smaller than 0.53. By doing so, the critical film thickness of the channel is increased and the total channel film thickness can be increased.

Example 3 An example of the structure of a semiconductor device to which the present invention (claim 3) is applied will be shown. The structural diagram is the same as that of the second embodiment (FIG. 3), but In
The composition ratios of the GaAs layers are different.

The semi-insulating InP substrate 111 the undoped In _{0 on.} In _{5 2} Al _{0. 4 8} As layer 112 is 800nm thick, a first undoped In _{0. 6} Ga _{0. 4} As layer 113a is 3nm of Second thick undoped In
_{0. 7} Ga _{0. 3} in As layer 113b is 4nm thick, the third non-doped _{In 0. 8 Ga 0. 2} As layer 113c is 5nm thick, a fourth non-doped In _{0. 6} Ga
_0.4 As layer 113d has a thickness of 3 nm and is undoped I
_{.. n 0 5 2 Al 0} 4 at ₈ As layer 114 is 3nm ^{thick, 2 × 10 1 8 cm -} . In 0 which is Si-doped n-type to a concentration of ³ _{5 2} Al _{0 .4 8} As electronic The supply layer 115 has a thickness of 30 nm and is made of non-doped In 0.52 Al _.
At a thickness of _{0. 4 8} As Schottky layer 116 is ^{20nm, 5 × 10 1 8 cm} -.. 3 of In concentration is Si doped n-type to _{0 5 3} Ga _{0 4 7} As cap layer 117 is 30nm With the thickness of, the crystals are successively grown.

A source electrode 118 and a drain electrode 119 are formed of AuGe and Ni on the n-type InGaAs cap layer 117.
Of the non-doped InAlAs Schottky layer 1 formed between the ohmic electrodes.
The Schottky gate electrode 120 is formed by vapor deposition of, for example, Ti, Pt, and Au in the recess that has been etched and removed up to the middle of 16.

In the field effect transistor of this embodiment, the first, second, third and fourth non-doped InGaA are used.
s layers 113a, 113b, 113c, 113d
A two-dimensional electron gas is formed in the quantum well formed by
The two-dimensional electron gas operates as a channel. The two-dimensional electron gas has a certain distribution in the quantum wells extending over these four layers, but in the second non-doped InGaAs layer 113b to the third non-doped InGaAs layer 113c, which is near the center of the channel as compared with the vicinity of both interfaces. The center of electron distribution exists.

Second non-doped InGaAs layer 113b
In composition in the first non-doped InGaAs layer 1
13a and the In composition of the fourth non-doped InGaAs layer 113d. It is set to 0.7 which exceeds 0.6, and the In composition of the third non-doped InGaAs layer 113c is set to 0.8 which exceeds it. By making the structure of the quantum well in this way, the center of the distribution of the channel electrons accumulated in the quantum well shifts to the surface side of the channel, and the effective electron distribution is obtained when the device operating bias operates at a large current. Becomes Most of the traveling electrons operate at a high speed by reflecting such an In concentration distribution of the channel, thereby guaranteeing an improvement in device characteristics. FIG. 5 shows a band diagram and a distribution state of electrons just below the gate of the device structure in this example in association with the In composition ratio in the channel.

The In composition of the InGaAs layers 113a, 113b, 113c, 113d used for the channel is set to 0.6 in this embodiment, and the In composition is set to 0.7 between the first and fourth non-doped InGaAs layers. Setting InGaA
s layer as the second non-doped channel layer 113b, and 0.
InGaAs layer with 8 settings Third non-doped channel layer 1
13c, the present invention uses these non-doped I
The In composition ratio in the nGaAs layer is not limited to this value, and the In composition ratio x1, x2, x in each layer is not limited to this value.
The magnitude relationship between 3 and x4 is x1 <x2 <x3 and x4 <x3
Is guaranteed, the In composition ratio can be appropriately changed within the range where misfit transition does not occur in the strained layer.

Similarly, first and fourth non-doped InGa
The In composition of the As layers 113a and 113d can be changed, and 0.53 that lattice-matches the InP material may be selected. In particular, the In composition ratio of the first and fourth non-doped InGaAs layers 113a and 113d may be conversely selected to be smaller than 0.53. By doing so, the critical film thickness of the channel is increased and the total channel film thickness can be increased.

Embodiment 4 FIG. 6 is a sectional view showing an example of the structure of a semiconductor device of the present invention (claim 4).

The semi-insulating InP substrate 211 the undoped In _{0 on.} In _{5 2} Al _{0. 4 8} As layer 212 of 800nm thickness, a first undoped In _{0. 6} Ga _{0. 4} As layer 213a is 3nm of Second thick undoped In
_{0. 8} Ga _{0. 2} As layer 213b is in a thickness of 3 nm, the third non-doped _{In 0. 7 2 Ga 0.} 2 8 As layer 213
c is a thickness of 3 nm, the fourth non-doped In _{0. 6 5} G
a _{0. 3} in ₅ As layer 213d is 3nm thick, a fifth undoped _{In 0. 6 Ga 0. 4} As layer 213e is 3nm
_.. With a thickness of, undoped In _{0 5 2} Al _{0 4 8} In As layer 214 is 3nm ^{thick, 2 × 10 1 8 cm -} . In 0 which is Si-doped n-type to a ^third concentration _{5 2} Al _0.48 A
s to a thickness of the electron supply layer 215 is an example 30 nm, undoped _{In 0 5 2 Al 0 4 8} As Schottky layer 216 of 20nm ^{thickness, 5 × 10 1 8 cm -} .. to ³ n-type to a concentration of Si-doped in _{0. 5 3} Al _0. in _{4 7} as cap layer 217 is 30nm thick are sequentially grown respectively.

The source electrode 218 and the drain electrode 219 are AuGe and Ni on the n-type InGaAs cap 217.
Of the non-doped InAlAs between the ohmic electrodes.
A Schottky gate electrode 202 made of vapor deposition of Ti, Pt, and Au is formed inside the recessed region that is etched and removed halfway through the Schottky layer 216.

In the field effect transistor of this embodiment, the first, second, third, fourth and fifth non-doped In are used.
GaAs layers 213a, 213b, 213c, 2 respectively
Two-dimensional electron gas is formed in the quantum well formed by 13d and 213e, and this two-dimensional electron gas operates as a channel. The two-dimensional electron gas has a certain distribution in the quantum well extending over these five layers, but in the second, third, and fourth non-doped InGaAs layers 213b, 213c, and 213d, which are near the center of the channel as compared with the vicinity of both interfaces. There is a center of electron distribution in.

Fourth non-doped InGaAs layer 213d
In composition in the first non-doped InGaAs layer 2
The In composition of the 13a and the fifth non-doped InGaAs layer 213e is 0.65, which exceeds 0.6, and the In composition of the third non-doped InGaAs layer 213c is set to 0.72, which exceeds it. Furthermore, the In composition of the second non-doped InGaAs layer 213b is set to 0.8, and the In composition is the highest in the channel. By making the structure of the quantum well in this way, the distribution center of the channel electrons accumulated therein shifts to the substrate side of the channel, and the electron distribution becomes effective when the device operates near the pinch-off. Most of the traveling electrons operate at a high speed by reflecting such an In concentration distribution of the channel, thereby guaranteeing an improvement in device characteristics. FIG. 7 shows a band diagram and a distribution state of electrons just below the gate of the device structure directly below the gate of the device structure in this example in association with the In composition ratio in the channel.

The In composition of the InGaAs layers 213a, 213b, 213c, 213d, and 213e used for the channel is set to 0.6 in this embodiment, and the In composition is 0 between the first and fifth non-doped InGaAs layers. The InGaAs layer set to .65 is used as a fourth non-doped channel layer 213.
d, the InGaAs layer of 0.72 setting to the third non-doped channel layer 213c, and the InGaA of 0.8 setting.
Although the s layer is used as the second non-doped channel layer 213b, the present invention does not limit the In composition ratio in these non-doped InGaAs layers to this value, and the In composition ratios x1 and x2 of the respective layers are not limited to this value. , X3, x4, and x5, if the magnitude relationship x1 <x2 and x5 <x4 <x3 <x2 are guaranteed, the In composition ratio is appropriately changed within the range where misfit transition does not occur as the strained layer. It is possible.

Similarly, first and fifth non-doped InGa
The In composition of the As layers 213a and 213e can be changed, and 0.53 that lattice-matches the InP material may be selected. In particular, the In composition ratio of the first and fifth non-doped InGaAs layers 213a and 213e may be selected to a value smaller than 0.53. By doing so, the critical film thickness of the channel is increased, and it is possible to increase the total film thickness of the channel.

Example 5 A structure of an example of a semiconductor device of the present invention (claim 5) is shown.
The structure is the same as in FIG. 6 of the fourth embodiment, but the composition relation of the InGaAs layer is different.

The semi-insulating InP substrate 211 on the undoped an In _0. In _{5 2} Al _{0. 4 8} As layer 212 of 800nm thickness, a first undoped _{In 0. 6 Ga 0. 4} As layer 213a is 3nm of Second thick undoped In
_{0. 7} Ga _{0. 3} As layer 213b is a thickness of 3nm, the third non-doped _{In 0. 8 Ga 0. 2} As layer 213c is 3nm thick, a fourth non-doped In _{0. 7} Ga
_{0. 3} As layer 213d is a thickness of 3nm, the fifth undoped _{In 0. 6 Ga 0. 4} As layer 213e is 3nm thick, non-doped _{In 0. 5 2 Al 0.} 4 8 As layer 21
4 is 3 nm thick and has a concentration of 2 × 10 ¹⁸ cm ⁻³
In ₀ the mold to the _Si-doped. In _{5 2} Al _{0. 4 8} As electron supply layer 215 is 30nm thick, doped In
_{0. 5 2 Al 0. 4} 8 As Schottky layer 216 is 20
S with n-type thickness of 5 × 10 ¹⁸ cm ^-3
i doped In _{0. 5 3} Ga _0. In _{4 7} As cap layer 217 is 30nm thick are sequentially grown respectively.

The source electrode 218 and the drain electrode 219 are AuGe and N on the n-type InGaAs cap layer 217.
A Schottky gate electrode 220 made of Ti, Pt, and Au is formed in the recess region, which is formed by the vapor deposition of i and the subsequent heat treatment alloy and is etched and removed to the middle of the non-doped InAlAs Schottky layer 216 between the ohmic electrodes. Has been formed.

In the field effect transistor of this embodiment, the first, second, third, fourth and fifth non-doped In are used.
GaAs layers 213a, 213b, 213c, 2 respectively
Two-dimensional electron gas is formed in the quantum well formed by 13d and 213e, and this two-dimensional electron gas operates as a channel. The two-dimensional electron gas has a certain distribution in the quantum well extending over these five layers, but in the second, third, and fourth non-doped InGaAs layers 213b, 213c, and 213d, which are near the center of the channel as compared with the vicinity of both interfaces. There is a center of electron distribution in.

Fourth non-doped InGaAs layer 213b
And 213d have the first In composition of the first undoped InG
It is 0.7 which exceeds 0.6 which is the In composition of the aAs layer 213a and the fifth non-doped InGaAs layer 213e. Furthermore, I of the third non-doped InGaAs layer 213c
The n composition is set to 0.8, and the In composition is highest in the channel. By making the structure of the quantum well in this way, the distribution center of the channel electrons accumulated therein shifts to the center, and the device has an effective electron distribution in operation. Most of the traveling electrons operate at a high speed by reflecting such an In concentration distribution of the channel, thereby guaranteeing an improvement in device characteristics. FIG. 8 shows a band diagram immediately below the gate and a distribution state of electrons in the device structure of this example in association with the In composition ratio in the channel.

The In composition of the InGaAs layers 213a, 213b, 213c, 213d, and 213e used for the channel is set to 0.6 in this embodiment, and is 0 between the first and fifth non-doped InGaAs layers. The second non-doped channel layer 213b with the InGaAs layer set to 0.7.
And a fourth non-doped channel layer 213d, and an InGaAs layer with 0.8 setting as the third non-doped channel layer 21.
3c, the present invention uses these non-doped In
The In composition ratio in the GaAs layer is not limited to this value, but the In composition ratio x1, x2, x in each layer
The magnitude relationship of 3, x4, x5 is x1 <x2 <x3, x5 <
If x4 <x3 is guaranteed, the In composition ratio can be appropriately changed within a range where misfit transition does not occur in the strained layer.

Similarly, first and fifth non-doped InGa
The In composition of the As layers 213a and 213e can be changed, and 0.53 that lattice-matches the InP material may be selected. In particular, the In composition ratio of the first and fifth non-doped InGaAs layers 213a and 213e may be selected to a value smaller than 0.53. By doing so, the critical thickness of the channel increases, and the total channel thickness can be increased.

Example 6 The structure showing an example of the structure of the semiconductor device of the present invention (claim 6) is the same as that of FIG. 6 of Example 4, but the composition relation of the InGaAs layer is different.

The semi-insulating InP substrate 211 the undoped In _{0 on.} In _{5 2} Al _{0. 4 8} As layer 212 of 800nm thickness, a first undoped In _{0. 6} Ga _{0. 4} As layer 213a is 3nm of Second thick undoped In
_{0. 6 5} Ga _{0. 3} in ₅ As layer 213b is 3nm thick, the third non-doped _{In 0. 7 2 Ga 0.} 2 8 As layer 213c is 3nm thick, a fourth doped In
_{0. 8} Ga _0. In ₂ As layer 213d is 3nm thick, a thickness of the fifth undoped _{In 0. 6 Ga 0. 4} As layer 213e is 3nm, a non-doped _{In 0. 5 2 Al 0.} 4 8
The As layer 214 has a thickness of 3 nm and has a thickness of 2 × 10 ¹⁸ cm ⁻³
n-type doped the In _0. In _{5 2} Al _{0. 4 8} As electron supply layer 215 is 30nm thick, doped In
_{0. 5 2 Al 0. 4} 8 As Schottky layer 216 is 20
S with n-type thickness of 5 × 10 ¹⁸ cm ^-3
i doped In _{0. 5 3} Ga _0. In _{4 7} As cap layer 217 is 30nm thick are sequentially grown respectively.

A source electrode 218 and a drain electrode 219 are formed on the n-type InGaAs cap layer 217 by using AuGe and Ni.
Of non-doped InAlAs between the ohmic electrodes.
A Schottky gate electrode 220 composed of Ti, Pt, and Au is formed inside the recess region that is etched and removed halfway through the Schottky layer 216.

In the field effect transistor of this embodiment, the first, second, third, fourth and fifth non-doped In are used.
GaAs layers 213a, 213b, 213c, 2 respectively
Two-dimensional electron gas is formed in the quantum well formed by 13d and 213e, and this two-dimensional electron gas operates as a channel. The two-dimensional electron gas has a certain distribution in the quantum well extending over these five layers, but in the second, third, and fourth non-doped InGaAs layers 213b, 213c, and 213d, which are near the center of the channel as compared with the vicinity of both interfaces. There is a center of electron distribution in.

Second non-doped InGaAs layer 213b
In composition in the first non-doped InGaAs layer 2
The In composition of the 13a and the fifth non-doped InGaAs layer 213e is 0.65, which exceeds 0.6, and the In composition of the third non-doped InGaAs layer 213c is set to 0.72, which exceeds it. Furthermore, the In composition of the fourth non-doped InGaAs layer 213d is set to 0.8, and the In composition is the highest in the channel. By making the structure of the quantum well in this way, the distribution center of the channel electrons accumulated in it shifts to the surface side of the channel, and the electron distribution becomes effective when the device operation bias operates at high current. . Most of the traveling electrons operate at a high speed by reflecting such an In concentration distribution of the channel, thereby guaranteeing an improvement in device characteristics. FIG. 9 shows a band diagram immediately below the gate and a distribution state of electrons in the device structure of this example in association with the In composition ratio in the channel.

The In composition of the InGaAs layers 213a, 213b, 213c, 213d, and 213e used for the channel is set to 0.6 in this embodiment, and is 0 between the first and fifth non-doped InGaAs layers. The second non-doped channel layer 213 with the InGaAs layer of .65 setting
b, the InGaAs layer of 0.72 setting as the third non-doped channel layer 213c, and the InGaA of 0.8 setting.
Although the s layer is used as the fourth non-doped channel layer 213d, the present invention does not limit the In composition ratio in these non-doped InGaAs layers to this value, and the In composition ratios x1 and x2 of the respective layers are not limited to this value. , X3, x4, x5, if the magnitude relationship x1 <x2 <x3 <x4, x5 <x4 is guaranteed, the In composition ratio should be appropriately changed within the range where misfit transition does not occur in the strained layer. Is possible.

Similarly, first and fifth non-doped InGa
The In composition of the As layers 213a and 213e can be changed, and 0.53 that lattice-matches the InP material may be selected. In particular, the In composition ratio of the first and fifth non-doped InGaAs layers 213a and 213e may be selected to a value smaller than 0.53. By doing so, the critical film thickness of the channel is increased, and it is possible to increase the total film thickness of the channel.

As described above, the concrete examples of the present invention have been presented from the first embodiment to the sixth embodiment. In these embodiments, specific materials and specific specific numbers have been described, but this is for ease of understanding. For example, Ti / Pt can be used as a metal for a gate electrode. It is not limited to / Au but may be any as long as it forms a Schottky junction, and this metal composition does not change the essential effects of the present invention. Also, the thickness of each layer is not necessarily limited to that shown here as an example.

Further, in the present embodiment, the impurity distribution of the electron supply layer is uniformly doped, but it is not limited to this. For example, the impurity concentration may be changed stepwise in the depth direction, or the impurity concentration may be changed. It is also possible to localize the distribution (eg planar dope).

[0056]

According to the present invention, InAlAs / InGa
In the two-dimensional electron gas FET using the As heterojunction, the channel electron concentration can be improved, and the effective mass of the channel traveling electrons can be reduced and the effective drift velocity can be improved. This is reflected in the improvement of the high frequency operation in the device, and realizes the improvement of the device characteristics such as the cutoff frequency, the noise characteristic, and the high output characteristic.

[Brief description of the drawings]

FIG. 1 is a structural sectional view for explaining the present invention.

FIG. 2 is a diagram showing a band diagram for explaining the present invention in correspondence with an In composition ratio of a channel.

FIG. 3 is a structural sectional view for explaining the present invention.

FIG. 4 is a diagram showing a band diagram for explaining the present invention in association with a channel In composition ratio.

FIG. 5 is a diagram showing a band diagram for explaining the present invention in association with a channel In composition ratio.

FIG. 6 is a structural sectional view for explaining the present invention.

FIG. 7 is a diagram showing a band diagram for explaining the present invention in association with a channel In composition ratio.

FIG. 8 is a diagram showing a band diagram for explaining the present invention in association with the In composition ratio of a channel.

FIG. 9 is a diagram showing a band diagram for explaining the present invention in association with the In composition ratio of a channel.

FIG. 10 is a structural cross-sectional view for explaining a conventional example.

FIG. 11 is a diagram showing a band diagram for explaining a conventional example in association with the In composition ratio of the channel.

FIG. 12 is a structural cross-sectional view for explaining a conventional example.

FIG. 13 is a diagram showing a band diagram for explaining a conventional example in association with the In composition ratio of the channel.

[Explanation of symbols]

11, 111, 211 semi-insulating InP substrate 12, 112, 212 non-doped In _{0. 5 2} Al
_{0. 4 8} As buffer layer 13a, 113a, 213a first non-doped InG
aAs layers 13b, 113b, 213b Second undoped InG
aAs layer 13c, 113c, 213c Third non-doped InG
aAs layer 113d, 213d fourth undoped InGaAs layer 213e fifth undoped InGaAs layer 14, 114, 214 non-doped In _{0. 5 2} Al
_{0. 4 8} As spacer layer 15,115,215 n-type doped In _{0. 5 2} A
l _{0. 4 8} As electron supply layer 16, 116, 216 non-doped In _{0. 5 2} Al
_{0. 4 8} As Schottky layer 17,117,217 n-type doped InGaAs cap layer 18, 118, 218 source electrodes 19, 119, 219 a drain electrode 20, 120, 220 gate electrode 411,511 semi-insulating InP substrate 412, 512a doped In _{0. 5 2} Al
_{0. 4 8} As buffer layer 512b doped _{In 0. 5 3 Ga 0.} 4 7 As the smoothing layer 413,513 undoped InGaAs channel layer 414, 514 doped _{In 0. 5 2 Al 0.} 4 8
As spacer layer 415,515 n-type doped _{In 0. 5 2 Al 0.} 4 8
As electron supply layer 416,516 undoped _{In 0. 5 2 Al 0.} 4 7
As Schottky layer 417, 517 n-type doped InGaAs cap layer 418, 518 source electrode 419, 519 drain electrode 420, 520 gate electrode

Claims (6)

(57) [Claims] 1. A buffer layer on a semi-insulating InP substrate.
In a field effect transistor in which a non-doped channel layer and an n-type impurity-doped electron supply layer are stacked in this order, the non-doped channel layer is In _{x 1} Ga _{1 -x 1}
As layer, In _{x 2} Ga _{1 -x 2} As layer, In _{x 3} Ga
_{A 1-} x3As layer is laminated in this order from the buffer layer toward the electron supply layer, and
0.4 <x1 <x2 <0.9 and 0.4 <x3 <x2 <
A field-effect transistor characterized by satisfying 0.9. 2. A buffer layer on a semi-insulating InP substrate.
In a field effect transistor in which a non-doped channel layer and an electron supply layer doped with an n-type impurity are stacked in this order, the non-doped channel layer is In _{x 1} Ga.
_{1 - x 1} As _{layer, In x 2 Ga 1 - x} 2 As layer, In
_{The structure is such that an x 3} Ga _{1 -x 3} As layer and an In _{x 4} Ga _{1 -x4} As layer are stacked in this order from the buffer layer to the electron supply layer, and 0.4 <x1 <x
A field-effect transistor characterized by satisfying 2 <0.9 and 0.4 <x4 <x3 <x2 <0.9. 3. A buffer layer on a semi-insulating InP substrate.
In a field effect transistor in which a non-doped channel layer and an electron supply layer doped with an n-type impurity are stacked in this order, the non-doped channel layer is In _{x 1} Ga.
_{1 - x 1} As _{layer, In x 2 Ga 1 - x} 2 As layer, In
_{The structure is such that an x 3} Ga _{1 -x 3} As layer and an In _{x 4} Ga _{1 -x4} As layer are stacked in this order from the buffer layer to the electron supply layer, and 0.4 <x1 <x
A field-effect transistor characterized by satisfying 2 <x3 <0.9 and 0.4 <x4 <x3 <0.9. 4. A buffer layer on a semi-insulating InP substrate.
In a field effect transistor in which a non-doped channel layer and an electron supply layer doped with an n-type impurity are stacked in this order, the non-doped channel layer is In _{x 1} Ga.
_{1 - x 1} As _{layer, In x 2 Ga 1 - x} 2 As layer, In
_{x 3} Ga _{1 - x 3} As _{layer, In x 4 Ga 1 - x} 4 As
Layer and In _{x 5} Ga _{1 -x 5} As layer are laminated in this order in the direction from the buffer layer to the electron supply layer, and 0.4 <x1 <x2 <0.9 and 0. Four
A field effect transistor, wherein <x5 <x4 <x3 <x2 <0.9 is satisfied. 5. A buffer layer on a semi-insulating InP substrate.
In a field effect transistor in which a non-doped channel layer and an electron supply layer doped with an n-type impurity are stacked in this order, the non-doped channel layer is In _{x 1} Ga.
_{1 - x 1} As _{layer, In x 2 Ga 1 - x} 2 As layer, In
_{x 3} Ga _{1 -x 3} As layer, In _{x 4} Ga _{1 -x4} As layer
And an In _{x 5} Ga _{1 -x 5} As layer are stacked in this order in the direction from the buffer layer to the electron supply layer, and 0.4 <x1 <x2 <x3 <0.9 and A field effect transistor characterized by satisfying 0.4 <x5 <x4 <x3 <0.9. 6. A buffer layer on a semi-insulating InP substrate.
In a field effect transistor in which a non-doped channel layer and an electron supply layer doped with an n-type impurity are stacked in this order, the non-doped channel layer is In _{x 1} Ga.
_{1 - x 1} As _{layer, In x 2 Ga 1 - x} 2 As layer, In
_{x 3} Ga _{1 -x 3} As layer, In _{x 4} Ga _{1 -x4} As layer
Layer and In _{x 5} Ga _{1 -x 5} As layer are stacked in this order in the direction from the buffer layer to the electron supply layer, and 0.4 <x1 <x2 <x3 <x4 <0.
9. A field effect transistor characterized by satisfying 9 and 0.4 <x5 <x4 <0.9.