JP2673393B2 - Waveform analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform analyzer such as a digital oscilloscope.

[0002]

2. Description of the Related Art Conventionally, in this type of waveform analysis apparatus, when data is acquired for a long time using a long memory, for example, when data for four screens is acquired, Y-axis data (voltage direction) is compressed. In addition, by thinning and displaying the X-axis data (time axis direction), it is possible to find a point to be observed in detail from this compressed display waveform and display it simultaneously as an enlarged waveform.

FIG. 4 shows the configuration of such a conventional waveform analysis apparatus. In FIG. 4, 1 is an AD converter, which stores the converted digital data in the acquisition memory 2 and transfers it to the display memory 5 by the memory address control circuit 3 and the memory transfer circuit 4. 6 is CPU
The CPU 6 performs thinning processing in the X-axis direction, and the Y-axis data compression circuit 7 compresses and displays the Y-axis data. At this time, the compression rate is × 1/4 and the offset is fixed. From this compressed waveform,
As shown in, it is possible to select a portion to be magnified and observe, and simultaneously display it at a compression rate of 1.

[0004]

However, in the above-mentioned conventional waveform analyzer, the data in the time axis direction is compressed by thinning (1/2 screen for 2 screens, 1/4 screen for 4 screens). However, there is a problem that it is difficult to observe minute changes in the time axis direction on one screen. Further, since the CPU performs the compression in the time axis direction by the thinning processing, there is a problem that the processing takes a long time.

The present invention solves such a conventional problem, and is an excellent waveform analysis capable of displaying the data captured for up to four screens on the same screen without compressing in the time axis direction. The purpose is to provide a device.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a waveform analysis apparatus that converts an input signal into a digital signal.
From the AD converter that converts to a digital signal and this AD converter
A memory for storing digital data for a plurality of screens to be output, and a bit for storing the stored digital data are compressed.
The data in the voltage axis direction is compressed to 1/4 times, 1/2 times, or 1 time, and at the same time, it corresponds to the display position on the screen.
A data compression circuit for adding an offset bit and a CPU for controlling the offset bit and managing the address of the memory are provided.

[0007]

Therefore, according to the present invention, data for up to four screens can be displayed on one screen without being compressed in the time axis direction. Further, since the processing by the CPU can be reduced, there is an effect that the capturing speed is improved.

[0008]

FIG. 1 shows the configuration of an embodiment of the present invention. Reference numeral 11 is an AD converter, which converts the input measurement signal into a digital signal. An acquisition memory 12 stores the converted digital signal. 13
Is a memory address control circuit, and 14 is a memory transfer circuit, which transfers the data in the acquisition memory 12 to the display memory 15. Reference numeral 16 denotes a CPU, which controls the memory address control circuit 13, the memory transfer circuit 14, and the display memory 15 and also controls the Y-axis data compression circuit 17
To output to the display circuit.

FIG. 2 shows the configuration of the Y-axis data compression circuit 17. This circuit has a Y-axis (voltage axis) compression ratio of x1, x1
This is a circuit that can be divided into / 2 and × 1/4, and at the same time control the offset bit from the CPU 16. When normal display is selected, × 1 is selected, and when two screens of data are displayed on the same screen, × 1/2 is selected. Select. When x1 / 2 is selected, the upper half of the screen is set to the offset bit "1" and the lower half is set to the offset bit "0".

Next, the operation of the above embodiment will be described.
The measurement signal digitized by the AD converter 11 is
It is stored in the acquisition memory 12, which is a high-speed memory. Here, the input data string is 8 bits. The acquisition memory 12 has a capacity of 64 kbite,
If the number of data per screen is 4 kbite, data for 16 screens can be stored at one time. next,
The data stored in the acquisition memory 12 is transferred to the display memory 15 by the memory transfer circuit 14 while the address is controlled by the memory address control circuit 13. The display memory 15 also has the same capacity as the acquisition memory 12 and can store a maximum of 64 kbits of data, but here, 4 screens of data 4 kbits x 4 = 16 kbites are transferred to the display memory 15. And Then, under the control of the CPU 16, the data is sent from the display memory 15 to the Y-axis data compression circuit 17 by dividing one screen into four times.

Now, the data group 4 kbite of the first screen is group A, the second screen is group B, the third screen is group C, and the fourth screen is group D.
Group. In order to individually display the data of the four groups on one screen as shown in FIG. 3, the data of the A, B, C, and D groups are compressed to 8 bits → 6 bits (× 1/4),
At the same time, an offset bit "1" or "0" corresponding to each display position is added to the MSB for 2 bits.
An example of such a data structure is shown below.

MSB LSB data bit string D ₈ D ₇ D ₆ D ₅ D ₄ D ₃ D ₂ D ₁ A group data 1 1 D ₈ D ₇ D ₆ D ₅ D ₄ D ₃ B group data 1 0 D ₈ D ₇ D ₆ D ₅ D ₄ D ₃ C group data 0 1 D ₈ D ₇ D ₆ D ₅ D ₄ D ₃ D group data 0 0 D ₈ D ₇ D ₆ D ₅ D ₄ D ₃

As described above, according to the above embodiment, the input data digitized by the AD converter 11 is stored in the acquisition memory 12 and the display memory 15, and the data is passed through the Y-axis data compression circuit 17 to 1 / It is possible to display data of four screen lengths on one screen by compressing the data four times and at the same time adding offset data of 2 bits by the CPU 16 and outputting to the display circuit.

[0014]

As is apparent from the above embodiment, the present invention makes almost no changes to the current hardware,
By changing the data processing sequence, it is possible to inexpensively realize a new function of displaying data for up to four screens on one screen. Further, the advantage of the conventional method can be left as it is as a function, and since the thinning operation of the data in the time axis direction by the CPU is eliminated, the processing by the CPU can be reduced and the fetching speed can be improved. Have an effect.

[Brief description of the drawings]

FIG. 1 is a block diagram of a waveform analysis device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a Y-axis data compression circuit in the same device.

FIG. 3 is a signal waveform diagram showing a screen display example in the same device.

FIG. 4 is a block diagram of a conventional waveform analysis device.

FIG. 5 is a signal waveform diagram showing a screen display example in a conventional example.

[Explanation of symbols]

 11 AD converter 12 acquisition memory 13 memory address control circuit 14 memory transfer circuit 15 display memory 16 CPU 17 Y-axis data compression circuit

Claims (1)

(57) [Claims] 1. A for converting an input signal into a digital signal.
A D converter, a memory for storing digital data for a plurality of screens output from the AD converter, a bit of the stored digital data is compressed, and data in the voltage axis direction is multiplied by 1/4 or 1 /. A data compression circuit that doubles or folds the data and adds an offset bit corresponding to the display position on the screen, and a CPU that controls the offset bit and manages the memory address
Waveform analysis device equipped with.