JP2665763B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an FET input type differential amplifier circuit.

[Prior Art] FIG. 3 is a connection diagram showing a basic form of an FET input type differential amplifier circuit. In the figure, reference numerals 1 and 2 denote FETs, and reference numerals 5 and 7 denote n.
pn transistor, 6 and 8 are load resistors respectively, 9 is a constant current circuit, 10 is a power supply line from a positive terminal of the power supply, 11 is a power supply line from a negative terminal of the power supply, and 12 is a signal line of the first signal. , 13 are signal lines for the second signal, and 14 is an output signal line.

The pinch-off voltage of the FET, that is, the value of Vgs when the drain-source current Ids becomes 0 by lowering the gate-source voltage Vgs while keeping the drain-source voltage Vds constant,
When the pinch-off current, that is, Vgs is kept constant and Vds is stepped up, Ids is saturated. The value of the saturated Ids (hereinafter, referred to as Idss) differs depending on each FET, and the FET1 in the circuit of FIG. If the hinch-off of FET2 and that of FET2 are different from each other, a DC offset occurs in the differential amplifier of FIG.

A conventional circuit for reducing such a DC offset is shown in FIG. 4, the same reference numerals as those in FIG. 3 denote the same or corresponding parts, and reference numerals 30 and 40 denote FETs connected in parallel to the FETs 2 and 1, respectively. FIG. 2 is an explanatory view for explaining the present invention, and FIG.
T30 and T30 will be described. In this case, the reference numerals 3 and 4 in FIG. An FET formed on the same wafer surface has a large cross-correlation between the pinch-off voltage and the pinch-off current, and the offset of the differential amplifier circuit is reduced by using the cross-correlation. In FIG. 2, the direction of the channel of the FET is defined as the Y axis, and the direction perpendicular to the Y axis is defined as the X axis.
Are formed adjacent to each other in the X-axis direction, and FETs 1 and 3 and FETs 2 and 4 are formed adjacent to each other in the Y-axis direction. In the case of FIG. 4, FETs 1 and 4 (in FIG.
40) are used by connecting FETs 2 and 3 (reference numeral 30 in FIG. 4) in parallel.

Since the difference between the characteristics of FETs 1 and 2 is corrected by the difference between the characteristics of FETs 30 and 40, the offset voltage of the circuit shown in FIG.
It is reduced from the offset voltage of the circuit shown.

[Problems to be Solved by the Invention] As described above, in the conventional circuit, FET1 and 40 and FET2 and 30 are cross-connected to each other, and wiring becomes difficult.
There is a problem that a large area is required for wiring. Even if the FET is made as small as possible, connecting two in parallel increases the capacitance between the gate and the substrate, making it impossible to cope with the recent trend of speeding up data processing.

An object of the present invention is to solve the above-mentioned problems of the conventional circuit and to obtain a differential amplifier circuit having a small offset voltage.

[Means for Solving the Problems] In the present invention, the F having the same pinch-off characteristics as the signal input FET
ET was connected as the load of the signal input FET.

[Operation] Since a load having a large Idss is connected to an FET having a large Idss, a large current is caused to flow through the FET and the Vgs thereof is reduced to correct the offset voltage.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a connection diagram showing an embodiment of the present invention. In FIG. 1, the same reference numerals as in FIG.
Reference numeral 4 denotes FETs connected as loads. 91,9
Reference numeral 2 denotes an FET constituting the constant current circuit 9, and reference numeral 93 denotes a bias voltage determined by a current mirror (not shown).

The configuration of FETs 3 and 4 with respect to FETs 1 and 2 is as described above with reference to FIG. 2, but as is clear from FIG.
Can be made very small because the applied voltage is low (for example, about 0.7 V).

For example, assuming that the pinch-off current Idss1 of FET1 is larger than the pinch-off current Idss2 of FET2, in the conventional circuit shown in FIG. 3, the gate-source voltage Vgs1 of FET1
Vgs1> Vgs2 compared to the gate-source voltage Vgs2 of FET2, and an offset voltage is generated. In the circuit of FIG. 1, however, the pinch-off current of FET3 is larger than the pinch-off current of FET4. 5, the current flowing through the npn transistor 7 decreases, and the current of the FETs 1 and 2 is changed so that Vgs1 = Vgs2. Since the current flowing through the FETs 3 and 4 is distributed from the constant current circuit 9, the effect of reducing the offset voltage can be obtained more than the compensation effect of the FETs 1 and 3 and the FETs 2 and 4.

Assuming that the operating points of the pinch-off current Idss are used for the FETs 1 and 2 in FIG. 1, the current value of the constant current circuit 9 is 2Idss
The FETs 91 and 92 pass Idss, respectively, and the FETs 3 and 4 have a pinch-off current larger than Idss (for example, 1.05 to 1.10 Idss). The collector voltage of npn transistor 5 is generally 1.4V
In order not to saturate this, the pinch-off currents of the FETs 3 and 4 are increased.

[Effects of the Invention] As described above, according to the present invention, the difference between the DC characteristics of the input FETs 1 and 2 is compensated by the difference between the DC characteristics of the load FETs 3 and 4,
The input offset voltage can be reduced, and the chip occupied area can be reduced because the withstand voltage of the load FETs 3 and 4 is low.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the configuration of the FET shown in FIG. 1, and FIG. 3 is a connection diagram showing a basic type of an FET input type differential amplifier circuit. FIG. 4 is a connection diagram showing a conventional circuit. 1 ... FET, 2 ... FET, 3 ... Load FET, 4 ... Load FE
T, 5 ... npn transistor, 7 ... npn transistor,
9 ... constant current circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] Assuming an XY orthogonal coordinate axis having a channel direction of an FET (field effect transistor) as a Y axis, FET1 and FET2 are formed adjacent to each other in the X-axis direction on the surface of the same wafer. FET3 is formed adjacent to the
Form FET4 adjacent to T2 in the Y-axis direction on the same side as FET3, connect FET1 and FET2 in parallel to the constant current circuit, input the first signal to the gate of FET1, and connect it to the gate of FET2. A differential amplifier circuit is formed by inputting the second signal, a series circuit of npn transistor 5 and FET3 is connected as a load of FET1, and an npn transistor 7 and FET are connected as a load of FET2.
4 is connected to the series circuit, the bases of npn transistors 5 and 7 are both connected to the collector of npn transistor 5, and the gates of FETs 3 and 4 are connected to their respective drains to form a differential amplifier. Semiconductor integrated circuit.