JP2663842B2 - Semiconductor light receiving element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light receiving element used for optical measurement and optical communication.

[0002]

2. Description of the Related Art In optical communication, coherent optical communication technology for transmitting information by modulating the frequency and phase of light has been studied instead of optical communication for transmitting information by intensity modulation of light. By utilizing the characteristics of light waves in this way, compared to the conventional intensity modulation method, the transmission distance can be extended (extreme spanning) and the density can be increased by division and multiplexing of the optical frequency. It is being studied as a capacity optical communication technology.

FIG. 1 shows an example of a coherent optical communication system.
0 is shown. FIG. 10 shows an example of a heterodyne detection system, which is divided into a transmission section for extracting a signal and a reception section for performing heterodyne detection and polarization diversity reception. The receiving unit is a polarization beam splitter (PBS) that separates into two orthogonal polarizations to compensate for the polarization state of the single-mode optical fiber cable, which is a transmission path, and a local oscillation optical laser diode (heterodyne detection) for heterodyne detection. LD), a 3 dB optical coupler that mixes the signal light and the local oscillation light (hereinafter, local light) separated into their respective polarization states and splits them into two lights that are shifted in phase by π, and converts the mixed light into electricity A balanced photodetector (Dual-PIN or Dual-PIN) in which two PIN photodiodes are connected in series to extract a beat signal
A Quad-PIN in which two PINs are integrated, and a low-noise preamplifier and a detection circuit.

In such a configuration of the receiving section, the minimum receiving sensitivity can be reduced by (1) increasing the output of the local light and (2) canceling out the intensity noise from the local LD by the balanced light receiving element. The quantum noise limit is reached, and higher sensitivity can be achieved.
Therefore, the characteristics required for a balanced light-receiving element for high sensitivity are that two PIN-PDs connected in series are optically and electrically equivalent, and that the characteristics (quantum efficiency, dark current , Junction capacitance, response speed, and S / N), and a monolithically integrated Dual-PIN is being studied to meet these requirements. FIG. 11 shows Du, which is an example of a balanced light receiving element.
A conventional example of al-PIN is shown. Semi-insulating InP substrate 1
It has a configuration in which two light receiving elements provided at an interval above are integrated. Each light receiving element has a carrier concentration of 1E15 cm−3 and a layer thickness of 2 μm on the semi-insulating substrate 1.
InP buffer layer 3, carrier concentration 3E15cm-3 layer thickness 2μ
m n ⁻ -InGaAs light absorbing layer 4 and finally n ⁻ -InP window layer 5 having a carrier concentration of 5E15 cm −3 and a thickness of 1.4 μm
And a 1E18 cm-3 p-InP region 6 formed in the window layer. Of these two light receiving elements,
The p-side electrode pulled out from one p-InP light receiving region is
By connecting to the n-type electrode provided on the n-InP window layer of the other light receiving element, the common electrode 8 on the output side of the Dual-PIN is formed. Here, the light receiving element composed of the n-side electrode and the common electrode is called an N element, and the light receiving element composed of the common electrode and the p-side electrode is called a P element.

[0005] In a balanced light receiving element having such a structure,
When the mixed light of the signal light and the local light having the phase shifted by π is simultaneously incident on the P element and the N element, the carrier photoelectrically converted by each element flows to the common electrode, and as a result, the balanced light receiving element The difference signal between the two is output to the output side of. For this reason, the intensity noise component of the light from the local light emitting LD can be canceled, and the quantum noise limit of the receiving sensitivity can be achieved. Here, in order to cancel the intensity noise of the local light LD, it is important that the outputs of the P element and the N element are equivalent as described above. Here two PIN-PD
Are monolithically integrated, and the P element and the common electrode serving as the n side electrode of the P element and the p side electrode of the N element are centered.
By arranging the N elements symmetrically, variation in quantum efficiency and variation in capacitance due to variation in epi thickness are suppressed to 1% or less, and a good balance characteristic is obtained.

However, what matters here is the dark current characteristic related to the noise characteristic. FIG. 12 shows dark current characteristics of each of the conventional P element and N element. As is apparent from FIG. 12, the dark current of the P element composed of the p-side electrode 9 and the common electrode 8 is 0.1 nA at Vr = 5 V, whereas the N element composed of the common electrode 8-n-side electrode 10 The element has a large difference of 0.5 nA. The cause of the imbalance in the dark current characteristics will be described with reference to FIG. The path on which the dark current flows on the P element side is only a path via a pn junction flowing from the p-side electrode 9 → p-InP region 6 → n-InP window layer 5 → common electrode 8 and is a normal PIN− Same as PD. on the other hand,
On the N element side, similarly to the P element, an n-side electrode 10 → n-InP window layer 5 → p-InP layer 6 → n-side electrode 10 → n− InP window layer 5 → n-InGaAs light absorbing layer 4 → n-InP buffer layer 3
→ Semi-insulating InP substrate 1 → n-InP buffer layer 3 → nI
nGaAs light absorbing layer 4 → n-InP window layer 5 → common electrode 8
Leakage current flows through the flowing substrate. This is D
Since the p-side electrode of the N element is common to the n-side electrode of the P element due to the structure of the ual-PIN, an electric field is applied between the n-side electrode of the N element and the n-side electrode of the P element. As a result, a leak current is generated between the n-type layer and the n-type layer. Accordingly, a difference in the dark current characteristics as shown in FIG. 8 is generated, and as a result, imbalance occurs in the noise characteristics, which causes deterioration of the minimum receiving sensitivity.

[0007]

In the above-mentioned prior art balanced light receiving element, the dark current characteristic of each of the P element and the N element of the conventional example is different from that of the P element constituted by the p-side electrode and the common electrode. When the current is 0.1 nA, the N element formed of the common electrode and the n-side electrode has a large difference of 0.5 nA. As a cause of the imbalance of the dark current characteristics, the path through which the dark current flows on the P element side is p-side electrode → p-InP → n
−Inp cap layer → only the path via the pn junction flowing to the common electrode, whereas the N element side has the n-side electrode → n-InP cap → p-InP layer → common electrode like the P element. In addition to the path via the flowing pn junction, the n-side electrode → n-InP cap layer → n-InGaAs light absorption layer →
n-InP Buffer → S. I. Substrate → n-InP
Buffer → n-InGaAs light absorption layer → n-In
A leakage current is applied through the substrate flowing from the P cap layer to the common electrode. This is because the p-side electrode of the N element is common to the n-side electrode of the P element due to the structure of the Dual-PIN.
An electric field is applied between the n-side electrode of the element and the n-side electrode of the P element,
As a result, a leakage current occurs between the n-type layer and the n-type layer via the substrate. Therefore, there is a problem that a difference in dark current characteristic is generated by the amount of the leak current component, resulting in imbalance in noise characteristic, which causes deterioration of minimum receiving sensitivity.

[0008]

According to the present invention, a first conductive type carrier block layer (Eg) is formed on a semi-insulating substrate (Eg1).
1), the second conductive buffer layer (Eg1), the second conductive light absorbing layer (Eg2), and the second conductive window layer (Eg1) are Eg1> E.
g2, and a device structure in which the first conductive region (Eg1) is partially provided in the window layer is formed on the semi-insulating substrate at an interval. A semiconductor light receiving element, characterized in that at least one formed structure and a second conductive light absorbing layer of the second element and a first conductive area of the first element are connected by a conductive metal. . In addition, the present invention provides a semiconductor device according to the present invention, wherein the second conductive buffer layer (Eg1), the second conductive light absorbing layer (Eg2), and the second conductive window layer (Eg1) are formed on the semi-insulating substrate (Eg1). A device structure in which a first conductive region (Eg1) is partially provided in the window layer and a heteroepitaxial layer sequentially formed under the condition of> Eg2, Two or more formed structures, and a first conductive region of the first element and a second conductive window layer of the second element have an element isolation groove reaching a semi-insulating substrate, and an element of aerial wiring A structure in which a first conductivity type impurity is implanted into a portion of a groove reaching the semi-insulating substrate of the first element and the second element in a structure in which the first element and the second element are arranged in series. A semiconductor light-receiving element, wherein the second conductive window layer of the second element is connected with a conductive metal, In the semiconductor light receiving element described above, the second conductive type buffer layer and the first conductive type region of the first element are connected by a conductive metal instead of the second conductive type window layer of the second element. The semiconductor light receiving device further includes a second conductive buffer layer and a first conductive region of the first device instead of the second conductive window layer of the second device. Characterized in that they are connected by a conductive metal.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 shows an embodiment of a semiconductor light receiving element according to the present invention. 2 (a) to 2 (d) and 3 (e) to 3 (h) show a method for manufacturing a semiconductor light receiving element of the present invention. Carrier concentration of 1E16 to 2E on semi-insulating InP substrate 1 by vapor phase epitaxy.
A p-InP carrier block layer 2 having a carrier concentration of 1E15 cm-3 and a layer thickness of 2 μm, a carrier concentration of 1E15 to 2E16 cm-3 and a layer thickness of 1 to 3 μm are preferred, and a carrier concentration of 1E15
The n-InP buffer layer 3 having a cm-3 layer thickness of 2 μm and a carrier concentration of 1E15 to 5E15 cm-3 layer thickness of 3 to 4 μm are preferable.
This time, n ^--with carrier concentration of 3E15cm-3 layer thickness of 2μm
After growing the InGaAs light absorbing layer 4, the carrier concentration is finally 2E15 to 6E15 cm-3 and the layer thickness is 1 to 2 μm as a window layer.
m, and this time, an n ⁻ -InP window layer 5 having a carrier concentration of 5E15 cm −3 and a layer thickness of 1.4 μm is grown (FIG. 2).
(A)). After forming an SiO ₂ film 14 as a diffusion mask on the epitaxial wafer by, for example, a CVD method,
A hole is formed in a portion corresponding to the light receiving region, and for example, 1E17 to 1E20 corresponding to the light receiving portion by sealing diffusion of Zn.
The p + region 6 of cm-3 is selectively formed (FIG. 2).
(B)).

After removing the diffusion mask, an etching mask 15 is grown by a CVD method so as to divide the n-InP window layer 5 excluding the light receiving region into three parts (FIG. 2C). The portion from the fifth side to the semi-insulating InP substrate 1 is removed by, for example, RIE (Reactive Ion Etching) (FIG. 2D). After removing the etching mask, for example, a SiNx film 7 is formed on the exposed element surface as a surface protective film also serving as an anti-reflection film by a P-CVD method or the like (FIG. 3E). Next, the SiN on the light receiving area
After a part of the x film is opened by using a photoresist as a mask to expose the p-InP region, the p-type ohmic electrode 1 is formed.
For example, AuZn is vapor-deposited using a vapor deposition method or the like (FIG. 3 (f)), and the photoresist mask is removed after vapor deposition.
A heat treatment at 380 ° C. is performed to alloy the deposited AuZn.

Next, in order to provide an n-side electrode and a common electrode outside the light-receiving region, a part of the SiNx film on the n-InP cap layer is opened by using a photoresist as a mask to form an nI.
After exposing the nP region, for example, AuGe is deposited as the n-type ohmic electrode 11 using an evaporation method or the like (FIG. 3).
(G)) After the deposition, the photoresist mask is removed, and a heat treatment at 360 ° C. is performed to alloy the deposited AuZn. Finally, an aerial wiring 13 is formed using, for example, Au plating so as to connect the p-type ohmic electrode 12 of the N element and the common electrode 8 and the p-type ohmic electrode 12 of the P element and the p-type electrode. n-type electrode 10, p-type electrode 9
Then, the common electrode 8 is formed using Au plating (FIG. 3H).

The Dual-PIN created in this manner
When a bias is applied between the n-side electrode 10 and the common electrode 8 of the N element, the n-side electrode 10 → n-InP window layer 5 → n
The current passing through the -InGaAs light absorbing layer 4 → n-InP buffer layer 3 is blocked by the p-InP carrier block layer 2, and does not become a leak current flowing between the n-type layer and the n-type layer via the substrate 1. . Dual-PIN of the present embodiment
FIG. 4 shows the dark current characteristics of FIG. p- layer between the n-type layer and the n-type layer
A leak current can be prevented by forming the n-p-n structure by inserting the InP carrier block layer 2, and the path of the dark current generated in the N element is only the path through the same pn junction as the P element. The difference between the dark currents of the N element and the N element is 10 pA or less. As a result, a good S / N balance characteristic is obtained, and the reception sensitivity can be improved by 0.7 dB. The above effects are not only epitaxial wafers grown by vapor phase growth,
Liquid phase growth method, CVD method, MOCVD method, MBE method, AL
The same effect can be obtained in an epitaxial wafer by the E method.

[Embodiment 2] FIG. 5 is a sectional view of a light receiving element according to a second embodiment of the present invention. The manufacturing method is the same as in Example 1,
It is characterized in that the common electrode 8 is formed on the n-InGaAs light absorption layer 4. N of one element as in Example 1
Since it is possible to prevent the occurrence of a leak current through the substrate between the mold layer and the n-type layer of the other element, the path of the dark current between the two elements becomes equal, and the difference between the dark currents of the P element and the N element is reduced. Is 10 pA or less, and as a result, a good S / N balance characteristic is obtained and the reception sensitivity can be improved by 0.7 dB.

[Embodiment 3] FIG. 6 is a sectional view of a light receiving element according to a third embodiment of the present invention. The manufacturing method is the same as in Example 1,
It is characterized in that the common electrode 8 is formed on the n-InP buffer layer 3. As in the first embodiment, it is possible to prevent the occurrence of a leak current through the substrate between the n-type layer of one element and the n-type layer of the other element. The difference in dark current between the P element and the N element is 10p
A or less, and as a result, a good S / N balance characteristic can be obtained, and the reception sensitivity can be improved by 0.7 dB.

Embodiment 4 Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 7 shows an embodiment of the semiconductor light receiving element of the present invention. 8 (a) to 8 (d) and 9 (e) to 9 (h) show a method for manufacturing a semiconductor light receiving element of the present invention. The carrier concentration is preferably 1E15 to 2E16 cm−3 layer thickness of 1 to 3 μm on the semi-insulating InP substrate 1 by the vapor phase growth method. In this case, the n-InP buffer layer 3 having the carrier concentration of 1E15 cm−3 layer thickness of 2 μm is used. 5E15
In this case, the n ⁻ -InGaAs light absorbing layer 4 having a carrier concentration of 3E15 cm−3 and a thickness of 2 μm is grown, and finally a carrier concentration of 2E is used as a window layer.
Preferably 15~6E15cm-3 thickness 1 to 2 [mu] m, n of the carrier concentration 5E15 cm-3 the layer thickness 1.4μm This time ^- -
An InP window layer 5 is grown (FIG. 8A). Etching mask 1 for element isolation on the epitaxial wafer
5 is grown by the CVD method (FIG. 8B), and then, for example, RIE is performed from the window layer 5 side to the semi-insulating InP substrate 1.
(Reactive Ion Etching) method to perform element isolation.

Impurities are implanted into the surface of the semi-insulating InP substrate between the epitaxial layers exposed by the etching by using, for example, the Be ion implantation method using the etching mask, and then the etching mask is removed. Then, a protective film 14 of phosphoric glass and SiO ₂ is newly grown by the CVD method, and then a high-temperature treatment at 700 ° C. is performed to form the p-InP carrier block layer 2 in the ion-implanted region. (FIG. 8 (c)). Next, a hole is made in a portion of the protective film 14 corresponding to the light receiving region, and 1E17 to 1E20 cm corresponding to the light receiving portion is formed by, for example, sealing diffusion of Zn.
The −3 p + region 6 is selectively formed (FIG. 8D).
After removing the protective film, for example, a SiNx film 7 is formed on the exposed element surface as a surface protective film also serving as an anti-reflection film by a P-CVD method or the like (FIG. 9E).

Next, a part of the SiNx film on the light receiving region is opened by using a photoresist as a mask to expose the p-InP region, and then, for example, AuZn is formed as a p-type ohmic electrode 12 by using an evaporation method or the like. Vapor deposition is performed (Fig. 9
(F)), after the deposition, the photoresist mask is removed, and a heat treatment at 380 ° C. is performed to alloy the deposited AuZn. Next, the n-side electrode 10 and the common electrode 8
A hole is formed in a part of the SiNx film 7 on the n-InP window layer 5 using a photoresist as a mask to provide n-InP.
After exposing the region 6, for example, AuGe is deposited as the n-type ohmic electrode 11 by using an evaporation method or the like (FIG. 9).
(G)) After the deposition, the photoresist mask is removed, and a heat treatment at 360 ° C. is performed to alloy the deposited AuZn. Finally, an aerial wiring 13 is formed using, for example, Au plating so as to connect the p-type ohmic electrode and the common electrode of the N element and the p-type ohmic electrode 12 and the p-type electrode 9 of the P element. The electrode, the p-type electrode, and the common electrode are formed using Au plating (FIG. 9H).

In the Dual-PIN thus prepared, when a bias is applied between the n-side electrode and the common electrode of the N element, the n-side electrode 10 → n-InP window layer 5 → n-InG
Since the current passing through the aAs light absorbing layer 4 → n-InP buffer layer 3 is blocked by the p-InP carrier blocking layer 2, it does not become a leak current flowing between the n-type layer and the n-type layer via the substrate. Therefore, the path of the dark current generated in the N element is only the path via the same pn junction as the P element,
The difference between the dark current of the P element and the dark current of the N element is 10 pA or less. As a result, a good S / N balance characteristic is obtained, and the reception sensitivity can be improved by 0.7 dB. The same effect can be obtained in an epitaxial wafer formed by a liquid phase growth method, a CVD method, a MOCVD method, an MBE method, or an ALE method, in addition to an epitaxial wafer formed by a vapor phase growth method.

[0019]

As described above, according to the present invention,
By providing a p-type carrier block layer between two adjacent elements, it is possible to prevent leakage current from flowing through the substrate between the n-type layer of one element and the n-type layer of the other element. The dark current generation paths between the two elements are equal, and the difference between the dark current and the S / N is 1% or less. As a result, there is an effect that the sensitivity can be improved by 0.7 dB.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor light receiving element according to a first embodiment of the present invention.

FIGS. 2A to 2D are explanatory diagrams of manufacturing methods (a) to (d) of the semiconductor light receiving element according to the first embodiment of the present invention.

3A to 3H are explanatory diagrams of manufacturing (e) to (h) of the semiconductor light receiving element according to the first embodiment of the present invention.

FIG. 4 is a dark current characteristic diagram of the semiconductor light receiving element according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor light receiving element according to a second embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor light receiving element according to a third embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor light receiving element according to a fourth embodiment of the present invention.

FIGS. 8A to 8D are explanatory diagrams of manufacturing methods (a) to (d) of the semiconductor light receiving element according to the fourth embodiment of the present invention.

FIG. 9 is an explanatory view of manufacturing (e) to (h) of the semiconductor light receiving element according to the fourth embodiment of the present invention.

FIG. 10 is an application example of a conventional example.

FIG. 11 is a sectional view of a conventional semiconductor light receiving element.

FIG. 12 is a dark current characteristic diagram of a conventional semiconductor light receiving element.

FIG. 13 is an explanatory diagram of generation of dark current in a conventional semiconductor light receiving element.

[Explanation of symbols]

Reference Signs List 1 n + -InP substrate 2 carrier block layer 3 n-InP buffer layer 4 n ^-- InGaAs light absorption layer 5 n-InP window layer 6 p-InP region 7 SiNx film 8 common electrode 9 p-side electrode 10 n-side electrode 11 n-side ohmic electrode 12 p-side ohmic electrode 13 aerial wiring 14 SiO ₂ film 15 etching mask 16 photoresist

Claims (4)

(57) [Claims] 1. A first conductive type carrier block layer (Eg1) and a second conductive type buffer layer (E) on a semi-insulating substrate (Eg1).
g1), a second conductive type light absorption layer (Eg2), and a second conductive type window layer (Eg1) in which a heteroepitaxial layer is sequentially formed under the condition of Eg1>Eg2; A structure in which two or more element structures each having a first conductive region (Eg1) are provided on the semi-insulating substrate at an interval; a second conductive light absorbing layer of a second element; A semiconductor light-receiving element, wherein a first conductive region of the element is connected with a conductive metal. 2. The semiconductor device according to claim 1, wherein the second conductive buffer layer (Eg1), the second conductive light absorbing layer (Eg2), and the second conductive window layer (Eg1) are formed on the semi-insulating substrate (Eg1). A heteroepitaxial layer sequentially formed under the condition of Eg2 and an element structure in which the first conductive region (Eg1) is partially provided in the window layer are provided on the semi-insulating substrate at an interval. One or more formed structures, the first conductive region of the first element and the second conductive window layer of the second element have an element isolation groove reaching the semi-insulating substrate, and an element of aerial wiring is provided. A structure in which a first conductivity type impurity is implanted in a groove portion reaching a semi-insulating substrate of the first element and the second element in a structure arranged in series, a first conductivity type region of the first element and the A semiconductor light receiving element, wherein two element second conduction type window layers are connected by a conductive metal. 3. The semiconductor light receiving device according to claim 2, wherein a second conductive buffer layer and a first conductive region of the first device are provided instead of the second conductive window layer of the second device. A semiconductor light receiving element, wherein the light receiving element is connected by a conductive metal. 4. The semiconductor light receiving device according to claim 2, wherein a second conductive buffer layer and a first conductive region of the first element are connected instead of the second conductive window layer of the second element. A semiconductor light receiving element, wherein the light receiving element is connected by a conductive metal.