JP2660752B2 - License plate recognition device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a license plate automatic which recognizes a license plate of a vehicle by capturing a running vehicle with a television camera, processing a still image obtained by the television camera, and processing the still image. It relates to a recognition device.

(Prior Art) Conventionally, in a bus use right arbitration device used in an arithmetic processing unit in this type of automatic license plate recognition device, the priority of each line is determined by the connection state of a bus request line, and the priority is low. When a higher-order request line is using the bus or requesting to use the bus, the right to use the bus cannot be obtained.

Only when the bus is in an unused state and no higher-level lines have issued a use request, the bus usage request for a line with a lower priority is given a use right. Was. There was no example in which two buses were available.

(Problems to be Solved by the Invention) In the above-mentioned conventional bus arbitration device, the number of request lines is usually eight or less. However, if the number of lines is large and the frequency of bus use is high, the request with low priority is low. There was a problem that the line had to wait for a long time to obtain the right to use.

For license plate recognition, for example, character recognition of vehicle type codes and character recognition of application codes, the recognition result is not valid unless both recognitions are completed, and there is no priority for each character recognition process. . In such a case, due to the restriction of the bus arbitration system, priorities are given, so that there is a problem that the bus access is waited for only one character recognition process, and the recognition result is delayed.

On the other hand, in license plate recognition processing, it is necessary to process all vehicles that are running continuously, so plate extraction processing and character recognition processing are performed in a pipeline system. In line processing, candidates for plate location address information obtained as a result of plate extraction are sent to character recognition processing several times in one imaging operation, as soon as the result is obtained. In most cases, the first time is the correct plate presence position address, but this is a method in which the cutting process is continued as long as time is available, and if there is a candidate, it is sent to the character recognition process to increase the cutting accuracy.

For this reason, the bus arbitration system switches so as to give priority to the request line from the plate cutout process when capturing the vehicle, and to give priority to the request line from the character recognition process when the first plate location position address is obtained. If the next vehicle passes and an image of the next vehicle is taken, it is desirable that the plate cutout processing be prioritized again. However, such priorities cannot be switched by the conventional bus arbitration device.

The present invention solves such a conventional problem, in which two buses are provided, and when the number of requests is less than two, permission is given to the vacant one without any distinction, and the waiting time is reduced. When there are three or more requests, the third and subsequent requests are kept waiting,
At that time, by changing the priority of the two used to the lowest, the permission is not shifted, and the priority of the plate cutting process and the character recognition process can be switched according to the processing status, thereby enabling the number recognition process. It is an object of the present invention to provide a license plate recognizing device which is most suitable for a license plate.

(Means for Solving the Problems) In order to achieve the above object, a license plate recognition device according to the present invention includes a plurality of image memory cards for storing still image digital data captured simultaneously by a plurality of cameras, and the image memory cards. A plurality of plate cutout image processing operation cards for determining whether or not an automobile license plate is present therein, and determining the plate presence position address if there is, and information on the plate presence position address Image processing calculation card for extracting the position of each character (land support code, vehicle type code, application code, serial number) from the license plate, and a plurality of character recognition calculation cards for recognizing each character from the information on each character position And an overall control card that controls and manages the entire process, and various processes for software debugging and maintenance. Each processing card including a monitoring processing card having a monitor function capable of referring to data during processing, two buses for enabling each processing card to read / write from / to an image memory, and a plate cutout image processing operation card A bus use permission signal for the previous two buses and a current bus request signal, and encodes and outputs a current bus request line according to a priority pattern algorithm stored therein. A request code output unit, a bus use permission signal for the previous two buses from the character recognition calculation card and a current bus request signal are input, and a current bus request line is generated according to a priority pattern algorithm stored therein. A second bus acquisition request code output unit for encoding and outputting, and each bus acquisition request code output unit Based on bus request line code signal et,
A bus arbitration code output unit for outputting a bus acquisition permission code signal for the two buses to be used this time according to an algorithm of a priority pattern stored therein; a bus arbiter for acquiring a right to use the two buses It has a high-speed bus use right arbitration function that is optimal for number recognition processing.

(Operation) According to the above configuration, the present invention performs a number recognition process based on a bus acquisition request from each processing card at this time, a bus acquisition request from each previous processing card, and a bus use permission response to each previous processing card. By combining the current bus use permission response most suitable for all the patterns, it is possible to immediately output a use permission response to a change in the bus acquisition input. Further, since a large number of bus request inputs are internally coded, the above functions can be realized with a small circuit configuration.
Also, the use permission can be efficiently given to the two buses.

FIG. 1 is a circuit diagram of a high-speed bus control unit of a license plate recognition device according to an embodiment of the present invention. 1,2 is
Refers to and processes a plurality of image memory cards storing still image digital data captured simultaneously by a plurality of cameras, and the contents of the memory of the image memory card, and checks whether or not an automobile license plate exists therein. For example, a plurality of plate cut-out image processing calculation cards for obtaining the plate existence position address and the position of each character (land support code / vehicle type code / use code / serial number) in the license plate are extracted from the information of the plate existence position address. An image processing calculation card to be output, a plurality of character recognition calculation cards for recognizing each character from the information on each character position, an overall control card for controlling and managing the entire processing, and each processing data for software debugging and maintenance. Each processing card composed of a monitoring processing card having a monitoring function Bus request input latch unit for receiving the bus request signals from the de, 3 and 4 to the respective processing card 2
This is a use permission output decoding unit for the buses A and B.

Further, 5 is the current bus request from the plate cutout image processing operation card (plate cutout unit) and the previous A,
A first bus acquisition request code output unit, which receives a B bus use permission code as input and encodes and outputs the current bus request line according to a priority pattern algorithm stored therein, is a character recognition operation card (character) In response to the request from the recognizing unit), the current bus request and the previous A and B bus use permission codes are input and the current bus request line is stored in accordance with the priority pattern algorithm stored therein. The second bus acquisition request code output unit 7 which encodes and outputs a bus that finally outputs a bus acquisition permission code from all the bus acquisition requests according to the algorithm of the priority pattern stored therein. A use permission output decoding unit, 8 is a bus acquisition request latch unit from the plate cutout unit, 9 is a bus acquisition request latch unit from the character recognition unit, 10 A bus grant state latch unit.

The outline of the operation of the control unit is as follows.
In response to the bus acquisition input change of 2, the bus acquisition request code output units 5 and 6 and the bus use permission output decode unit 7 determine the priority at that time, and the use permission output decode units 3 and
In step 4, the result is output to each processing card. The details will be described below.

The input data of the bus request input latch units 1 and 2 is a total of 14 data including 13 bus request signals and one priority mode signal (PCORCR).

The bus request signal is HWRQ which is the output of the overall control card, HWRQ2 ~ 7 from the plate cutting card, HWRQ8 ~ 12 from the character recognition card, and HWRQ from the monitoring processing card.
Consists of Q13. The priority mode signal is output when PCORCR = 0.
Plate cut-out section request> Character recognition section request (the plate cut-out section request takes precedence).

The output data of the use permission output decoding units 3 and 4 is a total of 27 data of 13 A bus permission signals, 13 B bus permission signals, and one bus busy status signal corresponding to each request.

The bus enable signal is HWAAV1, HWB which is the control card input.
AV1, plate cutout, HWAAV2 ~ 12, H to character recognition card
HWAAV13, HWB to WBAV2-12 and monitoring processing card
Consists of AV13.

 The priority system is as follows.

In accordance with the priority mode signal, priority control of the plate cutout section card and the character recognition section card is performed.

Requests from the overall control processing card (HWRQ1) are included in the plate extraction group, and requests from the monitoring processing card are included in the character recognition group, but the priority within each group is the lowest.

The priority within each group is determined by rotating the priority for each level for which permission has been given at that time. If there is no permit, the priority is fixed.

If there are two requests, give it permission regardless of priority.

Two buses A and B are provided as outputs.

Next, the algorithm of all the patterns stored in the bus acquisition request code output units 5 and 6 and the bus use permission output decoding unit 7 for realizing the above-mentioned priority system will be described.

Algorithm of First Bus Acquisition Request Code Output Unit 5 Each bit of address input and data output has the following meaning.

A0 to A6 (A) Allocate bus requests HWRQ1 to HWRQ7 from the overall control and plate cutout unit one by one.

A7 to A10 (A) ... Input the coded data for the line currently granting the A bus permission. (See Table 1).

A11 to A14 (c): Input the coded data of the line currently granting the B bus permission. (Refer to Table 1.) A15 (d) ... Input priority mode signal (PCORCR).
When the value is 0, HWRQ1 to HWRQ7, which are requests from the plate cutout unit, and HWRQ1, which is a request from the overall control, that is, the first bus acquisition request code output unit 5 is replaced with the second bus acquisition request code output unit 6. Take precedence. When 1 is the opposite.

O _{0 to} O ₂ (E)... Outputs data obtained by coding a level at which permission is given to the A bus. (See Table 2) O _{3 to} O ₅ (f) Output data that encodes the level that grants permission to the B bus (see Table 2) (1) When all are OFF → O = 0, Ka = 0 (2) When i = 0 & C = 0 When only one of them (let's be α) is ON → Oh = α ',
F = 0 When two or more of α (α, β, γ, ...) are ON, then α>β>γ> ... according to the priority order of A0>A1>A2>A3>A4>A5> A6 → E = Α ', f = β' (3) (1 ≦ a ≦ 7) & c = 0 When b = α ″, when only one (α) is ON → o = α ′, When only one of them is ON (let β be set, β ≠ α) When PCORCR = 0 (5 priority), d = 0 o = β ',
0 When PCORCR = 1 (6 priority), d = 1 o = 0, ka = 0 When two of them (α, β) are ON → o = α ', ka =
β 'When two of them (β, γ, ββγ ・ α) are ON If β> γ in accordance with the priority order, when d = 0 → o = β ', ka = γ' When d = 1 → o = 0, ka = β 'At least three of (α, β, γ ,…) Is ON When three or more of them (β, γ, ... ， α) are ON When d = 0 → o = β ', ka = γ' When d = 1 → o = 0, ka = β '(4) When i = 0 & (1 ≤ c ≤ 7), c = α'' When only one of them (α) is ON → o = 0, KA = α 'When only one of them (let β, β ≠ α) is ON d = 0 → o = 0, KA = β 'd = 1 → OH = 0, KA = 0 When two of them (α, β) are ON → OH = β', KA =
When two of α '(β, γ, β · γ ≠ α) are ON When d = 0 → e = β 'f = γ' When d = 1 → e = β 'f = 0 When three or more (α, β, γ, ...) are ON When three or more of them (β, γ, ... ， α) are ON When d = 0 → o = β ', ka = γ' When e = 1 → o = β ', ka = 0 (5) When i ≥ 8 & c = 0 One of a (let it be α) When only is ON → O = 0, Ka =
When two or more of α's (α, β, γ, ...) are ON, if α>β> γ ... according to the priority order of A0>A1>A2>A3>A4>A5> A6 → E = 0 , F = α '(6) When i = 0 & c ≥ 8 When only one of them (let's be α) is ON → e = α',
F = 0 When two or more of α (α, β, γ, ...) are ON, if α>β> γ ... according to the priority order of A0>A1>A2>A3>A4>A5> A6 → E = α ′, power = 0 (7) (1 ≦ a ≦ 7) & (1 ≦ c ≦ 7) A = α ″,
C = β "If only one of the a (α) is ON → o = α ', KA = 0 If only one of the a (β) is ON → o = 0, KA = β 'When only one of them (γ, γ ≠ α · γ ≠ β) is ON d = 0 → o = γ', ka = 0 d = 1 → o = 0, ka = 0 a When two or more (α, β, γ, ...) are ON → e = α ', f = β' When two (α, γ, γ ≠ β) are ON, d = 0 When → O = α'C = γ 'd = 1 → O = α'C = 0 When two of them (β, γ, γ ≠ α) are ON D = 0 → O = γ ', Power = β' When d = 1 → e = 0, power = β 'Two or more of them (γ, δ, ε, ... are both ≠ α, ≠ β)
Is ON D = 0 → o = γ ', ka = δ' d = 1 → o = 0, k = 0 When three or more (α, γ, δ ... ≠ β) are ON If γ>δ> ... according to the priority order, when d = 0 → e = α ', d = γ' When d = 1 → d = α ', d = 0, three or more of the (β, γ , Δ… ≠ α) is ON D = 0 → o = γ ', ka = β' d = 1 = o = 0, ka = β '(8) (1 ≦ a ≦ 7) & c ≧ 8 a = α ″ If only one of α (α) is ON → E = α ', KA = 0 If only one of A (β, β ≠ α) is ON D = 0 → E = Β ', ka = 0 d = 1 → o = 0, ka = 0 When two or more (α, β, γ, ...) are ON → o =
α ', KA = 0 When two or more (α, γ, ... ≠ α) are ON D = 0 → o = β ', ka = 0 d = 1 → o = 0, ka = 0 (9) When i ≤ 8 & (1 ≤ u ≤ 7), then u = α " When only one (α) of them is ON → o = 0, power = α 'When only one of them (let β, β ≠ α) is ON d = 0 → o = 0, When mosquito = β 'd = 1 → o = 0, ka = 0 When two or more (α, β, γ, ...) are ON → o = 0,
F = α 'When two or more of them (β, γ, ... ≠ α) are ON D = 0 → o = 0, ka = β 'd = 1 → o = 0, ka = 0 (10) When i ≤ 0 ≥ 8 & c ≤ 8 → o = 0, ka = 0 second The algorithm of the bus acquisition request code output unit 6 of FIG.

A0 to A6 (A) ... Allocate bus requests HWRQ8 to HWRQ13 from the plate cutout section and the monitoring processing card one by one. However, A5 is not used.

A7 to A10 (A) ... Input the coded data for the line currently granting the A bus permission. (See Table 1).

A11 to A14 (c): Input the coded data of the line currently granting the B bus permission. (Refer to Table 2.) A15 (c): Input the priority mode signal (PCORCR).
At the time of 1, the HWRQs 8 to 12, which are requests from the character confirmation unit, and the HWRQ 13, which is a request from the monitoring processing card, that is, the data of the second bus acquisition request code output unit 6 are replaced with the data of the first bus acquisition request code unit 5. Take precedence. When 0, reverse.

O _{0 to} O ₂ (E)... Outputs data obtained by coding a level at which permission is given to the A bus. (See Table 3) O _{3 to} O ₅ (f) Output data that encodes the level for granting permission to the B bus (see Table 3) (1) When all are OFF → O = 0, CA = 0 (2) When i = 0 & C = 0 When only one of them (α) is ON → O = 0, CA =
α 'When two or more of them (α, β, γ, ...) are ON, if α>β>γ> ... according to the priority order of A0>A1>A2>A3>A4>A5> A6 → e = β ', mosquito = α' (3) If a≥8 & c ≥0, suppose that i = α ". When only one of them (α) is ON → e = α ', mosquito = 0 When only one (β, β ≠ α) is ON d = 0 When o = 0, ka = 0 When E = 1 → o = β ', ka = 0 Two of α (α , Β) is ON → e = α ', f =
β 'When two of them (β, γ, ββγ ・ α) are ON When d = 0 → o = 0, ka = β 'When e = 1 → o = γ', ka = β 'When at least three of them (α, β, γ, ...) are ON When three or more of them (β, γ, ... ， α) are ON When d = 0 → o = 0, ka = β 'When e = 1 → o = γ', ka = β '(4) When i = 0 & c ≥ 8, c = α " When only one (α) is ON → O = 0, power = α 'When only one of them (let β, β ≠ α) is ON D = 0 → Oh = 0, power = 0 When d = 1 → e = 0, ka = β 'When two (α, β) are ON → o = β', ka =
When two of α '(β, γ, β · γ ≠ α) are ON When d = 0 → e = β 'f = 0 When d = 1 → e = γ' f = β 'When three or more (α, β, γ, ...) are ON When three or more of them (β, γ, ... ， α) are ON D = 0 → o = β ', ka = 0 d = 1 → o = γ', k = β '(5) (1 ≤ a ≤ 7) & c = 0 One of a (Only α) is ON → o = 0, ka =
When two or more of α's (α, β, γ, ...) are ON, if α>β> γ ... according to the priority order of A0>A1>A2>A3>A4>A5> A6 → E = 0 , Mosquito = α '(6) When i = 0 & (1 ≤ c ≤ 7) When only one of them (let's be α) is ON → e = α',
F = 0 When two or more of α (α, β, γ, ...) are ON, if α>β> γ ... according to the priority order of A0>A1>A2>A3>A4>A5> A6 → E = α ', KA = 0 (7) When A ≧ 8 & C ≧ 8, set A = α ″ and C = β ″ When only one (α) is ON → E = α ′, C = 0 When only one of them (β) is ON → e = 0, ka = β 'When only one of them (γ, γ ≠ α · γ ≠ β) is ON d = 0 → O = 0, ka = 0 d = 1 → o = 0, ka = γ 'When two or more of them (α, β, γ, ...) are ON → o = α', ka = β ' When two or more of them (α, γ, γ） β) are ON, d = 0 → o = α 'f = 0 e = 1, o = α' f = γ ' When this (β, γ, γ ≠ α) is ON When D = 0 → E = 0, E = β 'When E = 1 → E = γ', E = β ' γ, δ, ε, ... are both ≠ α, ≠ β)
Is ON D = 0 → o = 0, ka = 0 d = 1 → o = δ ', ka = γ' When three or more (α, γ, δ ... ≠ β) are ON When d = 0 → o = α ', ka = 0 When e = 1 → o = α', ka = γ 'When at least three of them (β, γ, δ ...） α) are ON When d = 0 → o = 0, ka = β 'When e = 1 → o = γ', ka = β '(8) When i ≧ 8 & (1 ≦ u ≦ 7), set a = α ″ When only one of them (α) is ON → o = α ', KA = 0 When only one of them (let β, β ≠ α) is ON d = 0 → o = 0, ka = 0 d = 1 → o = β ', ka = 0 When two or more (α, β, γ, ...) are ON → o = α', ka = 0 a When two or more (α, γ, ... ≠ α) are ON When d = 0 → o = 0, ka = 0 When e = 1 → o = β ', ka = 0 (9) (1 ≦ a ≦ 7) & c ≧ 8 When c = α ″ When only one of them (α) is ON → o = 0, power = α 'When only one of them (let β, β ≠ α) is ON d = 0 → o = 0 , KA = 0 ET = 1 → OH = 0, KA = β 'When two or more of them (α, β, γ, ...) are ON → OH = 0, KA = α' When more than (β, γ, ... ≠ α) is ON D = 0 → o = 0, ka = 0 d = 1 → o = 0, k = β '(10) If (1 ≤ i ≤ 7) & (1 ≤ c ≤ 7) → o = 0,
F = 0 Algorithm of the bus use permission code output unit 7 Each bit of the address input and the data output has the following meaning.

A0 to A2 (E '): Input a line code for granting permission to use the bus A in response to a request from the overall control and plate cutting. (See Table 2.) A3 to A5 (f) Input a code of a line that grants permission to use the bus B in response to requests from the overall control and plate cutting. (See Table 2) A6 to A8 (E "): Enter the code of the line that grants permission to use bus A in response to a request from the monitoring processing card and character recognition (see Table 3). F ")... In response to the request from the monitoring processing card and the character recognition, the code of the line for granting the use permission of the bus B is input. (See Table 3.) O _{0 to} O ₃ (A ′)... Output the output code of the line that grants use permission to the A bus. The (Table 1 refer) O ₄ ~ O ₇ (c ') ... outputs the output code of the line B bus to authorize use (first OmoteTeru) A12 (d') ... priority mode signal (PCORCR) input.

When 0 → Plate cut out> Character recognition ie E '>
E ", KA"> KA "When 1 → Character recognition> Plate cutout, ie ″>
E ', K ">K' In this way, the priority is controlled in the state of D '.

The outputs A 'and C' correspond to the A bus and the B bus, respectively, and are independent of each other. I 'is determined by o', o "and d ', and c' is determined by f ', k" and d'.

5.1 Output A '(1) When O' = 0, O "= 0 → A '= 0 (2) When O' ≠ 0, O" = 0 When O '= α' →
A '= α "(3) E' = 0, E" When E ≠ 0, E "= α '→
I '= α "(4) If o' ≠ 0, o '≠ 0, then o' = α ', o' = β ', then d' = 0 → a '= α"d' = 1 Time → b ′ = β ″ 5.2 output c ′ (1) When k ′ = 0, k ″ = 0 → c ′ = 0 (2) When k ′ ≠ 0, k ″ = 0, k ′ = α ′ If you leave →
C ′ = α ″ (3) Power ′ = 0, Power “when α′0” = α ′ →
C ′ = α ″ (4) When K ′ ≠ 0, K ″ = 0, K ′ = α ′, K ″ = β ′ If D ′ = 0 → C ′ = α ″ D ′ = 1 Time → c ′ = β ″ (Effect of the Invention) According to the present invention, it is possible to perform high-speed bus arbitration control optimal for license plate recognition processing for a large number of bus input requests, and to give priority to buses during recognition processing. Since the order can be changed, and in particular, two buses can be efficiently controlled for a large number of requests, a plurality of simultaneous memory accesses can be performed in a multi-CPU configuration, and the practical effect is extremely large.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a high-speed bus control unit of a license plate recognition device according to one embodiment of the present invention. 1, 2 ... bus request input latch section from each processing card, 3 ... bus A use permission output decode section to each processing card, 4 ... bus B use permission output decode section to each processing card, 5 ... ... the current bus acquisition request code output unit obtained from the current bus acquisition request from the plate cutout unit and the previous A and B bus use permission code, 6 ... the current bus acquisition request from the character recognition unit and the previous A ,
The current bus acquisition request code output section obtained from the B bus use permission code, 7... The current bus use permission code output section obtained from all bus acquisition requests and the priority mode signal, 8... Acquisition request latch section, 9: Bus acquisition request latch section from character recognition section, 10: Bus use permission state latch section.

Continuation of the front page (72) Inventor Yoshiharu Yano 4-3-1 Tsunashima Higashi, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Inside Matsushita Communication Industrial Co., Ltd. (56) References JP-A-62-90800 (JP, A) JP-A Sho 60-221863 (JP, A) JP-A-3-51999 (JP, A) JP-A-3-68099 (JP, A)

Claims (1)

(57) [Claims] 1. A plurality of image memory sections for storing digital still image data picked up by a plurality of cameras simultaneously, and referring to and processing the memory contents of the image memory sections to determine whether an automobile license plate exists therein. A plurality of plate cut-out image processing operation units for checking and, if present, the plate location position address, and each character in the license plate (land support code / vehicle type code / use code / serial number) from the information of the plate location position address ), An image processing operation unit for cutting out the position, a plurality of character recognition operation units for recognizing each character from the information on each character position, an overall control unit for controlling and managing the entire processing, and a software debug and maintenance unit. A processing unit comprising a monitoring processing unit having a monitor function capable of referring to data in the middle of each processing; And two buses for enabling read / write to the image memory by the unit, a bus use permission signal for the previous two buses from the plate cutout image processing operation unit, and a current bus request signal. A first bus acquisition request code output unit for encoding and outputting the current bus request line in accordance with the stored priority pattern algorithm; and a bus use permission signal for the previous two buses from the character recognition operation unit. A second bus acquisition request code output unit that receives the current bus request signal, encodes the current bus request line according to an algorithm of a priority pattern stored therein, and outputs the encoded bus request line; Use this time according to the priority pattern algorithm stored inside based on the bus request line code signal from That the license plate recognition device characterized by comprising a, a bus grant code output unit for outputting a bus acquisition permission code signal for two buses.