JP2654787B2 - Spread spectrum receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Field of the Invention The present invention relates to a receiver used in a spread spectrum communication system, and particularly to a correlated pulse generation circuit thereof.

B. Summary of the Invention A correlator obtains a correlation spike by correlating a received signal with a reference signal, and obtains a correlation pulse from the correlation spike through a comparison circuit. First and second peak value detection circuits for detecting the first and second peak values, a first comparison circuit for comparing the first and second peak values, and the first and second peak value detection circuits.
A selection circuit that selects the first and second peak values based on the output of the comparison circuit, a threshold setting circuit that generates a threshold value based on the peak value selected by the selection circuit, and a comparison between the threshold value and the correlation spike. And outputs a correlation pulse.

C. Conventional Techniques In a spread spectrum communication system, it is necessary that even if the correlator output fluctuates, an appropriate threshold signal can be obtained in accordance with the fluctuation and a target correlation output can be detected.

As a conventional method, for example, there is a method disclosed in Japanese Patent Publication No. Sho 60-5639, "Receiving Circuit in Spread Spectrum Communication System".

This method combines the positive and negative correlation spikes of the matched filter output after peak-holding them by a peel hold circuit, generates a threshold signal proportional to this peak hold value, sets the threshold circuit, detects the correlation spike, and demodulates the data. FIG. 3 shows the circuit configuration. In FIG. 3, 21 is a correlator, 22 is a peak hold circuit, 23 is an arithmetic circuit, 24 is a flip-flop, 25 is a shift lock generator, 26 is a shift circuit, 27 is a PN code, 28 is a delay circuit, 29, Numeral 30 denotes a multiplier, which multiplies by -1 to serve as an inverter. That is, the peak hold circuit
31 holds the peak of the positive polarity, and the peak hold circuit 32 holds the peak of the negative polarity. Variable resistance from its peak value
To obtain a threshold signal via the R _3, the comparator 33 detects a positive correlation spike, detects correlation spikes negative the comparator 34.

D. Problems to be Solved by the Invention However, this circuit configuration has the following problems. The peak hold circuit 22, when fully peak hold correlation spike, be very small time constants correlation spike width due to the internal resistance and the capacitor C ₁ or C ₂ of the very thin because the diode D ₁ or D ₂ Must. That is, it is necessary to reduce the charging time constant.

Conversely, if you hold this peak value as the correlation spike one period minutes, in order to suppress the reduction of the hold value, called droop, if take into to increase the time constant of a resistor R ₁ or R ₂ and the capacitor C ₁ or C ₂ No. That is, it is necessary to increase the discharge time constant.

With the circuit configuration shown in FIG. 3, in setting a threshold signal that fluctuates in response to a fluctuating correlation spike φ (t), the discharge time constant R ₁ C ₁ of the peak hold circuit 31 or 32 is set.
Alternatively, it is apparent that R ₂ C ₂ must be increased, as shown in FIG.

Next, when considering a change in the peak value, in the case of a peak hold circuit having a good hold property, that is, a peak hold circuit having a large discharge time constant, the followability with respect to a decrease in the peak value is deteriorated. This will be described with reference to FIG.

When a correlation spike φ (t) (in this case, data corresponds to 1,1,0,0,) causing a level change as shown in FIG. 5 is input to the peak hold circuit 22, The values of the peak hold circuits 31 and 32 are the values of b) and c)
S _A and S _B.

Here, when the correlation spike 1 is smaller than the correlation spike 2 of positive polarity or negative polarity correlation spike 3 is smaller than the correlation spike 4, were obtained, the capacitor C ₁ or
C ₂ is not charged, continued discharge. That is, if the peak value decreases more than the droop due to the discharge, the peak value cannot be detected. Further, when the threshold signals S _C and S _D are set as shown in FIG. 5A, the correlation spike 1 can be detected, but the correlation spikes 2, 3, and 4 cannot be detected.

Accordingly, the demodulated data d (t) is applied to the input data.
Is incorrect data. In FIG. 5, d) and e) show the respective waveforms of S _E and d (t) of FIG. 3.

E. Object of the Invention The object of the present invention is to set an appropriate threshold signal even when the correlator output fluctuates with the fluctuation of the received signal level,
An object of the present invention is to provide a circuit capable of reliably demodulating data by obtaining a correlation pulse.

F. Means for Solving the Problems In order to achieve the above object, a spread spectrum receiver of the present invention includes a correlator that obtains a correlation spike by correlating a received signal with a reference signal, A first peak value detection circuit for detecting a peak value of a positive spike, a second peak value detection circuit for detecting a peak value of a negative spike of the correlation spike, and a peak value and a negative value of the positive spike. A first comparing circuit that compares the peak value of the spike, a selecting circuit that selects any one of the peak values according to the output of the first comparing circuit, and a peak value that is selected by the selecting circuit. And a second comparison circuit that compares the threshold value with a correlation spike and outputs a correlation pulse.

In an advantageous embodiment of the present invention, the threshold setting circuit includes a first threshold setting circuit for generating a threshold for a positive correlation spike, and a second threshold setting circuit for generating a threshold for a negative correlation spike. The second comparison circuit outputs a correlation pulse for a positive correlation spike, a fourth comparison circuit outputs a correlation pulse for a negative correlation spike, and the first and second comparison circuits.
The first and second peak value detection circuits of the correlation spikes
, And first and second hold circuits for holding the hold values held by the first and second peak hold circuits, the hold being held by the first and second peak hold circuits. Means for clearing the value at a desired timing is included. The threshold setting circuit includes outputting a value obtained by multiplying a peak value selected by the selection circuit by a multiplication coefficient, and controlling the multiplication coefficient by a CPU.

G. Action For the positive and negative correlation spikes, further latch the value of the peak hold circuit that holds the peak value of the correlator output every cycle of the correlator output, and compare them.
Select and set a threshold value for one correlator output synchronization.

H. Examples Hereinafter, the present invention will be described in more detail by way of examples with reference to the drawings, but these are merely examples, and various modifications and improvements can be made without departing from the scope of the present invention. Of course, this is possible.

FIG. 1 is a block diagram showing a configuration of a correlation pulse generating circuit used in a spread spectrum receiver according to the present invention, and FIG. 2 is a timing chart of signals in respective parts of the circuit shown in FIG. In FIG. 1, 1 is a correlator and a PDI (Pos
t Detection Integration: integration circuit), 2 is A / D converter, 3 is inversion circuit, 4, 5, 8, 9 is latch circuit, 6, 7, 10, 14, 1
5 is a comparison circuit, 11 is a selection circuit, 12 and 13 are threshold value setting circuits, 1
6, 17 represent a peak hold circuit, and 18, 19 represent a peak value detection circuit.

The A / D converter 2 A / D converts the correlation spike a based on the sampling signal b to obtain an output c. Here, the result of sampling the period in which the correlation spike a exists is A /
The output c of the D converter 2 is in the shaded area.

Next, the output c of the A / D converter 2 is branched to a path 1 and a path 2. Path 1 is a peak value detection circuit 18 composed of a peak hold circuit 16 and a latch circuit 8, and path 2 is an inversion circuit 3 and a peak value detection circuit 19 composed of a peak hold circuit 17 and a latch circuit 9.

The path 2 can be realized with the same circuit configuration as the path 1 by inverting the polarity of the N-bit data of the output C of the A / D converter 2. Therefore, after the A / D converter 2, the signal is input to the inverting circuit 3 of the path 2.

 First, the operation of the path 1 will be described.

The output c of the A / D converter 2 is input to the latch circuit 4 and the comparison circuit 6. The comparison circuit 6 compares the output c of the A / D converter 2 with the data f stored in the latch circuit 4, and determines that the data of the output c of the A / D converter 2 is larger. , And a pulse output e. With the pulse e as a trigger, the latch circuit 4 stores the data of the output c of the A / D converter 2 and updates the data f of the latch circuit 4.

As described above, the output c of the A / D converter 2 is sequentially compared with the data f of the latch circuit 4, and the data f stored in the latch circuit 4 is updated. The required peak hold circuit 16 is configured.

The latch circuit 4 clears the content f stored by the clear signal d at each cycle of the correlation spike, and performs a peak hold for one new cycle of the correlation spike. The cycle of the pulse of the clear signal d is the same as the cycle of the correlation spike. In other words, with the peak hold circuit having this circuit configuration, the peak value in one cycle of the correlation spike can be reliably held.

Next, the maximum value of the output c of the A / D converter 2 for one cycle of the correlation spike stored in the latch circuit 4 is equal to the enable signal i before the latch circuit 4 is cleared by the clear signal d. Is stored as a trigger.

 Next, the operation of the path 2 will be described.

The operation from the inverting circuit 3 to the latch circuit 9 is the same as the operation of the path 1 since the operation can be realized by the same circuit configuration as that of the path 1 of the path 2.

Therefore, the latch circuits 8 and 9 in the paths 1 and 2
Stores the maximum value of the positive polarity and the maximum value of the negative polarity in one cycle of the correlation spike.

Next, the output j of the latch circuit 8 and the output k of the latch circuit 9
Is input to the comparison circuit 10. The comparison circuit 10 compares the input data j and k, and obtains an output 1 when the data j is larger than the data k.

The output 1 of the comparison circuit 10 is input to the selection circuit 11. The selection circuit 11 passes either the output data j of the latch circuit 8 or the output data k of the latch circuit 9 in the state of the input signal l. That is, in the correlation spike a,
Regardless of whether or not a correlation spike exists, the higher of the peak value of the positive polarity or the peak value of the negative polarity is obtained, and the peak value is updated every cycle of the correlation spike.

With this configuration, the peak value of the correlation spike can be reliably held within one cycle of the correlator output,
In addition, it is possible to follow the fluctuation of the peak value, and it is possible to eliminate a malfunction when the polarity of the correlation spike changes.

Next, the data m resulting from the selection of either the output j of the latch circuit 8 or the output k of the latch circuit 8 by the selection circuit 11 is input to the threshold setting circuits 12 and 13, respectively.

Threshold setting circuits 12 and 13 calculate data m and control signal P representing a multiplication coefficient to generate threshold signals Q and R, respectively. The threshold signals Q and R are N-bit digital signals.

Further, the threshold setting circuits 12 and 13 can independently set different threshold signals.

The control signal P is generated from, for example, a CPU or the like.

Next, the threshold signal Q obtained by the threshold setting circuits 12 and 13
And R are input to comparison circuits 14 and 15.

The comparison circuits 14 and 15 compare the output c of the A / D converter 2 and the output S of the inversion circuit 3 with threshold signals Q and R,
Output c of A / D converter 2 larger than threshold signals Q and R
When the output S of the inverting circuit 3 is input, outputs n and o are obtained. In this way, correlation pulses n and o corresponding to the correlation spike are obtained.

Further, as shown in FIG. 2, when the correlation spike is at the positive polarity, the latch circuit 8 holds the peak value in one cycle in which the positive correlation spike exists, thereby making the next one cycle possible. Can be set, and the comparison circuit 10 compares the peak values.The selection circuit 11 determines the absolute maximum value in that cycle, sets the threshold signal for the positive-negative correlation spike, and obtains the final correlation pulse. . Therefore, the peak hold of the positive / negative correlation spike corresponding to the binary baseband information is performed and latched, so that there is no erroneous detection.

Although the above-described peak hold circuit configuration is premised on digital signal processing, the present invention can be applied to analog signal processing by replacing the latch circuit with a hold circuit.

I. Effects of the Invention As described above, according to the present invention, there is obtained an advantage that accurate data demodulation can be performed with respect to the level fluctuation of the correlator output.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a correlation pulse generation circuit used in a spread spectrum receiver according to the present invention.
FIG. 3 is a timing chart of signals in various parts of the circuit shown in FIG. 1, FIG. 3 is a circuit diagram of a conventional correlation pulse generation circuit, and FIG. 4 is a voltage waveform when the discharge time constant is small and when the discharge time constant is large. FIG. 5 is a signal waveform diagram in each part of the circuit shown in FIG. 1 Correlator and PDI, 2 A / D converter, 3 Inverting circuit, 4, 5, 8, 9 Latch circuit, 6, 7, 10, 14, 15 Comparator circuit, 11 …… Selection circuit, 12,13 …… Threshold setting circuit, 16,17
…… Peak hold circuit, 18,19 …… Peak value detection circuit.

Claims (7)

(57) [Claims] 1. A correlator for obtaining a correlation spike by correlating a received signal with a reference signal; a first peak value detection circuit for detecting a peak value of a positive polarity spike of the correlation spike; A second peak value detection circuit for detecting the peak value of the negative polarity spike, a first comparison circuit for comparing the peak value of the positive polarity spike with the peak value of the negative polarity spike, and the first comparison circuit A selection circuit for selecting any one of the peak values according to the output of the threshold value; a threshold setting circuit for generating a threshold value based on the peak value selected by the selection circuit; and comparing the threshold value with a correlation spike for correlation. And a second comparison circuit for outputting a pulse. 2. A threshold setting circuit comprising: a first threshold setting circuit for generating a threshold for a positive correlation spike; and a second threshold setting circuit for generating a threshold for a negative correlation spike. The spread spectrum receiver according to claim 1, 3. A second comparison circuit comprising: a third comparison circuit for outputting a correlation pulse for a positive correlation spike; and a fourth comparison circuit for outputting a correlation pulse for a negative correlation spike. The spread spectrum receiver according to claim 1, characterized in that: 4. The first and second peak value detection circuits hold first and second peak hold circuits for correlation spikes and hold values held by the first and second peak hold circuits. 2. The spread spectrum receiver according to claim 1, comprising a first and a second hold circuit. 5. The spread spectrum receiver according to claim 4, further comprising means for clearing a hold value held by said first and second peak hold circuits at a desired timing. 6. The spread spectrum receiver according to claim 1, wherein said threshold value setting circuit outputs a value obtained by multiplying a peak value selected by said selection circuit by a multiplication coefficient. 7. The spread spectrum receiver according to claim 6, wherein said multiplication coefficient is controlled by a CPU.