JP2653683B2 - Semiconductor trench memory cell structure - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates generally to semiconductor circuits and methods of making the same, and more specifically, to semiconductor memory structures and methods of making the same.

2. Description of the Related Art There is an ongoing effort to develop faster semiconductor memories with greater storage capacity. Recently, efforts have been made to reduce the area required for each storage cell of the memory,
Therefore, an integrated circuit chip can contain many such cells. Efforts have also been made to reduce the various capacitances associated with the memory cells to enable high speed electrical read and write operations.

One way to achieve high density, high speed dynamic random access memory (DRAM) is to use trench technology. With this technique, a DRAM cell including a pass transistor in series with a storage capacitor is formed in a trench having a transistor formed on the capacitor. In this method, the transistor does not need to be formed on the wafer in the lateral direction with respect to the capacitor as in the prior art, so that the wafer area per cell is reduced. To optimize the operation of the trench DRAM cell, the storage capacitance was kept to a maximum by forming the trench deep in the silicon wafer. If the trench is deep, the storage capacitor can be made large, but the depth of the trench is limited due to the limitations of the conventional process.

When etching silicon ware to form the trench, such a trench tapers inward near the bottom surface of the trench due to certain process limitations. Therefore,
In narrow trenches, which are desirable to reduce cell area,
The trench sidewalls are a few microns deep below the wafer surface and converge or adjoin one another. Therefore, efforts to form narrow trenches and further reduce the required ell area are not productive in that the capacitance of the storage capacitor is correspondingly reduced or at least limited.

The trench cells were accessed by bit lines diffused into the semiconductor material of the wafer. Utilizing a bit line of the above structure, with respect to the substrate, the junction capacitance places a speed limit on cell access. Also, such cell structures are susceptible to soft errors due to the nature of the electrical cell operation being inaccurate due to alpha particles entering the substrate.

From the above, it is apparent that the DRAM cell structure needs to be improved, and that a manufacturing method that reduces the cell area without affecting the storage capacity of the storage capacitor is required. In addition, there is a need for a memory structure that reduces word line capacitance and a strong immunity to alpha particle strikes. Relatedly, there is also a need for high-density, high-speed DRAM arrays that can be manufactured with currently available silicon manufacturing techniques.

SUMMARY OF THE INVENTION In accordance with the present invention, a DRAM cell structure and method for fabricating the same significantly reduces or eliminates the disadvantages of the prior art. According to the present invention, the trench is formed in a semiconductor wafer with a width necessary to achieve a desired depth. In this way, the trench can be formed deeper and a correspondingly larger storage capacitor can be obtained. Multiple memory cells are formed in each such trench, as wider trenches may be required. The technical advantage of this technique is that the large required lateral area of the trench does not increase the overall area required for a given number of DRAN cells. In addition, it is a technical advantage that cell capacitance is greater due to the elimination of trench depth limitations.

The trench is delimited by an insulator, defining the location of the cell and electrically isolating therebetween. The majority of each partitioned area is occupied by cell capacitors, on which small area vertical pass transistors are formed. The pass transistors are formed at diagonally opposite corners of the trench,
Minimize electrical coupling between adjacent cells.

The word lines of the memory array are each connected to a column of cells by small vertical columns of conductive polysilicon formed in trenches adjacent to the pass transistors. Thus, a transistor having a small area is formed. The word line pillars act as such gate conductors and control the conduction of the pass transistor. The technical advantage of this feature is that the word line capacitance is reduced.

The bit lines of the DRAM memory array of the present invention include lines of conductive polysilicon that extend over the field oxide regions overlying the semiconductor material of the wafer. As a technical advantage of this, the field oxide reduces the capacitance between the bit line and the substrate and improves the speed characteristics of the memory. In addition, the bit line overlaps the region of the field oxide to be electrically insulated, thereby reducing the electrical impact of the bit line due to asphalt strikes on the substrate.

Other features and advantages will become apparent from the following description of the preferred embodiments of the present invention, with reference to the accompanying drawings. Throughout the drawings, similar parts or regions are denoted by the same reference numeral.

EXAMPLE An embodiment of a multiple cell trench according to the present invention is described in an exemplary manner with two cells in one trench. However, with the techniques of the invention described below, those skilled in the art will be able to apply the principles and concepts of the invention to
It is easy to provide more than two cells in a trench.
In fact, an elongated trench is provided with a large number of cells, each cell being isolated by a grid or matrix of insulators.

FIG. 1 shows a semiconductor wafer structure in the process, in which a cell trench is to be formed. In particular, shown is a heavily doped P + substrate 10, which is covered with a thinner doped epitaxial layer 12. The P + substrate 10 has a <100> crystallographic direction,
It can be formed of a suitable semiconductor material, such as a silicon wafer having an impurity concentration of about 1E19 atoms / cm ³ . Layer 12 of lightly doped semiconductor material is deposited in an epitaxial technique, with a concentration of about 1E16 to 1E17 atoms / cm ^3. Epitaxial layer 12 can be deposited to a depth of 4 to 4.5 microns. Since such a transistor is formed perpendicular to the lightly doped layer 12, the depth of the epitaxial layer 12 is related to the channel length of the pass transistor of the cell. The lightly doped P-type layer 12 is
It serves to increase the breakdown voltage of the cell transistor.

Thick field oxide strips 14 and 15 are formed on the wafer surface by conventional thermal syringe oxidation techniques. Silicon oxide strips 14 and 15 contain field oxide and grow to a sufficient thickness of 10,000 Angstroms. As described in FIG. 1, a thin oxide layer 16 connects the field oxide strips 14 and 15. The thin oxide 16 functions as a gate oxide for the MOS transistor formed in the peripheral circuit of the memory of the present invention. Overlying the epitaxial layer 12 and over the field oxide strips 14 and 15 is a layer 17 of polysilicon (polycrystalline silicon), which is suitably deposited to form an electrical conductor. . The doped polysilicon layer 17 is patterned by a process method described below, and is connected to the DRAM cell of the present invention to function as a bit line. The address, access, decode, clock, and other circuits typically required for semiconductor memories are formed around the cell array by conventional processing methods. The method is not described here. Further, while typical arrays embodying the cell structure of the present invention can include up to four million or more cells, only the fabrication of one set of such cells is described below. .

FIG. 2 shows the wafer structure after further processing, with trenches 18 formed through various layers of material to the underlying P + substrate 10. The location of the trench 18 is defined by patterning a layer of photoresist having a rectangular surface opening of approximately 4 microns by 4 microns. Then, plasma reactive ion etching (RIE) is performed on the wafer.
Is performed to remove the material in the opening and the material in the vertical direction. As mentioned above, the sidewalls of the trench 18 are tapered inward as a feature of the reactive ion etching process. The anisotropic etching process is continued until a trench having a depth of about 8 microns is formed. The capacitance of the storage capacitor is
Deeper trenches may be formed for capacitors that are related to the depth of the trenches 18 and therefore are larger. Here, the depth of the trench is defined as a portion corresponding to the P + substrate 10 and the P− substrate 12. In a preferred embodiment of the invention, about 2 million such trenches are formed to implement a 4 mega DRAM. The trenches are used to reduce electrical interference therebetween and between the field oxide strips 14 and
It should be well spaced to provide fifteen.
This is described in detail below.

Next, a layer 20 of silicon oxide is deposited on the array surface deep enough to fill trench 18. Isomorphic oxides such as TEOS are suitable for such purposes. An electrically insulating layer 20 of silicon oxide is then coated with a photoresist 22
Are patterned and anisotropically etched to form a partition across the trench 18 to partition the two regions.

FIG. 3 defines two regions and a rectangular trench
Shows insulation dividers extending along the 18 longer axes. As shown, partition 24 extends to the bottom of the trench and contacts P + substrate 10. After etching the isomorphous oxide 20 to form the partition 24, the photoresist 22
Is removed, portions of the memory array of the wafer are cleaned, and trenches 18 are formed on the sidewalls and bottom surface by silicon dioxide (Si).
O ₂ ) Place in silicon oxidizing atmosphere to form dielectric layer 26. The dielectric layer 26 includes a capacitor dielectric,
It can be as thick as ~ 200 Angstroms.

As further described in FIG. 3, a layer 28 of heavily doped N + polysilicon is deposited on the array surface thick enough to fill the defined area of the trench 18. The H + polysilicon material 28 fills each of the defined areas of the trench 18 and provides an inner plate for each cell capacitor. Approximately one to two microns of N + polysilicon 28 is removed by a suitable etch, and the top surface of N + polysilicon material 28 in a vertical position is somewhat P
-Be in the middle of the epitaxial layer 12; The wafer is then wet etched and N + polysilicon 28
Exposed silicon oxide dielectric 26 without affecting
Is selectively removed. Hydrogen fluoride (HF) solutions treated with a buffer are suitable for such selective oxidative etching. As a result of the wet etch, a portion of the thin silicon oxide layer 16 is also removed, forming recesses 30 and 31, as shown in FIG. Recesses 32 and 33 are also formed by selective wet etching in capacitor dielectric 26. The purpose of such recesses 30-33 is described below in connection with the formation of transistor source and drain regions.

4, a conformal layer 34 of undoped polysilicon is deposited on the array surface thick enough to fill recesses 30-33. Again by wet etching, substantially all of the deposited undoped polysilicon 34, except those filling the recesses 30-33, is removed. FIG. 5 shows the wafer after removal of the isomorphous oxide 34, leaving only those filling the recesses 30-33.

Please refer to FIG. 6 to facilitate understanding of the trench DRAM cell according to the present invention. Here, line 6 in FIG.
FIG. 6 shows a simplified view of a section along -6. Two field oxide strips 14 and 15 formed on each side of trench 18
Is shown. An insulating partition 24 is formed in the trench 18 to partition two regions, each of which is associated with a DRAM cell. Each of the regions is filled with a heavily doped N + material 28 that forms the inner plate of each capacitor. The plate material 28 inside the capacitor is insulated by the capacitor dielectric 26 from the heavily doped P + substrate material 10, which forms the plate outside the cell capacitor. P + substrate 10 surrounds each trench of the array and forms an outer plate common to each cell of the memory array.

6, upper recesses 30 and 31 are shown. These will later form the semiconductor drain regions of the pass transistors of each cell. Importantly, each transistor is formed at an obliquely opposite corner of a defined area of each trench to reduce electrical interference. In addition, the active portion of each cell transistor is formed at a small distance from the corners of the trenches 18, providing more physical,
Prevent the spread of electrical abnormalities. A pair of bit lines 17 and 38
Shown on each side of the trench. Bit lines 17 and 38 are patterned to form the shape shown. It is preferable that such bit line pattern processing is performed at a stage before the trench process. The connection of bit lines 17 and 38 to each cell transistor drain region 30 and 31 will be described below.

The wafer process continues as shown in FIG.
A conformal silicon oxide layer 40 such as TEOS is deposited,
The upper part of the trench 18 is filled with an insulator. Silicon oxide layer
40 is patterned with a photoresist 42 to form a set of word line cylinders, such as reference numbers 44 and 46 indicated by dashed lines. The photoresist opening is small, rectangular, near the diagonally opposite corner of the trench, and defines the active portion of each pass transistor. The exposed silicon oxide material 40 is etched to anisotropically remove material not covered by the patterned photoresist 42. Importantly, the insulating oxide 40 adjacent to the P-epitaxial layer 12 is removed in a subsequent step to form a gate oxide for the vertical transistor. Then, the photoresist 42 is removed.

As shown in FIG. 7, the wafer is then placed in a silicon oxidizing atmosphere where the upper sidewalls of trench 18
A thin layer 43 of silicon oxide is formed. The thin silicon oxide 43 is grown to a thickness of about 250 angstroms and functions as the gate insulator of the MOS pass transistor of each DRAM cell.

In FIG. 8, a conformal oxide layer 40 is shown with cylindrical openings 44 and 46. A layer of doped N + polysilicon is then deposited on the array surface deep enough to fill the cylindrical openings 44 and 46, forming columns of conductive polysilicon. Polysilicon 48 is heavily doped with N-type impurities to provide an electrically conductive material. As previously described, the conductive polysilicon pillars are located adjacent to the diagonally opposite corners of the trench 18. The conductive polysilicon pillars 44 and 46 function as gate conductors of the vertical pass transistor of each cell, respectively, formed in the area defined by the trench 18.

According to another aspect of the invention, the wafer is placed in a high temperature atmosphere to anneal and activate various impurities. In particular, the N + impurities in the N + capacitor plate material 28 are:
It is diffused outwardly through lower recesses 32 and 33 to form buried side contacts 50 and 52, respectively. Such N + semiconductor regions 50 and 52 form the source regions of the pass transistor, respectively. At the same time, the polysilicon bit line
The N-type impurities at 17 and 38 are diffused into the upper recesses 30 and 31, respectively, to form the semiconductor drain regions 54 and 56 of the vertical pass transistor. The P-material 12 between each source and drain region defines a conductive channel for each such pass transistor. Due to the narrow pillars of the gate conductor, only a small area of the transistor conduction channel is inverted during transistor conduction, so that the electric field is P
It is adapted to only a small part of the substance and forms an inverted conducting channel. Due to the small active pass transistor area, the capacitance is reduced and faster address signals are applied to the cell transistors.

The trench transistor cell of the present invention is written and read as follows. In the write operation of the rightmost cell of FIG. 8, the charge is stored on the N + capacitor plate, and the access circuit (not shown) passes a word line voltage on the word line 58 of about 5 volts. Such a voltage is applied to the gate oxide 36
Is effective in adapting the electric field through the transistor, and therefore between 50 and 54 of the transistor source and drain regions.
Invert a small portion of the lightly doped P-material 12. Such a transistor becomes conductive and connects bit line 17 electrically to capacitor plate 28 on the inside. If the bit lines were previously charged to a logically high level, such charges would be transferred to N + material 28, forming a capacitor plate inside the rightmost cell. On the other hand, if bit line 17 is previously charged to a logically low level, little or no charge is transferred to plate 28 inside the capacitor.

The read operation of the cell is almost identical to the write operation, except that the outer sense amplifier (not shown) is connected to bit line 17 to detect whether the storage capacitor has been precharged. . If pre-filled, charge is transferred from inner capacitor plate 28 to bit line 17 via a pass transistor. Such charges are sensed by the sense amplifier,
It is converted into a signal of a normal logic level. In a preferred embodiment of the invention, the outer common capacitor plate,
+ Substrate 10 is connected to a potential of about 2.5 volts.

The read and write operations of the leftmost cell of the trench 18 are:
This is achieved by accessing the word line 60 and sensing the stored charge on the bit line 38. The theory of the operation of the trench transistor is described in detail in a technical paper "Model of a Trench Transistor" by Benaji et al. In the August 1987 IEEE Transaction on Electron Device. The description is incorporated herein by reference.

Referring again to FIG. 8, it can be seen that bit lines 17 and 38 are formed over thick field oxide regions 14 and 15. This is in contrast to other memory structures where the bit lines are linearly diffused into the underlying semiconductor material. The bit line structure of the present invention allows the field oxide strip 14 and
15 functions as an insulator between the main part of each bit line 17 and 38 and the lightly doped semiconductor layer 12. Therefore, any alpha particles that can enter the semiconductor layer 12 are less likely to electrically affect the precharged nature of the bit lines 17 and 38. Thus, the rate of soft errors in DRAMs manufactured according to the present invention is reduced. Therefore, the reliability of the memory is also improved as compared with the conventionally known DRAM.

In addition, the isolation of the bit lines 17 and 38 from the underlying P-type semiconductor layer 12 significantly reduces the junction capacitance therebetween. As the bit line capacitance decreases, most of the charge that can be stored in the cell capacitors is transferred to the sensing circuit and not lost due to the bit line parasitic capacitance. Also, the speed characteristics of the memory cell are enhanced.

FIG. 9 shows a plan view of six DRAM cells according to the present invention formed in three trenches 28, 62 and 64, respectively. Pass transistors are designated by reference numerals 66-76. The trench structure described thus far is formed by two memory cell transistors 66 and 68, each associated with a separate word line 60 and 58. Similarly, the adjacent trench 62 has a memory
Form cell transistors 70 and 72. Pass transistors 70 and 72 are also associated with each word line 60 and 58.
A trench structure 64 having a set of 76 memory cell transistors 74 is driven by another set of word lines 78 and 80. It should be understood that the word lines described above have been adapted to drive many other trench structured cells of the array.

According to an important feature of the present invention, bit line 17 is common to memory cell trench structure transistors 68, 70, 76, and other trench cell transistors not shown. Bit line 17 overlaps the main portion of thick field oxide strip 14, reducing capacitors as described above. In addition, bit lines 17 include notches, such as 82 and 84, formed between adjacent cells. The bit line material at such notched locations is unnecessary for the operation of the various memory cells, and therefore the bit lines are patterned so that they do not overlap the underlying semiconductor material 12 at such locations. Is being processed. This further reduces the capacitance of bit line 17 and allows for faster operation of the memory. All bit lines in a typical memory array can be manufactured in a similar manner.

Also, as is apparent from FIG. 9, the word line columns 44 and 46 associated with the path transistors 66 and 68 have a small cross-sectional area and therefore reduce word line capacitance. As a result of the reduced word line capacitance, various memory cells according to the present invention can be accessed with faster address signals.

Above, a plurality of cell transistor structures have been described. This structure offers distinct advantages over other trench cell memories known in the art. A technical advantage of the present invention is that if multiple cells are provided in a single trench, such trenches can be made larger and deeper, thus increasing the storage capacity of the cell capacitor. You. Another technical advantage of the present invention is that providing conductive bit lines on an insulating oxide strip reduces the capacitance of such bit lines. As a result, not only the speed characteristics of the memory are improved, but also the soft error rate is improved due to the alpha particle strike. Another technical advantage of the present invention is that small word line pillars connect the conductive word line to the pass transistor of each cell, thereby reducing capacitance and improving memory speed characteristics.

Although the present invention has been described in terms of what appears to be the most substantial and preferred embodiments, modifications may be made without departing from the scope of the invention. Such changes should include some and all equivalent devices and functions,
It is limited to the claims.

 The following items are disclosed in connection with the above description.

(1) A semiconductor trench memory cell structure includes a semiconductor substrate in which a trench is formed, an electrical insulator that partitions the trench into a plurality of regions, and a storage capacitor in each of the partitioned regions. A semiconductor trench memory cell structure wherein a transistor is formed on each of the capacitors and electrically connected to the associated pasta, thereby providing a plurality of memory cells in a single trench.

(2) In the trench memory cell structure described in (1), each of the transistors includes a vertical transistor formed adjacent to a sidewall of the trench.

(3) In the trench memory cell structure according to (1), each transistor includes a drain semiconductor region, and a source semiconductor region and a conductive channel are formed in the substrate material.

(4) In the trench memory cell structure according to the item (3), the substrate includes a thickly doped semiconductor region layer and a lightly doped semiconductor layer, and the trench is formed in both the layers. The transistor source and drain regions are formed in the lightly doped semiconductor region.

(5) In the trench memory cell structure described in the paragraph (3), each of the transistors includes a gate insulator, and a gate conductor is formed perpendicular to the trench.

(6) In the trench memory cell structure according to the item (1), each of the transistors is formed adjacent to a corner of the trench.

(7) In the trench memory cell structure described in the above (6), each of the transistors is formed at a diagonally opposite corner of the trench.

(8) In the trench memory cell structure described in the paragraph (6), each of the transistors is slightly apart from a corner of each of the trenches.

(9) The trench memory cell structure described in (1) further includes a set of bit lines, each bit line being separately connected to the transistor.

(10) In the trench memory cell structure according to (9), each of the bit lines overlaps with an insulator strip, and at least a part of the bit line is electrically insulated from the substrate.

(11) In the trench memory cell structure described in the paragraph (10), each of the bit lines includes a concave region at a position not overlapping with the insulating strip.

(12) The trench memory cell structure according to (1) further includes a set of word lines, each word line associated with and connected to the separate transistor, and each word line connected to the trench. And a pillar of a conductive material that functions as a gate conductor of each of the transistors.

(13) The trench memory cell structure according to (1) further includes a combination of a plurality of the trench memory cell structures connected by a plurality of bit lines and a plurality of word lines, and To form

(14) The trench memory cell structure described in (13) further includes a combination of access and decode circuits around the array to form a random access memory.

(15) A semiconductor trench memory cell structure includes a semiconductor substrate in which a trench is formed, an electrical insulator that partitions the trench into a plurality of regions, and a capacitor dielectric includes a partition in each of the trenches. A doped semiconductor material formed on sidewalls and a bottom surface of the formed region, deposited on the partitioned region of each of the trenches to form a plurality of storage capacitors, and an inner capacitor plate deposited thereon. Defined by a semiconductor material, an outer capacitor plate is defined by the semiconductor substrate material, and the inner and outer capacitor plates are:
A vertical pass transistor associated with each of the capacitors, wherein each of the transistors is formed on one sidewall of the trench and includes a semiconductor drain region formed in the substrate; Electrically connected to the inner capacitor plate via a capacitor dielectric, a transistor conductive channel is formed in the semiconductor substrate, a semiconductor source region is formed in the semiconductor substrate,
A set of semiconductor drain regions formed in the semiconductor substrate, separated from the source region by the conductive channel, a gate insulator formed on sidewalls of the trench, and formed proximate to the conductive channel; A conductive polysilicon bit line is connected to each transistor / drain region, an insulator is formed between each bit line and the semiconductor substrate, and a conductive polysilicon word line is connected to each of the transistor and drain regions. A semiconductor trench comprising a set of conductive pillars, each pillar extending into the trench and forming a gate conductor of the respective transistor.
Memory cell structure.

(16) In the trench memory cell structure according to the above (15), the semiconductor substrate includes a semiconductor material of a first conductivity type, and the inner capacitor plate includes a semiconductor material of a second conductivity type. Including.

(17) In the trench memory cell structure described in the item 16, the semiconductor sources, the semiconductor drains, and the polycrystalline silicon bit lines include the impurities of the second conductivity type.

(18) In the trench memory cell structure according to (15), each of the transistors extends vertically, and electrically connects each of the capacitor inner plates to an associated one of the bit lines. It has a significantly smaller lateral width than the sidewall on which the transistor is formed.

(19) In the trench memory cell structure described in the above item 15, the trench is rectangular, and each of the transistors is formed at an opposite corner of the trench.

20. The trench memory cell structure according to claim 15, wherein the substrate includes a heavily doped layer and a lightly topped layer, and wherein the heavily doped layer includes the outer capacitor plate. .

(21) In the trench memory cell structure described in the item (20), a portion of the transistor is formed in the lightly doped layer.

(22) In a method of manufacturing a semiconductor memory cell, a trench is formed in a semiconductor substrate, an electrical insulator is formed, the trench is divided into a plurality of regions, and a storage capacitor is formed in each of the divided regions. A method of manufacturing a semiconductor memory cell, comprising: forming a transistor on each of the capacitors; and electrically connecting to the associated capacitor, forming a plurality of memory cells in a single trench.

(23) In the method described in the paragraph (22), further, each of the transistors is formed as a vertical transistor adjacent to a sidewall of the trench.

(24) The method according to the above (22), further comprising forming the transistors having a semiconductor drain region, a semiconductor source region and a channel region on the semiconductor substrate.

(25) The method as described in (24), further comprising forming each of the transistors having a vertical gate insulator and a gate conductor adjacent to the trench.

(26) The method according to the above (22), further comprising forming each of the transistors adjacent to a corner of the trench.

(27) In the method described in the paragraph (26), each of the transistors is formed at a diagonally opposite corner of the trench.

(28) In the method described in the paragraph (26), the transistors are further formed at a small distance from a corner of the trench.

(29) In the method described in the paragraph (22), further, a set of conductive bit lines is formed, and each bit is connected to the transistor separately.

(30) The method according to (29), further comprising forming each of the bit lines on an insulating strip, and electrically insulating at least a portion of the bit lines from the substrate.

(31) In the method described in the paragraph (30), further, a recessed region is formed at a position where each of the bit lines does not overlap with the insulator strip.

(32) The method according to paragraph 22, further comprising forming a set of word lines, each load line associated with and connected to a separate one of the transistors, each of the word lines extending to the trench, A pillar of conductive material is formed that functions as the gate conductor of each transistor.

(33) The method according to (22), further comprising: forming a plurality of trench memory cell structures on the semiconductor substrate surface, the plurality of trench memory cell structures being connected by a plurality of bit lines and a plurality of word lines; Form an array.

(34) In the method described in the paragraph (33), further, an access and decode circuit is formed on the semiconductor substrate around the memory array to form a random access memory.

(35) A method for increasing the cell density of a memory array is to form a deep trench in a semiconductor substrate material in which opposing sidewalls are tapered inward, and to form the trench with a sufficient width to reduce the taper. A cell in a memory array, wherein the trench is formed to a desired depth without gathering sidewalls at one point, a plurality of memory cells are formed in the trench, and each cell is electrically isolated from other cells. How to increase density.

(36) The method according to the above (35), further comprising forming each of the cells having a transistor and a storage capacitor, forming an outer plate common to an inner plate electrically insulating the storage capacitor, A dielectric is formed between the inner plate and the common outer plate.

(37) In the method described in the paragraph (35), further, a conductive bit line is formed adjacent to the trench, and an insulator is formed between the bit line and the semiconductor substrate.

(38) In the method described in the paragraph (35), further, each of the transistors is formed on a part of a surface of one sidewall of the trench.

(39) The method according to the paragraph (35), further comprising: forming a plurality of the trenches and associated cells to form an array.

(40) Multiple DRAM cell trench structures increase cell capacitance. A deep trench 18 is formed in the P + semiconductor substrate 10 and the width of the trench is sufficiently large to prevent the tapering trench sidewall from pinching off at the bottom. A plurality of memory cells are formed in trench 18 to increase the cell density of the array. Field oxide strips 14, 15 are formed of conductive polysilicon bit lines 17,
Formed between 18 and the P-substrate 12, it reduces the capacitance and soft error rate of the cell.

[Brief description of the drawings]

FIGS. 1-5, 7 and 8 are drawings according to the present invention.
FIG. 2 is a different cross-sectional view of a semiconductor wafer, illustrating different process stages of the manufacture of a DRAM cell. FIG. 6 is a cross-sectional view of the DRAM cell structure of FIG. 5 taken along line 6-6. FIG. 9 is a plan view of a multiple trench memory cell according to the present invention. Explanation of main symbols 10: substrate 12: epitaxial layer 14, 15: field oxide strip 17, 38: bit line 18, 62, 64: trench 22: photoresist layer 24: insulator partition 26: dielectric layer 30, 31, 32, 33: recess 54, 56: semiconductor drain region 58, 60: word line 66, 68, 70, 72, 74, 76: pass transistor 82, 84: notch

Claims (1)

(57) [Claims] 1. A semiconductor trench memory cell structure, comprising: a semiconductor substrate having a trench formed therein; an electrical insulator dividing the trench into a plurality of regions; Each comprising a storage capacitor formed such that the space between the storage capacitors is filled by the insulator; and a transistor formed on each of the capacitors and connected to the associated capacitor, and A semiconductor trench memory cell structure, wherein a plurality of memory cells are provided in one trench.