JP2647383B2 - Waveform generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

 [Technical Field of the Invention] The present invention relates to a waveform generation device for generating a plurality of periodic signals.
About the installation. [Prior art and its problems] Conventionally, for example, a liquid crystal printer
(Hereinafter referred to as LCS).
Optical data writing of image data by opening and closing the shutter
An image is being formed. In order to perform optical writing at high speed, low frequency f_LAnd high
Frequency f_HControl the liquid crystal optical shutter by the two-frequency drive of
I have. Furthermore, drive elements, the number of wires, and the mounting area are reduced.
Time-division driving is performed to reduce the size. FIG. 17 shows such a liquid crystal optical shutter by time division.
Generates drive signal and timing signal for two-frequency drive
LCS drive signal generation circuit in the liquid crystal printer
FIG. FIG. 18 (a) shows the LCS
FIG. 9 is a timing chart showing the operation of the drive signal generation circuit,
FIG. 18 (b) shows data DS stored in ROM2 (described later).
It is a figure which shows the content of TATUS. Fig. 17 and 1
8 Conventional LCS drive signal generation with reference to FIGS.
The configuration and operation of the circuit will be described. First, in FIG. 17, the counter 401 is n-ary (n ≦
Two^m) Is a counter, input through the inverter 404
0 in synchronization with the inverted clock signal of the clock signal φ
Count n-1 and output terminal Q₀(LSB) to Q_m-1(MS
B) from block address signal BLADR to ROM (Read Only M
emory) 402 address input terminal A₀~ A_m-1Output to B
The lock address signal BLADR is as shown in FIG.
Have values of 0 to n-1 and clock signals in the order of 0 to n-1.
Cycle T at the rising edge of the signal_WIn ROM4
Entered in 02. In the ROM 402, as shown in FIG.
Data DSTATUS is stored at addresses 0 to n-1
I have. ROM402 terminal ▲ ▼ (Chip Enable) and terminal ▲
▼ (Output Enable) are both grounded,
Is active (L level).
Input terminal A₀~ A_m-1Block address signal BLADR is input to
Every time, the data output terminal D of the ROM 402₀~ D₇Block from
The data DSTATUS corresponding to the address BLADR is
Data input terminal D₀~ D₇Is output to Also, input terminal A_m, A_{m + 1}Is provided
Input terminal A_m, A_{m + 1}Input the page selection signal to
, Four types of pages can be selected. Follow
Change the contents of the data DSTATUS for each page
By setting, four types (LCS drive signals COM1, COM2, P
T1, PT2, timing signals DSEL, ▲ ▼, TWSX)
Sets can be generated. The clock signal φ is input to the terminal CK of the latch 403.
Data input in synchronization with the rise of the clock signal φ.
Force terminal D₀~ D₇Output terminal D of ROM402₀~ D₇Output from
Data DSTATUS is input and the next clock signal φ rises
It is held until the glue. Data DSTAT input to latch 403
US is output terminal Q₀~ Q₆From the LCS drive signal PT1,
PT2, COM1, COM2 and timing signal DSEL, ▲
▼, output as TWSX. Also, the output of latch 403
Terminal Q₇From the reset signal of the n-ary counter 1
The data DST (n-1) shown in FIG.
When input, it is output to the reset terminal R of the n-ary counter 1.
It is. Therefore, the n-ary counter 1 is 0 to n-1 (the ROM 402
Address), and then latch 40 from ROM402.
Value of bit 7 of data DST (n-1) output to 3 is "1"
(See FIG. 18 (b)). latch
LCS drive signals COM1, COM2, PT1, PT2 output from 403 are
It is output to a recording control unit (not shown) and
Used to control two-frequency drive by LCS time division
You. Thus, in the conventional LCS drive signal generation circuit,
Is LCS by data DSTATUS fixedly stored in ROM2.
Drive signals COM1, COM2, PT1, PT2 and timing signal DS
LCS drive waveforms such as EL, ▲ ▼, and TWSX are generated.
You. However, due to advances in liquid crystal technology and changes in specifications,
Improvements and changes in the liquid crystal material used in the liquid crystal optical shutter
Operating characteristics of the liquid crystal optical shutter may change. This
At this time, the data is stored in ROM2 like the conventional LCS drive signal generation circuit.
Only fixed LCS drive waveforms based on stored data DSTATUS
Change or improve liquid crystal material for waveform generators that cannot generate
Can quickly respond to changes in LCS drive waveform specifications
It is difficult to generate the optimal LCS drive waveform
There was a problem. [Object of the invention] In view of the above-mentioned conventional problems, the present invention
To obtain various drive waveforms.
External control of optimal drive waveforms according to specifications
Provides a waveform generator that can be generated more easily
The purpose is to do. [Summary of the Invention] The above object is achieved according to the present invention by address generation means,
Code data specifying the shape, and
Step data for specifying the number of steps
Data of a plurality of frames as a
The data of the one frame is determined according to the address generated by the generating means.
First storage means for outputting data, the code data,
An ad created from the fundamental frequency signal of the waveform to be generated
Address or the address generated by the address generation means.
Selecting means for selecting and outputting one of them, and output of the selecting means
Is input and outputs waveform data.
Storage means, and the switch output from the first storage means.
Measure the period of one frame based on the step data and obtain the measured value
The next one frame of data to the address generating means
Measuring means for instructing the output of
This is achieved by providing a waveform generating device. Examples Examples of the present invention will be described below with reference to the drawings.
I will tell. FIGS. 1A, 1B and 1C show an embodiment of the present invention.
Block showing the circuit configuration of the LCS drive signal generation circuit
FIG. In FIG. 2A, memory 1 and memory 2 are
This is a static RAM with a 4-bit x 32-word configuration.
Mori 1 has a macro code MAC (x) and its macro code
ST (x) H, ST (x) L
However, data DSTATUS for generating LCS drive waveform is stored in memory 2.
Is stored. Here, the macro code MAC stored in the memory 1
(X), configuration of the number of development steps ST (x) H, ST (x) L
Is shown in FIG. 4 (a). As shown in FIG.
ST (0) L, S in the order of block address (BLADR)
T (0) H, MAC (0), MAC (1), ST (2) L, ...
・, ST (14) L, ST (14) H, MAC (14), MAC (15)
The stored address (BLADR) shown in FIG.
= 2x to 2x + 3, ST (x) L, ST (x) H, MA
One frame is composed of C (x) and MAC (x + 1)
(However, x is an even number of 0, 2,..., 12, 14). here
Where ST (x) L and ST (x) H are the number of development steps, respectively.
Lower 4 bits and upper 4 bits of
Is 8-bit data. The number of expansion steps [ST
(X) L and ST (x) H are expressed as ST (x). Therefore, 0
≤ ST (x) ≤ 255, and the number of development steps ST (x) is
In theory, you can specify from 0 to 255 steps
it can. FIG. 4 (c) shows the number of development steps ST (x) L,
Specific data of ST (x) H, MAC (x), MAC (x + 1)
An example is shown below. The connection configuration of the memory 1 will be described first.
Signal input terminal A₀~ A_FourEach have an up counter
3 Q_A~ Q_EOutput (BLADR) is input. Note that Q_AIs at the bottom
Bit, Q_EIs the most significant bit. Also enter data
Terminals WD0 to WD3 are connected to input data bus iDB0-3.
To the memory 1 via the input data bus iDB0-3.
Mode MAC (x), MAC (x + 1) and macro code MAC
(X), number of development steps ST (x) L, S of MAC (x + 1)
Writing of T (x) H is performed. Also, from memory 1
The read macro codes MAC (x), MAC (x + 1) and
ST (x) L and ST (x) H are the data
Latches 4-1 and 4-2 from output terminals RD0 to RD3, respectively.
4-3, 4-4 and a data selector 5
Output to Further, the data output from the data selector unit 6 is output.
Macro code MAC
(X), MAC (x + 1) and the number of development steps ST
Read / write of (x) L, ST (x) H is performed
You. Next, the up counter 3 counts from 0 to 31.
CK, R
Pulse signal BLCLK and reset signal RBLADR
And is triggered by the rise of the pulse signal BLCLK.
And reset by the reset signal RBLADR (H level).
It is reset to the initial value (0). Also an up counter
3 uses the count value BLADR as the block address signal
Output to memory 1 and count value BLADR is “3”, “31”
And set the signals BLAD (3) and BLAD (31) to H level
The NAND gate 7 and the AND gate shown in FIG.
To Step 8. Furthermore, the count value of the up counter 3
The lower two bits of the BLADR signal are_A, Q_BFrom
Output to the decoder 9. When the value of the terminal G is “1” (H level), the decoder 9
Depending on the value to be output to the slaves A and B,
This is a decoder for setting to L level. Terminals A and B of decoder 9
Has the count value BLAD of the up counter 3 as described above.
Since the lower 2 bits of R are input, the decoder 9
When DR is “2x ＋ 0”, the output of terminal Q0 is output.
When the output of the child Q1 is “2x + 2”, the output of the terminal Q2 is “2x +
At 3 ", the output of terminal Q3 is set to L level (however,
And x is an even number from 0 to 14). Output of terminal Q2 (MACLL), end
Output of child Q3 (MACHL), output of terminal Q0 (STLL), terminal Q1
Outputs (STHL) are latches 4-1, 4-2, 4
-3, 4-4. Latches 4-1 and 4-
2, 4-3, and 4-4 are the rising edges (L
Latch 4-bit input data D at level → H level
I do. Outputs of the latches 4-3 and 4-4 are data selectors.
Check that the select signal ISEL output from the
Or when the count value of the down counter 10 becomes “0”
Down counter 10 at rising edge of clock signal ▲ ▼
Is set to The down counter 10 has an 8-bit input (terminal
Down counters for children a to h), up to 2⁸= 128 times
Perform a count. And when the count value becomes "4"
The output of the terminal ST (4) is set to the H level as shown in FIG.
When the count value becomes "1" in addition to AND gate 8
Set the output of terminal ST (01) to H level to AND gate 11.
Add. Furthermore, when the count value is “0”, the carry signal
Set STCY to H level, NAND gate 7, flip-flop
To the terminal K of the loop 12. The data selector 13 will be described later.
When ISEL is at H level, the output of flip-flop 14
Output and latch of latch 4-1 by select signal SELMAC
Lock signal φ₃Or the output of latch 4-2 and the clock.
Signal φ₃Data address signal DADR
Is output to the memory 2. Circuit structure of data selector 13
The result is shown in FIG. In the circuit diagram shown in FIG.
And input terminal A₀~ A_ThreeOutput from latch 4-1
Code MAC (x) is input terminal B₀~ B_ThreeAnd the latch 4-2
The macro code MAC (x + 1) to be output is input terminal C₀~ C
_FourThe block address signal B output from the up counter 3
LADR generates the clock signal φ input to the input terminal D.₃But outside
Internal select output from data selector 6 to external terminal G
The signal ISEL is output from the flip-flop 14 to the select terminal S.
Input macro data select signal SELMAC
You. The operation of the data selector 13 will be described with reference to FIG.
Then, the terminal S (SELMAC) = "0" (L level) and the terminal
When G (ISEL) = "1" (H level), output terminal Y₀~ Y_FourOr
La A₀~ A_ThreeInput (macro code output from latch 4-1)
MAC (x)), D input (clock signal φ₃)｝ Is the terminal
S (SELMAC) = "1" (H level) and terminal G (ISEL) =
When “1” (H level), output terminal Y₀~ Y_FourFrom ｛B₀~ B_ThreeEntering
Force (macro code MAC (x +
1)), D input (clock signal φ₃)｝ Is connected to terminal G (IS
EL) = "0", output terminal Y₀~ Y_FourFrom ｛C₀~ C_FourInput (A
Block address signal BLAD output from the top counter 3
R)｝ is the address signal of memory 2 as the address signal DADR.
Signal input terminal A₀~ A_FourOutput to Next, the memory 2 stores the data input from the data selector 6.
Input from data selector 13 by input signal ▲ ▼
To the address specified by the address signal DADR
Reads / writes data DDATA. Memory 2 data
Data input terminal WD₀~ WD_ThreeIs connected to the input data bus iDB0-3
Input data when ▲ ▼ is at L level
Writing of macro data DDATA via bus iDB0-3
Done. The 4-bit data read from the memory 2
The lower two bits of the macro data DDATA are the data output terminals RD₀
~ RD₁To the data selector 15 shown in FIG.
2 bits are the data output terminal RD_Two~ RD_ThreeData selector from
Output to 16. The circuit configuration of the data selectors 15 and 16
It is shown in FIG. As shown in FIG.
When terminal G is at L level, Y₀, Y₁Output fixed at H level
Is determined. Further, the terminal G is at the H level and the selector terminal S
A when L is at L level₀, A₁B if input is H level₀,
B₁Inputs selected, each Y₀, Y₁Output. This implementation
In the example, the external terminal is connected to the select terminal S of the data selector 15.
Control signal PTSEL from the
Input terminal S receives the Q output (DSELQ) of flip-flop 17
I'm working. Also, the terminal RD of the memory 2₀And data select
Terminal 15 of terminal 15₀, B₁Is the terminal RD of the memory 2.₁And data select
Terminal 15 of terminal 15₁, B₀Is the terminal RD of the memory 2._TwoAnd data select
Terminal A of terminal 16₀, B₁Is the terminal RD of the memory 2._ThreeAnd data select
Terminal A of terminal 16₁, B₀Are connected to each other,
Rector 15 Y₀, Y₁The output is the terminal D of the latch 18, respectively.₁, D_TwoTo
Y of data selector 16₀, Y₁Each output is at the end of a latch 18.
Child D_Three, D_FourIs being entered. Therefore, the data selector 15 sets P
RD of memory 2 by TSEL control₀, RD₁Output and latch 18
Input terminal D₁, D_TwoSwitch the connection with. Also described below
DSELQ has a period T_WL level, period T in the first half of_Wof
H level in the latter half, so period T_WIn the first half of memory 2
RD_Two, RD_ThreeOutput is D of latch 18_Three, D_FourInput, period T_WAfter
Half, RD_Three, RD_TwoD of output latch 18_Three, D_FourInput. The latch 18 has the Y of the data selectors 15 and 16 described above.₀, Y₁
In addition to the output, the output of flip-flop 17 (DSELQ)
Output of lip flop 12 (▲ ▼)
The output of port 19 (▲ ▼) is connected to terminal D_Five~
D₇Is being entered. Latch 18 is externally input to terminal CK
Clock signal φ₁Terminal D in synchronization with the rising edge of₁~
D₇Input data from. Latch 18 Q₁~ Q₇Output is LCS driven via buffer unit 20
Signals PT1, PT2, COM1, COM2 and timing signal DSEL, ▲
▼ and ▲ ▼ for recording control unit 200 described later
Output, Q₇The output is the inverse of the output.
Video interface unit 4 described below as the
Output to 0. Furthermore, carry signal STCY output from down counter 10
Is the inverter 21, the NAND gate 7, and the inverter shown in FIG.
Input to terminal k of lip flop 12. Inverter
21 outputs are toggle flip-flops with enable
Input to terminal E of a certain lip flop 14,
The flip-flop 14 detects that the carry signal STCY is at the H level,
When the output of the inverter 21 is at the L level, it is enabled.
Rising of the external clock signal ▲ ▼ input to the terminal CK.
The Q output (SELMAC) of flip-flop 14 is
Turn over. ND to be input to SELMAC, STCY, BLAD (3)
The output of port 7 is a toggle flip-flop with enable
Is input to the terminal E of the flip-flop 17
Q output (DSELQ) of lip flop 17 is SELMAC, STC
Input to terminal CK when Y and BLAD (3) are all H level
Inverted by the rising edge of the external clock signal ▲ ▼
I do. Also, the reset terminals R of the flip-flops 14 and 17
Select signal ▲ output from data selector unit 6
▼ is input and ▲ ▼ is H level
(External control state), SELMAC and DSELQ become L level
Become. ST01, flip-flop output from the down counter 10
Q output of rop 14 (SELMAC) and external clock signal φ₁
Is input to AND gate 11, ST01 and SELMAC are H
During the level, the clock signal φ₁Passes through AND Gate 11
Pulse signal iBLCLK and input to the data selector 6
I do. Also, the Q output of the flip-flop 14 (SELMAC),
Q output of flip-flop 17 (DSELQ), up-count
BLAD (31) output from the counter 3 and the output
ST4 is input to AND gate 8 and
The output of 8 (TSXQ) is cycle T_WThe second half of (T_W/ 2) at SELM
AC and DSELQ are at H level and BLAD (31) is at H level
At some point, when ST4 goes high, it goes high and free.
It is added to the terminal J of the flip-flop 12. Flip-flops12
Is a JK type flip-flop, and
The carry signal STCY output from the counter 10
I have. Q output of flip-flop 12 (▲ ▼)
Is the terminal D of the latch 18.₆And the output is
Enter in the address 19. The data selector section is provided on the NAND gate 19.
When ISEL output from 6 is input and ISEL is at H level
(Internal control state) The Q output of flip-flop 12
After passing through gate 19, it becomes ▲ ▼ and latches
18 terminal D₇To enter. The data selector section 6 receives a select signal input from the outside.
Invert number iSEL and flip ▲ ▼ to flip-flop 14,1
Inverter 6a that outputs to reset terminal R of 7
Invert the ▲ ▼ output from the
Counter 10, inverter 6b that outputs to NAND gate 19,
Pulse signal iBLCLK output from the
External clock signal when ISEL output from
φ₀Gate that passes through and outputs to NAND gate 21
6c, ▲ ▼ output from inverter 6a and external selector
When the signal MEMSEL is at the H level,
Pass through signal XMWR
The NAND gate 6d that outputs to the terminal 21 and the terminal WE of the memory 1
When ▲ ▼ output from inverter 6a is at H level
Passed through external reset signal XRBLAD
A reset signal RBLADR is applied to the reset terminal R of counter 3
AND gate 6e that outputs the signal and ▲ that outputs the inverter 6b
Output from AND gate 11 when ▼ is at H level
AND gate 6f for passing pulse signal iBLCLK,
Input from outside when ISEL output from
6g that passes the pulse signal XBLCLK
IBLCLK output by gate 6f and output gate of AND gate 6g
And input one of them to the up counter 3
OR gate 6h to output to clock terminal CK and external select
Inverter 6i that inputs and inverts the
Output of inverter 6i and ▲ ▼ (output of inverter 6a
Force) is H, the write control signal XMWR is inverted and passed
As a write control signal ▲ ▼, it is applied to the terminal WE of the memory 2.
Nando gate 6j. Further, the data selector 5 receives the external select signal MEMSEL.
Output data terminal RD of memory 1₀~ RD_ThreeRead from
Data or output data terminal RD of memory 2₀~ RD_ThreeFrom
Select the read data and output data bus ODB0-3
It is a selector to output above. Next, the configuration of the video interface unit 40 is shown in FIG.
This will be described with reference to FIG. Video interface
The video unit 40 receives video data HLTXD from the outside
Latch in synchronization with clock ▲ ▼
Then, buffering is performed and the recording control unit 200 (described later) performs buffering.
Output and divide the clock ▲ ▼
Generates two clock signals ▲ ▼, ▲ ▼
Interface circuit for outputting to the recording control unit 200.
You. The circuit configuration will be described in more detail.
HLTXD is inverted by the inverter 40a and then
D input of flip-flop 40b. Also, input from outside
Clock signal ▲ ▼ to the inverter 40c
After inversion, the clock terminal C of the flip-flop 40b
K, the inverted signal of the video data HLTXD.
▼ indicates the falling of the clock signal ▲ ▼
The beam is latched by the latch 40b. Flip-flop
After the Q output of the loop 40b is inverted by the inverter 40d,
Record control unit 200 as video data LXTD by buffer 40e.
Is output to On the other hand, the clock signal ▲ output from the inverter 40c
▼ inverted signal HLTXCK is the flip-flop 40f
Input also to terminal T and inverter 40g. Flip flow
Flip-flop 40f and flip-flop 40h are cascaded
HLTXCK is 1/4 by flip-flops 40f and 40h
Divided and the Q output of flip-flop 40h is NAND gate
To the terminal S of the flip-flop 40k. Ma
The output of flip-flop 40h is connected to NAND gate 40j.
Input, Q output of flip-flop 40k is NAND gate 4
Input to 0i and 40j. In addition, NAND gates 40i and 40j
Input ▲ ▼ through the inverter 40g
Output of the latch 18 (LTWSX)
Barta 40_rThrough flip-flops 40f, 40h, 40k
Input terminal R. Exit of Nandgate 40i, 40j
The force is applied to the clock signal via buffers 40l and 40m, respectively.
Input to the recording control unit 200 as ▼ and ▲ ▼
You. Clock signals ▲ ▼, ▲ ▼ are HLTXCK
Clock that generates two clock pulses alternately in synchronization with
Signal. Next, the LCS drive signal generation circuit configured as described above
The operation of will be described. At startup, iSEL and DRVEN reset to L level.
Is set. First, L is applied to the terminals G of the data selectors 15 and 16.
With the addition of the level DRVEN, the data selector 15,
16 Y₀, Y₁All outputs are fixed at H level. this child
And the LCS drive signal applied to the LCS signal electrode (not shown)
LCS drive signal applied to common electrodes (not shown) of PT1, PT2, LCS
Signals COM1 and COM2 have the same potential, and an unexpected voltage, especially
The application of the current voltage is prevented. Also, if iSEL is L
External control mode is reset by resetting
Pulse signal XBLCLK, block signal
Address signal XBLAD, write control signal XMWR, and select
Signal MENSEL becomes valid. The data selector 6
▲ ▼ becomes H level via
Q output (SELMAC, DSELQ) of flip-flops 14 and 17 is L level
And the external clock signal φ₁Passes through AND Gate 11
No, the generation of the internal pulse signal iBLCLK is stopped. Furthermore,
ISEL becomes L level and is applied to terminal G of data selector 13.
Data selector 13 is C₀~ C_FourInput (up cow
Block address signal BLADR output from
Select the address signal input terminal A of the memory 2₀~ A_FourOutput to
I do. Also, SELMAC and DSELQ become L level and
Since it is added to the gate 8, the output TSXQ of the AND gate 8 becomes L
Fixed to level and applied to terminal J of flip-flop 12.
You. Therefore, the Q output of the flip-flop 12 (▲
▼) is fixed at L level, and latch 1
8, the pulse signal output via the buffer unit ▲
The occurrence of ▼ is stopped. For this reason, as will be described later.
In addition, the recording control unit 200
Stop inputting the video signal to be input. iSEL L level
The reset signal XRBLAD (H level)
In this way, the up-counter
RBLADR (H level) is added to the reset terminal R of 3
If the up counter 3 is “00000 B” (B is a binary
Number). Then, from outside, the pulse signal XB
By inputting LCLK to the data selector section 6, the data
Pulse signal BLCLK from the data selector section 6 is an up-counter
3 clock terminal CK, and the up counter 3
Undone. The count value of up counter 3 is
Input address signal of memory 1 as address signal BLADR
Force terminal A₀~ A_FourAnd terminal C of data selector 13₀~ C_FourEnter in
I do. Then, via the data selector 13, the memory 2 is accessed.
Dress signal input terminal A₀~ A_FourBlock address signal BLAD
R is supplied. At the time of initial setting, either memory 1 or memory 2
Although it is not limited whether data is written first to the memory,
It is preferable to write data to the first data. Therefore, outside
Set the select signal MEMSEL from the
By the pulse input of the control signal XMWR, the data selector 6
Write signal ▲ ▼ is applied to terminal WE of memory 2.
To do. Hereinafter, simply write the macro data DDATA to the memory 2
(ISEL = DRVEN = MEMSEL = L level)
Input terminal WD₀~ WD_ThreeTo output macro data DDATA. The data input is controlled by the pulse input of the external write control signal XMWR.
Write signal ▲ ▼ (L level)
To the terminal WE of the memory 2. This allows the macro
Data DDATA is the address specified by the block address signal BLADR.
Written on the dress. Data selector section by applying pulse signal XBLCLK from outside
6 to the pulse signal BLCLK of the up-counter 3.
To the terminal CK. As a result, the up counter 3
Count and advance the block address signal BLADR. As described above, the macro data of one block is
Data DDATA is written to the memory 2. Then, the operation of ~ is repeated, and all blocks are
Is written into the memory 2. After the writing is completed, the data selector 5 and the output data
Macro data written via data ODB0-3
DDATA is read from the memory 2 and the macro data DDATA
Check the contents (verify). As a result of verification, macro data DDATA of all blocks
Is correct, the memory select signal MEMS
Switch EL to H level and expand to memory 1 ST steps
(X) L, ST (x) H, macro code MAC (x), MAC
(X + 1) is stored in memory
Write to 1. In writing data to memory 1
Is connected to the input data bus iDB0-3 in the above operation.
Number of expansion steps ST (x) L, ST (x) H, macro code
MAC (x) and MAC (x + 1) are sequentially output. And
Data written to memory 1 as well as writing to memory 2
Through the data selector 5 and the output data bus ODB0-3.
Number of read and written expansion steps ST (x) L, ST
(X) H, macro code MAC (x), MAC (x + 1) are all
Is correct, and if it is,
Set iSEL to H level and switch to internal control. In addition, DRVE
N is at least one cycle (T
w) Change to H level later. As a result, the LCS drive signals PT1, PT2, COM1, COM2 and
Timing signals DSEL, ▲ ▼, HTWSX operate normally
You. Next, one cycle (T_W5) and 6).
This will be described with reference to the timing chart in FIG. As shown in FIG. 4 (a), as shown in FIG.
32 blocks of DSTATUS, that is, 8 frames of DSTAT
US is stored. The DSTATUS for these 8 frames
The first half of the period (T_W/ 2) and the latter half (T_W/ 2), so one cycle
(T_W) Is 16 frames. FIG. 5 shows the period T_WLate
Timing from the latter half of the last frame (16th frame)
Fig. 6 shows one cycle (T_W) Timing
It is a chart. In the latter half of the 16th frame, the
When the count value STCNT becomes “1”, the down counter 10
T01 becomes H level and is applied to the AND gate 11. ST01
Means that while the count value STCNT is “1” and “0”, the H level
Will be maintained. At this time, the Q output of the flip-flop 14 (SE
LMAC) is at the H level and the clock signal φ₁Butge
After passing through the port 11, it becomes a pulse signal iBLCLK and the data
Input to the lector unit 6. When iBLCLK is input to the data selector section 6, FIG.
As shown in FIG.
Four clock pulses are generated on BLCLK input to terminal CK
Then, every time the BLCLK rises from the up counter 3, BLADR
= 0, 1, 2, 3 are output to the memory 3. Also at this time ISEL
Is the H level, the NAND gate 6c of the data selector 6
From the clock signal φ while iBLCLK is at the H level.₀Is Nando
Input to terminal G of decoder 9 via gates 6c and 21
Is a clock signal φ.₀Is active during H level
Becomes BLADR (= 0) is output to memory 1 from up counter 3.
When input, the memory 1 outputs ST (0) L. this
When the clock signal φ₀Pulse from decoder 9 in synchronization with
The signal STLL is output to the latch 4-3. Latch 4-3
Is the ST output from the memory 1 when the STLL rises.
(0) L is input, and ST (0) L is input to the end of the down counter 10.
Output to children a to d. Next, the BLAD
When R (= 1) is output to the memory 1, the memory
ST (0) H output from 1 is output from the decoder 9
Latch 4-4
And ST (0) H is down-counted from latch 4-4.
The data is output to terminals e to h of the data 10. Hereafter, similarly, the up-counting is performed by the rising edge of BLCLK.
BLADR (= 3) and BLADR (= 4) are output from memory 3 to memory 1.
To the pulse signals MACLL and MACHL output from the decoder 9
MAC (0) and MAC (1) output from memory 1
And latched by the latches 4-1 and 4-2. Latch 4-
1, 4-2 are the data of MAC (0) and MAC (1), respectively.
Selector 13 terminal A₀~ A_Three, B₀~ B_ThreeOutput to In the timing chart of FIG. 5, LSTD is latch 4
-3 and 4-4 output to the down counter 10.
LMAC outputs the number of maps to latches 4-1 and 4-2.
It shows a black code. In the figure, ST (0) is
It shows 8-bit data of [ST (0) L, ST (0) H].
You. The count value ST of the down counter 10 (CNT becomes “0”
Then, carry signal STCY goes to H level and counts down.
The data 10 receives the LSTD {in this case, ST (0)}. The H level carry signal STCY is
10 to inverter 21, NAND gate 7, flip-flop
To the terminal K of the tap 12. Therefore, the inverter 21
(L level) is applied to the terminal E of the flip-flop 14.
The flip-flop 14 is enabled and the clock
Rising of clock signal ▲ ▼ (clock signal φ₂Standing
Q output of flip-flop 14 due to falling) (SELMAC)
Is inverted from H level to L level. SELMAC is L level
, The output of the latch 4-1 is output by the data selector 13.
(MAC (0)) is selected and the terminal A of the data selector 13₀~ A
_ThreeClock signal φ₃Enter with Also,
The output (L level) of port 7 is the terminal of flip-flop 17
In addition to E, the Q output (DSELQ) of flip-flop 17
From H level by rising of clock signal ▲ ▼
Invert to L level. Therefore, the data selector 16
Data output terminal RD of memory 2_Two, RD_ThreeAnd terminal D of latch 18
_Three, D_FourIs connected. Further, the data output terminal RD of the memory 2
₀, RD₁And terminal D of latch 18₁, D_TwoConnection with external select
Selection of the data selector 15 based on the
Will be determined, but it is assumed that PTSEL is
Will be explained. When PTSEL is L level, data in memory 2
Output terminal RD₀, RD₁Are respectively set by the data selector 15.
Switch 18 terminal D₁, D_TwoConnected to. Next, the down counter 10 starts the clock signal ▲ ▼.
At this time (STCY is H level), ST (0) is
Set the count value as STCNT, and then
Countdown is performed in synchronization with the rising edge of ▼. Da
Counter 10 counts down from ST (0) to 0
｛Tφ₂× (ST (0) +1)｝, data selector
13, the macro code MAC (0) and the clock signal φ₃
MAC address specified by the 5-bit address signal DADR
Data DDATA is read from memory 2 and data select
Terminal D of latch 18 via₁~ D_FourTo enter. Black
Signal φ₃Is the address signal input terminal A of the memory 2.₀~ A_Four
Most significant bit A of_FourInput from the memory 2
Signal DADR is the clock signal φ₃Is “0” (L level),
DADR every time it changes to “1” (H level)₀, DADR₀Strange with +16
(DADR₀Is the clock signal φ₃Is “0”
The address signal DADR is shown in FIG._i, DADR_i+16
The two macro data specified by_i(I = 0,1,2,
...). Therefore, the high-frequency signal f_HLap of
Period Tf_HIs Tφ₃Is equal to Terminal D of latch 18₁~ D_FourMacro data DDATA to be input to
Is the output terminal Q of the latch 18.₁~ Q_FourLCS drive signal from
No. PT1, PT2, COM1, COM2 and output to the recording control unit 200
Is done. Here, the block address BLADR of the memory 1 is 0 to 31.
The number of development steps ST (x) L, ST shown in FIG.
(X) H, macro code MAC (x), MAC (x + 1)
FIG. 4 showing the addresses DADR = 0 to 31 of the memory 2
If the macro data DDATA shown in (d) is stored
In this case, the LCS drive signals COM1, COM2, PT1, PT2 as shown in FIG.
Is the data output terminal Q of the latch 18.₁~ Q_FourFrom the recording control unit 200
Output to The data stored in the addresses DADR0 to DADR31 shown in FIG.
Signal waveforms PT1, PT2, C generated by macro data DDATA
OM1 and COM2 are shown in FIG. In FIG. 7 (a), DADR₀And DADR₁Is the memory 2
Indicates the address DADR, and the DADR described in the same column₀And D
ADR₁Macro data stored at the address specified by
By expanding DDATA, the signal wave shown in FIG.
PT1, PT2, COM1, and COM2 are obtained. The vertical axis is the voltage value
And f_H, ＊ f_HIs the high-frequency signal (* f_HIs f_HPhase of
Signal with a difference of 180 °). Y₁, Y_TwoOutput is OFF-OFF drive
Segment electrode signal PT1, ON-ON drive segment electrode signal PT
2 and Y_Three, Y_FourOutput is common electrode signal COM1, COM
It corresponds to 2. Y is applied to the signal electrode of LCS described later.₁(PT
1), Y_Two(PT2) to Y_Three(COM1), Y_Four
(COM2) is added to the micro shutter of LCS when input.
FIG. 7 (b) shows a waveform of such a voltage. In the figure,

[0] indicates that there is no electric field. LCS open / close control uses the voltage waveform shown in FIG.
(Two-frequency drive). Next, the driving waveforms COM1, COM2, PT1, PT shown in FIG.
2 is to be generated, the drive shown in FIG.
In the dynamic waveform, the waveform of the section of Td and Te in Fig. 8 (a) is generated.
I can't. In this case, it is stored in the memory 2.
The contents of the macro data DDATA to be displayed are shown in FIG.
To change. Compare FIG. 4 (d) and FIG. 8 (b)
8 (b), FIG.
Macro data of address DADR = 8, 9, 24, 25 in (d)
Changed the contents of DDATA. Memory 2 address DADR =
Expand macro data DDATA stored in 0-31 to
In order to obtain the drive waveform shown in FIG.
Data to be stored in the block address BLADR = 0 to 31 DATATUS
8 (c). By the way, BLADR (= 3)
When output to memory 1, BLAD (3) goes high at this time.
And joins the NAND gate 7. Timing chart of Fig. 5
As shown in the chart, when both SELMAC and STCY are at H level
BLAD (3) goes to H level, so from NAND gate 7
The L level is applied to the terminal E of the flip-flop 17, and
Q output of flip-flop 17 (DSELQ) rises to ▲ ▼
Glue (φ₂The timing chart shown in Fig. 6
As shown in FIG. this
Therefore, the RD of the memory 2 is_Two, RD_Threeoutput
Is the terminal D of the latch 18, respectively._Three, D_FourInput. and
The output of gate 7 then becomes BLADR "3" and BLAD (3)
Will not go low unless it goes high again
And the Q output (DSELQ) of the flip-flop 17 is before the cycle.
Half (T_W/ 2) is maintained at the L level. Therefore,
RD of memory 2 in the first half of the period_Two, RD_ThreeOutput latched 18
D_Three, D_FourInput. Further, a countdown is performed, and the countdown of the down counter 10 is performed.
When the count value STCNT becomes “1” again, ST01 goes low.
To H level. However, at this time, SELMAC is L
Level, so the clock signal φ₁Through AND gate 11
No clock pulse is generated in iBLCLK. Follow
Therefore, the BLADR output from the up counter 3 remains “3”.
is there. Next, the count value STCNT of the down counter 10 is set to “0”.
The carry signal STCY goes to H level and
Data 21 and a flip-flop via an inverter 21.
14 is enabled and clock signal ▲ ▼ rises
Glue (φ₂Of the flip-flop 14)
The Q output (STEMAC) changes from L level to H level.
In the data selector 13, the SELMAC of the H level is added to the terminal S.
Then, the macro code MAC (1) output from the latch 4-2
To select terminal B of memory 1.₀~ B_ThreeOutput to On the other hand,
Down count by rising of clock signal ▲ ▼
The number of steps ST output by the latches 4-3 and 4-4 is stored in the data
(0) is set again, so in the second half of the first frame
Macro code in the same way as the first half of the first frame
Clock MAC (1) and clock signal φ₃Address signal consisting of
Macro data DD stored at the address specified by the signal DADR
Tφ by ATA₂× (ST (0) +1) period, signal waveform
Is generated through the latch 18 and the buffer unit 20.
Output to 200. Then, it is counted down by the down counter 10 again.
Is performed and ST01 is restarted when the count value STCNT is “1” or “0”.
And H level, same as the latter half of the 16th frame
Generates four consecutive pulses on BLCLK,
BLADR = 4 to 7 are output to memory 1 from up counter 3.
Is forced. Then, when STLL and STHL rise,
The number of taps ST (2) is latched by the latches 4-3 and 4-4,
Macro code MAC (2) is lagged by the rise of MACLL.
In macro 4-3, the macro code MAC is generated by the rise of MACHL.
(3) is latched by the latch 4-4. In addition,
When the count value of the counter 10 becomes “0”, the down counter 10
Or carry signal STCY (H level) is generated and clock signal
▲ ▼ rise (φ₂Falling)
The number of steps ST (2) output by the switches 4-3 and 4-4 is down.
Is set in the counter 10 and the clock signal
Q output of flip-flop 14 due to rising (SELMAC)
Changes from the H level to the L level, and the output of the latch 4-1 is output.
Macro data MAC (2) and clock signal φ₃Is 1 day
Data selector 13 and becomes the address signal DADR.
Input to memory 2. After that, in the same way as the first frame
Tφ in the first half of the second frame₂× (ST (2) +1)
Period macro data MAC (2) and clock signal φ₃To
Tφ in the second half of the second frame₂× (ST
In the period of (2) +1), the macro data MAC (3) and the macro data
Signal φ₃Based on the macro data DD from the memory 2
ATA is read and signal waveforms PT1, PT2, COM1, and COM2 are generated.
You. As described above, the data selector unit 6 outputs one frame.
Each time the operation is completed, four pulses of BLCLK are generated,
4 blocks from the up counter 3 in synchronization with LCLK
The memory address (BLADR) is output to the memory 1. Soshi
And the number of steps ST (x) L, ST read from the memory 1
(X) H is stored in the latches 4-3 and 4-4, respectively.
Data MAC (x) and (x + 1) are latches 4-1 and
4-2, latch signal ST output from decoder 9
Input and hold at the rising edge of LL, STHL, MACLL, MACHL
You. Note that x is an even number from 0 to n / 2-2, that is, in this embodiment,
Is n = 32, and x is an even number from 0 to 14. Memory 2
Dress signal input terminal A₀~ A_FourThe flip-flop 14
Macro control in the first half of the frame by controlling the output SELMAC
Data MAC (x) and clock signal φ₃But in the frame
In the latter half, the macro data MAC (x + 1) and the clock signal φ
₃Is input and the macro data MAC (x) is input in the first half of the frame.
And the clock signal φ₃Of the frame of the address specified by
In the latter half, the macro data MAC (x + 1) and the clock signal φ
₃Macro data DDATA at the address specified by
And the LCS drive signals PT1, PT2, COM1, COM2
Generated. The frame cycle is determined by the number of steps ST (x).
Stipulated, Tφ for both the first and second half of the frame₂× (ST
(X) +1). The data shown in FIG.
Data DSTATUS and macro data D shown in FIG.
LCS drive signal generated when DATA is stored in memory 2
No. COM1, COM2, PT1, PT2 period T_WThe first half of (T_W/ 2) waveform
An example is shown in FIG. In the figure, f_L, F_L1Is a low frequency signal
Number, f_H, * F_HIs a high frequency signal and * f_HIs f_HPhase of 18
This is a waveform shifted by 0 °. Memory 2 address signal DADR
Is the clock signal φ₃F_HFrequency
Tf_HIs the clock signal φ₃Period Tφ₃Is equal to Also,
As shown in FIG.₃Is φ₂Is twice as large as
Therefore, as shown in FIG._H= 2Tφ₂It is. Also, the period T_WThe first half of (T_W/ 2) is completed,
4 pulses of BLCLK are generated from the
The BLADR = 0, 1, 2, and 3 are output from the counter 3 to the memory 11. So
Then, when the BLADR becomes “3”, the BLA
D (3) goes to the H level and is free via the NAND gate 7.
Flip-flop because it is added to terminal E of flip-flop 17
17 Q output (DSELRQ) level changes (L level → H
Level), RD of memory 2 by data selector 18_Two, RD_Three
The output is D of latch 18 respectively._Four, D_ThreeSwitch to input. Week
Period T_WThe second half of (T_W/ 2) in the first half (T_W/ 2)
The macro data DDATA stored in memory 2 is the number of steps ST
(0) to ST (7),
RD_Two, RD_ThreeOutput is switched by data selector 16.
Therefore, the waveforms of COM1 and COM2
T_WThe first half of (T_W/ 2) and the latter half (T_W/ 2) is replaced. Then, the macro data DDATA stored in the memory 2 is used.
LCS drive signals PT1, PT2, COM1, and COM2 generated by
Signal φ₁Latch 18, buffer in synchronization with rising edge of
The data is output to the recording control unit 200 (described later) via the recording unit 20. On the other hand, as shown in the timing chart of FIG.
Period T_WThe second half of (T_W/ 2) of the last frame (16th frame)
In the latter half, the block address output from the up counter 3
Dress BLADR becomes the final address (“31”) and
When the count value STCNT output from the counter 10 becomes "4", BLA
D (31), ST4 becomes H level and the output of AND gate 8
(TSXQ) becomes H level and the terminal of flip-flop 12
Joining J, the rise of ▲ ▼ because STCY is L level
The Q output of the flip-flop 12 (▲ ▼)
The H level and the output are inverted to the L level. For this reason,
The output of gate 19 (▲ ▼) from L level
It changes to H level. TSXQ becomes L when STCNT becomes “3”.
Level, and the output of Q of the flip-flop 12 (▲
▼) is φ₁Latch at latch 18 at rising edge
And recording control as ▲ ▼ through the buffer unit 20
Output to the unit 200. At this time, ▲ ▼ is φ₁At the rise of
Latched by the latch 18,
▼ is output to an external device (not shown). Also,
The inverted signal LTWSX of ▲ ▼ is the video interface
The data is output to the buffer 40r of the base unit 40. Next, when the count value STCNT becomes “0”,
The carry signal STCY from the
TSXQ added to the terminal K of the flop 12 and to the terminal J
The clock signal φ₂Flicker at the rise of
The Q output of the flop 12 is inverted to the H level. others
Therefore, the output ▲ ▼ of the NAND gate 19 becomes L level again.
It becomes. The carry signal STCY is also applied to the AND gate 7,
L level from AND gate 7 to terminal E of flip-flop 17
Since a bell is added, φ₂Flip-flop at the rise of
Q output (DSELQ) of step 17 is inverted from H level to L level
I do. DSELQ is φ₁Latch at latch 18 at rising edge
Is sent to the recording control unit 200 as DSEL via the buffer unit 20.
Is output. On the other hand, the video interface unit 40
While ▼ is at the L level, the clock signal ▲ ▼
One line from an external device (not shown) in synchronization with the fall
Input video data HLTTD for the latch 40b.
Recorded as video data LTXD via data buffer 40d and buffer 40e
Output to control unit 200. Also, from the clock signal HLTXCK
Flip-flops 40f, 40h, 40k, inverters 40g,
Two clock signals by the gates 40i and 40j
Generate ▼, ▲ ▼, buffer 40l, 40m respectively
To the recording control unit 200 via the. Clock signal ▲
▼ and ▲ ▼ are alternately two clocks as described above.
Each pulse occurs. As described in detail below, the recording control unit 200
Period T_W1 line from the video interface 40 during
Video data LTXD from the clock signals ▲ ▼, ▲
Receive in sync with ▼. And the video data LT
Based on the value of XD, the LCS drive input from the LCS drive signal generation circuit
Select the motion signals PT1 and PT2 and apply to the LCS signal electrodes
Control the opening and closing of each micro shutter in the LCS
Is included. At this time, the LCS drive signals COM1, COM
2 is applied to the common electrode of the LCS. I will explain in detail later
However, when PTSEL is L, the LCS drive signal PT1 is
LCS off drive signal to close micro shutter, LCS drive signal
No.PT2 is LCS on drive to open each micro shutter of LCS
LCS drive signals COM1 and COM2 have a period T
_WThe first half of (T_W/ 2), latter half (T_W/ 2) with signal to select LCS
is there. LCS is closed for the method of image formation by optical writing.
Normal light that records the area where light irradiation was not performed as black
The image method and the area where light irradiation was performed when the LCS was open were set as black
There is a reversal development method for recording, but in this embodiment, an external CPU
(Not shown), etc. in the case of the regular development system, PTSE
L is set to L level, and PTSEL = H level
In any of the above developing methods,
Also, if the bit of video data LTXD is “1”, a black dot
It is possible to unify to record Hereinafter, the LCS drive signal generation circuit of the present embodiment described above is applied.
The recording device 100 used will be described. FIG. 10 is a schematic configuration diagram of the recording apparatus 100, and FIG.
Therefore, the configuration of the recording device 100 will be described. In FIG. 1, the photosensitive drum 101 is made of metal such as aluminum.
A photoconductive photoreceptor can be applied to the outer peripheral surface of
Or, it is composed by vapor deposition.
It rotates in the marking direction B. Near the peripheral surface of the photosensitive drum 101
Charging device 102, optical recording head 103, developing device 104, transfer device 105,
A cleaner 106 and the like are provided. The charger 102 is mounted on the surface of the rotating photosensitive drum 101.
The surface of the photosensitive drum 101 is subjected to a predetermined potential
The optical recording head 103 is charged to a predetermined potential.
For images to be recorded on the surface of the charged photosensitive drum 101
Irradiates light to form an electrostatic latent image (optical recording head
The details of the node 103 will be described later). The electrostatic latent image formed on the surface of the photosensitive drum 101 is a toner image.
The toner image is developed by the developing device 104 containing
You. This toner image is combined with the toner image by transport means (not shown).
The transfer paper 107 overlaps with the transfer paper 107 conveyed in synchronization and
Is transferred onto the transfer paper 107 by the corona discharge. The toner image transferred onto the transfer paper 107 is fixed (not shown).
The fixing device fixes the toner image on the transfer paper and the toner image.
The paper 107 is discharged outside the machine. Also, transfer paper 1
07, the toner remaining on the surface of the photosensitive drum 101 without being transferred
The cleaner is removed from the surface of the photosensitive drum 101 by the cleaner 106.
Left. Next, FIG. 11 is a sectional view of the optical recording head 103.
You. Hereinafter, the configuration of the optical recording head 103 will be described with reference to FIG.
Will be described. A liquid crystal optical shutter 111 is provided in the optical recording head 103.
ing. FIG. 12 is a perspective view showing the configuration of the liquid crystal optical shutter 111.
FIG. As shown in FIG.
A liquid crystal agent (not shown) is interposed between the glass substrate 131 and the upper glass substrate 132.
) Is enclosed. Above lower glass substrate 131
The signal electrode 133 is formed on the surface, and the lower surface of the upper glass substrate 132
Has a common electrode extending in a direction substantially orthogonal to the signal electrode 133.
(Not shown) are formed and shared with the signal electrode 133.
A micro shutter 134 is formed at the intersection of the through electrodes.
You. Each micro-shutter 134 applies a predetermined drive signal to the common electrode.
Signal, and open the micro shutter 134 for each signal electrode 133.
By supplying an open / close drive signal for closing,
It is opened and closed separately. Next, returning to FIG. 11, the explanation will be continued.
A fluorescent lamp 112, which is a light source for irradiating light to the
Lamp case 113
In this space, air flows to cool the fluorescent lamp 112
It is configured as follows. The liquid crystal optical shutter 111 is accurately positioned
The positioning reference part of the head base 114 to be positioned
The imaging lens array 115 is also
Head base 114 to determine the positional relationship with the
Fixed in place. A drive circuit board 116 is provided on both sides of the lamp case 113.
The drive circuit is mounted on the drive circuit board 116.
The LCS drive LSI 117 which is SI is installed. Also drive times
The lower end of the surface of the circuit board 116 facing the lamp case 113
Conductive pattern drawn from the above LCS drive LSI 117
(Shown) is equal to the pitch of the signal electrodes 133.
It is formed of j. The conductive pattern of the drive circuit board 116 and the liquid crystal light shutter
Pitch with the signal electrode 133 of the
A flexible connector having a connection pattern formed of
They are connected by a film electrode connector 118. A common electrode drive signal is supplied above the lamp case 113
A drive circuit board 119 is provided for
On the circuit board 119, a logic level signal waveform is actually
To convert to a signal waveform of more than 20 volts applied to
Driver 120 is mounted and shared with the drive circuit board 119
The electrodes are connected by a connector (not shown). FIG. 13 is a partially enlarged view of the liquid crystal optical shutter 111.
Further, the liquid crystal optical shutter 11 along the line AA 'in FIG.
FIG. 14 is a sectional view of FIG. The signal electrode 133 is made of a transparent conductive material such as tin oxide or indium oxide.
It is composed of an electrical part 133a and a metal electrode 133b of chrome, gold or the like,
Similarly, the common electrode 135 has a transparent conductive portion 135a and a metal electrode 135b.
It is composed of The transparent conductive portions 133b and 135b face each other.
Micro-shutters 134 are formed in the
The micro-shutter 134 is opened and closed by the applied signal.
It is. Since each signal electrode 133 faces two common electrodes 135,
Two micro shutters 134 are formed on each signal electrode 133
Is done. This opens and closes each micro shutter 134
In order to reduce the number of drivers for
Because there is. Also, the micro shutter 135 does not open and close extremely fast.
Therefore, as the liquid crystal agent 136 shown in FIG. 14,
Liquid whose dielectric anisotropy is inverted according to the frequency of the applied electric field
Crystals (The frequency at which the dielectric anisotropy is zero is called the crossover frequency
And the crossing frequency and f_cAbbreviation) and dichroic dyes
Compound, and the driving method is f_cHigher frequency signal
Issue (hereinafter f_HAbbreviated as) and f_cLower frequency signal
(Hereinafter f_LAbbreviated)) or f_HAnd f_LSignal combined with
A so-called dual frequency drive for driving the liquid crystal using
You. Next, FIG. 15 (a) shows the opening / closing control of the liquid crystal optical shutter 111.
The circuit configuration of the recording control unit 200 that performs optical writing by
FIG. In the figure, reference numerals 134-1 and 134-2 denote the microchassis.
135-1, 135-2 identical to the shutter 134
Is the same common electrode as the common electrode 135. As illustrated in FIG.
LCS drive signals PT1, PT2, timing signal DSEL, ▲
▼ is input to the LCS drive LSI 217 via the control bus CB. The LCS drive signals COM1 and COM2 are
Input terminal I of high voltage driver 220 shown in (b)
_Ten, I₁₁And the high voltage driver 220
Micro-shutter 135-shifted to a few volts
1, 135-2. Generates two pulses alternately
Clock signals ▲ ▼ and ▲ ▼
Output to the upper and lower LCS drive LSIs 217. Therefore, before
The video data transferred from the video interface unit 40
Data LTXD (from the first 1-bit data, starting with number 1)
Serial number).
{1,2}, {5,6}, {9,10}, ... bit data
｛3,4｝, ｛7,8｝, ｛11,1
2｝ ... th bit data is transferred to the lower LCS drive LSI 217
input. Next, FIG. 16A shows a circuit configuration of the LCS driving LSI 217.
It is a block diagram showing composition. The shift register 301 receives the clock signal ▲
One line in synchronization with the rise of ▼ (▲ ▼)
Input video data LTXD. Shift register 301
Final output (Q₁Output) is cascaded through buffer 302
Input to the next connected LCS drive LSI 217 (not shown).
You. The latch 303 is activated by the falling edge of the clock signal CK2.
One line of video data LTXD from shift register 301
And input the even-bit data (D_Two, D_Four, ... D₁₅₈, D
₁₆₀) To the data delay control unit 304,
(D₁, D_Three, ... D₁₅₇, D₁₅₉A) the terminal of the multiplexer 305
A₁~ A₈₀Output to Multiplexer 305, FIG.
As shown in (b), A signal is input to A input by select signal DSEL.
Or B input, and select A input or B input
Select LCS drive signal PT1 or PT2 according to force value
Then terminal W₁~ W₈₀Output to higher voltage driver 306
I do. The high voltage driver 306 is used for input LCS drive
Level shift of signal PT1 or PT2 and Y₁~ Y₈₀Output
It is applied to the signal electrode 133 of the liquid crystal optical shutter 111. Next, the operation of the recording control unit 200 configured as described above
Will be described with reference to the timing chart of FIG.
You. The video interface unit 40 includes a ▲ shown in FIG.
While ▼ is at L level, video data is
Output LTXD. The LCS drive LSI 217 is
Clock signal output from the face unit ▲
Video data synchronized with falling of ▼, ▲ ▼
LTXD is input to the shift register 301. Video interface
Transfer of one line of video data LTXD from the face unit 40
Is completed, a pulse changes to ▲ ▼ as shown in FIG.
Is generated, and one line of video is generated at the falling edge of the pulse.
Data LTXD is transferred from shift register 301 to latch 303
The shift register 301 stores new video data LTXD.
Input is possible. Thus, one cycle T_WOne line of video data between
LTXD is input to the shift register 301 of the LCS drive LSI 217.
You. Also, the odd bits of the video data LTXD received last time
Multiplies from latch 303 at the rise of ▲ ▼
Lexa 305 terminal A₁~ A₈₀To enter. Video Day
The even bit of LTXD is the same
Then, it is input to the data delay control unit 304. Data delay control
In the section 304, the flip-flop 304a
Video data LTXD
Is 2 cycles T for odd bits_WMinutes late multiplexer
Enter in 305. This is a zigzag array of micro shutters
And set the staggered pitch in the sub-scanning direction to 2.5 lines.
Because there is. In addition, as shown in FIG._WL in the first half of
Since the bell is at the H level in the latter half, the multiplexer 305
Is the period T_WIn the first half of each of the odd bits of the video data LTXD
Select one of the LCS drive signals PT1 and PT2 according to the data.
Output to the high voltage driver 306,
Each micro shutter 234−
1, 234-2 is opened and closed to perform optical writing. To the common electrodes 135-1 and 135-2 of the liquid crystal optical shutter 111
Is the COM shown in the timing chart of Fig. 9.
1, COM2 is applied via high voltage driver 220
It is. When PTSEL is L, the LCS drive signal PT1 is LCS closed.
Signal, PT2 is an open signal of LCS, and the bit of video data LTXD is
When the trigger data is “1”, PT1 is applied to the signal electrode 233,
When the selected micro shutter 234-1 or 234-2 is closed
No optical writing is performed, and when “0”, PT2
Is applied and the selected micro shutter 234-1 or 2
34-2 is opened and optical writing is performed. Therefore,
In the case of the image method, the bit data of the video data LTXD is “1”
If, black dots are formed, and if "0", white dots are formed.
It is formed. Period T_WIn the latter half of the video
The same operation as the first half is performed by the even-bit data of data LTXD.
Optical writing is performed depending on the operation. As can be seen from the above description, in the present embodiment, the memory 1
Data select to stored macro code MAC (x)
Clock signal φ₃By adding
Generates an address signal DADR for memory 2 and outputs the address signal DADR.
Macro data DDATA specified by the dress signal DADR
2, a readout waveform is generated. Clock signal φ₃
Takes one of two values, “0” or “1”.
Macro data of 2 words by decoding the macro code MAC (x)
Data DDATA (4 × 2 bits) is read from memory 2
You. Therefore, decoding n macrocodes MAC (x)
The memory capacity M0 required to perform the operation is as follows: M0 = 4 bits × 2 words × n [bits] (1.1) The memory 2 is composed of n = 16 macros stored in the memory 1.
Since the code MAC (x) is decoded, the capacity M of the memory 2 is
2 is M2 = 4 × 2 × 16 = 128 [bits] (1.2) according to the equation (1.1).
When configured, about 800 gates for static RAM, pseudo
Static RAM can be configured with about 500 gates. By decoding one macro code MAC (x),
Lock signal φ₃2-word macro data DDAT in synchronization with
A is read and each bit of macro data DDATA is driven by LCS
The waveforms of the signals PT1, PT2, COM1, and COM2 are generated. At this time, 1
Takes two values, “0” or “1”, so two consecutive words
2 × 2 = 4 types depending on each bit of macro data DDATA
Kind of waveform is generated. That is, (“1”, “1”),
(“0”, “0”), (“1”, “0”), (“0”, “1”)
Kind. These waveforms are shown in FIG.
Element f_L, ＊ f_L, High frequency element f_H, ＊ f_HIs defined. Therefore, LC
Combination of S drive signals PT1, PT2, COM1, COM2 is 4 × 4 × 4 ×
4 = 256 ways, however, actually LCS micro
The voltage waveform applied to the shutter is PT1-COM1, PT1-COM
1.Because the voltage difference between PT2-COM1 and PT2-COM2,
256 ÷ as the type of voltage waveform applied to the black shutter
2 = 128 types are conceivable. But actually there are 10 ways
The combination is sufficient, and the capacity of the memory 2 may be M0 = 4 × 2 × 10 = 80 [bits] (1.3). The LCS drive waveform COM shown in FIGS. 8A and 9 described above.
1, COM2, PT1, PT2 are 6 waveform sets and 8 waveform sets respectively.
It is a combination. Fig. 8 because the capacity of memory 2 is 32 words
In order to obtain the LCS drive waveform shown in (a), the memories 1 and 2
The data shown in FIGS. 8 (c) and (b) are stored, respectively.
I have. As can be seen from FIG.
Has eight types of macro codes MAC (0) = "13", MAC
(1) = "15", MAC (2) = "12", MAC (3) = "1"
4 ", MAC (4) =" 9 ", MAC (5) =" 8 ", MAC (6) = M
AC (7) = "7", MAC (8) = MAC (9) = MAC (10) = M
AC (11) = MAC (12) = MAC (13) = MAC (14) = MAC (1
5) = "6" is stored. Eight combinations of waveforms
The capacity of the memory 2 of the minimum configuration for obtaining the data is 16 words (=
2 words × 8), but in this embodiment, the contents of the memories 1 and 2 are used.
Since the amount is 32 words, they are shown in Fig. 8 (c) and (b) respectively.
The data was stored as follows. The number of steps ST (X) L, ST (x) H,
Black code MAC (x), MAC (x + 1),
Chromadata DDATA are both external microprocessors.
Drive with an infinite number of combinations
Waveform can be obtained. Therefore, the liquid crystal in the recording device
Improve and change LCS liquid crystal materials used in headers quickly
Can be handled. In addition, the LCS panel is heated to around 40-60 ° C due to electro-optical characteristics.
It is desirable to use it while keeping it warm.
Power on when using LCS panel as optical shutter
Sometimes the light source is turned on to warm up and the light
To help heat the LCS panel with the radiant heat of the source
I have. At this time, the LCS is not
Marie-off type (Micro shutter is normally closed)
There is no problem if it is twisted, but the polarizing plate is arranged in crossed Nicols
Normally on, such as tonematic and birefringent
When the shape (usually the micro shutter is open)
Light passes through the LCS and irradiates the photoreceptor.
Will deteriorate. For this reason, the photoconductor is rotated
I try to prevent my body from deteriorating. In such a case,
Completely shutter each normally-on type LCS micro shutter
A special drive waveform that turns off (closes)
Application to the photoconductor drum to rotate the photoreceptor drum.
It is no longer necessary. In addition, the LCS micro shutter is opened by two-frequency drive.
When performing close control, the high-frequency signal f_HFrequency is a number + KHz ~
Due to the high frequency of several hundred KHz, the electrodes of the LCS panel
Heat is seen, but in anticipation of this, LCS panel
To prevent the temperature from rising above the appropriate temperature (40 ° C to 60 ° C).
Special drive for LCS micro shutter at warm-up
Add waveforms to ensure that the LCS panel is stable at the proper temperature.
Is desirable. In this way, normal use such as during warm-up
Special drive waveforms for LCS under different conditions
When applying to the micro shutter, the conventional waveform generator
Then it was necessary to increase the capacity of ROM2. However, in the present invention
Is the number of steps ST (x) H, MAC stored in the memory 1.
(X), MAC (x + 1) and the MAC stored in the memory 2
Warm-up because rewriting of data DDATA is possible
The contents of the macro data DDATA between time and use
Special drive without increasing memory capacity
Waveforms can be generated. In this embodiment, RAMs are used for the memories 1 and 2.
(Electrical Erasable Programable Read Only Memor
y) may be used. Also, when using EEPROM,
There is an advantage that the process of writing data to the memory becomes unnecessary. [Effect of the Invention] As described above, according to the present invention, a waveform is generated.
Since the decoder is composed of rewritable memory,
The following effects are obtained. a. Almost infinite combinations of waveforms can be obtained. b. Data in memory can be rewritten by external control
Liquid crystal material when used to generate LCS drive waveforms
Quickly respond to changes in drive waveforms due to improvements and changes in
Maintenance becomes easier. c. Recording device that performs optical writing with normally-on type LCS
When used to generate LCS drive waveforms for
To close the LCS micro shutter
B) By adding to the shutter,
The photoconductor is rotated when the light source assists the heating of the LCS panel.
There is no need to perform this, and control is simplified. Also, the photoconductor
Deterioration can also be prevented.

[Brief description of the drawings]

1 (a) to 1 (c) are block diagrams showing a circuit configuration of an embodiment of the present invention, FIGS. 2 (a) and 2 (b) are circuit configuration diagrams of a data selector 13, and FIG. FIG. 4A is a diagram showing a format of data stored in the memory 1 of the present embodiment, and FIG. 4B is a diagram showing a data configuration of one frame. FIG. 4 (c) is a diagram showing a specific example of data stored in the memory 1, FIG. 4 (d) is a diagram showing a specific example of data stored in the memory 2, FIG. FIG. 6 is a timing chart showing the operation of the present embodiment, and FIG. 7 (a) is a timing chart showing L generated by the macro data DDATA.
FIG. 7B is a diagram showing waveforms of the CS drive signals PT1, PT2, COM1, and COM2. FIG. 7B is a diagram showing voltage waveforms applied to the micro shutter of the LCS by the LCS drive signals COM1, COM2, PT1, and PT2. FIG. 8A is a diagram showing a specific example of an LCS drive waveform generated according to the present embodiment. FIGS. 8B and 8C are diagrams each showing a memory 2 for generating the LCS drive waveform. diagram showing the contents of data stored in the memory 2, FIG. 9 is a timing shutter illustrating the operation of one cycle T _W of the present embodiment, FIG. 10 is a schematic structural view of a recording apparatus 100, FIG. 11 12, a cross-sectional view of the optical recording head 103, FIG. 12 is a perspective view showing the configuration of the liquid crystal optical shutter 111, FIG. 13 is a partially enlarged view of the liquid crystal optical shutter 111, and FIG. FIG. 15 (a) is a block diagram showing a circuit configuration of the recording control unit 200, and FIG. 15 (b) is a high voltage driver 220. 16 (a) is a block diagram showing a circuit configuration of the LCS drive LSI 217, FIG. 16 (b) is a circuit configuration diagram of the multiplexer 305, and FIG. 17 is a conventional LCS drive signal generation FIG. 18 (a) is a block diagram showing a circuit configuration of the LCS drive signal generation circuit, and FIG. 18 (b) is a diagram showing DSTATUS contents stored in a ROM 402. It is. 1,2 ... Memory, 3 ... Up counter, 4-1,4-2, 4-3, 4-4, 18 ... Latch, 5,13,15,16 ... Data selector, 6 ... Data Selector section, 7,19 ... Nand gate, 9 ... Decoder, 10 ... Down counter, 12,14,17 ... Flip-flop, 21 ... Inverter, 8,11 ... And gate.

Continued on the front page (51) Int.Cl. ⁶ Identification number Reference number in the agency FI Technical display location H03K 5/156 H04N 5/66 102 H04N 5/66 102

Claims (3)

(57) [Claims] An address generating means, code data for specifying a waveform, and step data for specifying the number of development steps of the code data are stored as data of one frame, and data of a plurality of frames are stored. First storage means for outputting the data of the one frame in accordance with an address, and selecting one of an address generated from the code data and a fundamental frequency signal of a waveform to be generated or an address generated by the address generation means A rewritable second storage unit to which the output of the selection unit is input and outputs waveform data; and a frame of one frame based on the step data output from the first storage unit. Measuring means for measuring a period and instructing the address generating means to output data of the next one frame in accordance with the measured value. A waveform generating apparatus comprising: 2. The apparatus according to claim 1, wherein said second storage means is a RAM. 3. The waveform generator according to claim 1, wherein said second storage means is an EEPROM.