JP2637215B2 - Complex operational amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a pulse amplifier for amplifying an input pulse voltage with high speed and high accuracy, and particularly relates to a high-speed operational amplifier such as a drift amplifier and a thermal tail. The present invention relates to a composite operational amplifier circuit that corrects an input error voltage with a high-precision operational amplifier.

(Prior Art) A high-speed and high-precision pulse amplifier is used in various devices such as a beam deflection circuit in an electron beam exposure device, and its performance is desired to be improved. As a pulse amplifier of this type, a complex operational amplifier circuit has been conventionally known. Hereinafter, in describing the composite operational amplifier circuit, a general inverting amplifier will be described first with reference to FIG.

The inverting amplifier has a resistor R1 connected to the inverting input terminal of the operational amplifier 1.
The input voltage e1 is input via the, the reference voltage (GND) is input to the non-inverting input terminal, and the output voltage e2 is
The signal is fed back to the inverting input terminal via 2.

Here, assuming that the amplification degree of the operational amplifier 1 is A and the inverting input terminal voltage is e3, the output voltage e2 can be expressed by e1 = −e3 · A (1). e3 is Therefore, if the total gain of the inverting amplifier is G = R2 / R1, then Becomes In general, since A≫G, the above equation (3) may be replaced with e2 = −G · e1 (4). However, in a high-precision amplifier, the term (G + 1) / A in equation (3) becomes a problem. For example, the amplification A of the operational amplifier required to obtain 1/2 LSB accuracy of an 18-bit DA converter with G = 10 is
It requires 135 dB or more, which cannot be realized with a high-speed operational amplifier alone.

The composite operational amplifier has been proposed to satisfy such a requirement, and is specifically configured as shown in FIG. The first operational amplifier 1 has a high speed but small DC amplification, and the second operational amplifier 2 has a low speed but large DC amplification. The inverting input terminal voltage e3 (error voltage) of the operational amplifier 1 is integrated and amplified by the integrator 3 composed of the operational amplifier 2, the resistor R3 and the capacitor C1, and is applied to the non-inverting input terminal of the operational amplifier 1 constituting the inverting amplifier 4. Input as reference voltage.

Here, assuming that the amplification degree of the operational amplifier 1 is A1 and the output voltage of the operational amplifier 2 is e5, the output e2 of the inverting amplifier 4 is e2 = − (e3−e5) · A1 (5) Amplification of the inverting amplifier 2 If the degree is A2, the output voltage e5 of the integrator 3 is e5 = −e3 · A2... (6). Equation (3) described above is The error voltage of the operational amplifier 1 can be reduced by 1 / (A2 + 1).

However, the conventional composite operational amplifier circuit configured as described above has the following problems. That is, as shown in FIG. 14, when the input pulse signal (e1) is input, the edge of the output voltage e2 becomes dull due to the delay of the inverting amplifier 4, and as a result, a differential waveform is generated at the inverting input terminal voltage e3. Resulting in. This differentiated waveform is integrated by the integrator 3, causing a change in the reference voltage e5 of the inverting amplifier 4 as shown in the figure, and there is a problem that an output error is increased.

(Problems to be Solved by the Invention) As described above, in the conventional high-speed and high-accuracy composite operational amplifier circuit, the influence of the transitional state at the time of rising and falling of the input pulse signal causes the influence of the first operational amplifier. There has been a problem that the reference voltage applied to the non-inverting input fluctuates, resulting in an output error.

The present invention has been made in view of the above problems, and suppresses a non-inverting input voltage of an operational amplifier constituting an inverting amplifier from fluctuating in a transient state of an input pulse signal,
An object of the present invention is to provide a composite operational amplifier circuit that can effectively prevent the occurrence of output errors.

[Structure of the Invention] (Means for Solving the Problems) A first invention is an inverting amplifier configured to invert and amplify an input pulse signal, comprising a first operational amplifier capable of operating at high speed,
A sample-and-hold circuit for inputting an error voltage appearing at an inverting input terminal of the first operational amplifier, transmitting the input error voltage in a sample state, and holding and outputting the error voltage in the sample state in a hold state Control means for controlling the sample and hold circuit to be in a hold state at least during a period when the inverting amplifier is in a transient state, and to control the sample and hold circuit to be in a sample state during other periods; And an integrator configured to integrate and amplify the output of the sample and hold circuit and output the output as a reference voltage to a non-inverting input terminal of the first operational amplifier. I do.

A second invention includes an inverting amplifier configured to invert and amplify an input pulse signal, the inverting amplifier including a first operational amplifier operable at high speed,
A delay circuit for delaying the input pulse signal for a predetermined time;
A voltage dividing circuit connected between the output terminal of the delay circuit and the output terminal of the inverting amplifier; and a voltage follower circuit for converting the divided output of the voltage dividing circuit into a low impedance output and providing the output as an input of the integrator. An integrator comprising a second operational amplifier having a high amplification degree, integrating and amplifying an output voltage of the voltage follower circuit, and outputting the output as a reference voltage to a non-inverting input terminal of the first operational amplifier; It is characterized by having.

According to a third aspect of the present invention, there is provided an inverting amplifier comprising a first operational amplifier operable at high speed and inverting and amplifying an input pulse signal;
An error voltage appearing at the inverting input terminal of the first operational amplifier, which is composed of a second operational amplifier having a high amplification degree, is integrated and amplified, and the output is used as a reference voltage at the non-inverting input terminal of the first operational amplifier. In a composite operational amplifier having an integrator for outputting, a feedback capacitor is connected between an inverting input terminal and an output terminal of the first operational amplifier.

(Operation) According to the first aspect, while the error voltage appearing at the inverting input terminal of the first operational amplifier fluctuates due to the influence of the transient state at the time of rising and falling of the input pulse signal, the control means , The sample and hold circuit holds the error voltage in a steady state.
Since the held voltage is supplied to the integrator, a stable input is always supplied to the integrator, the reference voltage does not fluctuate, and the output error can be suppressed after all.

According to the second aspect of the invention, a waveform similar to the output of the inverting amplifier is obtained by delaying the input pulse signal for a predetermined time, and both are divided by the voltage dividing circuit, whereby a stable divided output is obtained. Since the divided output is converted into a low impedance output by a voltage follower circuit and input to the integrator, the S / N is improved and an extremely stable reference voltage can be obtained.

According to the third aspect, the change point of the input pulse signal, that is, the first point of change of the input pulse signal, is obtained by the action of the feedback capacitor connected between the inverting input terminal and the output terminal of the first operational amplifier constituting the inverting amplifier. During the transient state of the operational amplifier, a differential waveform and a pulse of the opposite polarity are generated as a pair at the inverting input terminal. The differential waveform can be absorbed by the pulse of the opposite polarity. Therefore, no error is accumulated in the integrator, and the reference voltage can be stabilized.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a composite operational amplifier circuit according to an embodiment of the first invention of the present invention.

The first operational amplifier 1 capable of high-speed operation inputs an input voltage e1 to its inverting input terminal (-) via a resistor R1, inputs a reference voltage to a non-inverting input terminal (+), and outputs an output voltage. e2 feeds back to the inverting input terminal via the feedback resistor R2 to form the inverting amplifier 4. The inverting input terminal of the operational amplifier 1 is connected to the input of the integrator 3 via the sample and hold circuit 11.

The integrator 3 has a low speed but a large DC amplification degree.
The non-inverting input terminal of the operational amplifier 2 is connected to the output of the sample and hold circuit 11 via the resistor R3, the non-inverting input terminal is connected to the reference potential (GND), and the output terminal and the inverting input terminal It is configured by connecting a capacitor C1.

The sample-and-hold circuit 11 is connected between the inverting input terminal of the operational amplifier 1 and the input terminal of the integrator 3 in series, and has a gain of 1, and is interposed between the amplifiers 21 and 22. Analog switch 23 and analog switch
Capacitor C2 for holding the potential between 23 and amplifier 22
It is composed of The output of the amplifier 21 is input to the control circuit 12 for detecting a change point of the input pulse signal.

The control circuit 12 controls the output of the amplifier 21 to a predetermined reference level Vr.
Comparators 24 and 25 that detect whether ef1 and Vref2 are greater than or less than ef1, and detect a change point of the input pulse signal based on the outputs of these comparators 24 and 25 and output a predetermined hold pulse HP And a sample-and-hold control circuit 26. The analog switch 23 of the sample and hold circuit 11 holds the error voltage e3 'by the hold pulse HP.

In the circuit of the present embodiment configured as described above, the Laplace-transformed transfer characteristic A (s) of the inverting amplifier 4 is now obtained.
But, Assuming that the non-inverting input terminal of the operational amplifier 1 is grounded, e2 = −e3 · A (s) (10) From the above equation (2), Is required. Generally, A1≫R2 / R1, so Can be expressed as

Here, assuming that T1 = (R2 + R1) T / (R1 A1), the step response of this equation is Becomes When this is inverse Laplace transformed, Becomes

Therefore, as shown in FIG. 2, when a signal such as e1 is input as an input pulse signal to the circuit of the present embodiment, the output signal e2 of the inverting amplifier 4 becomes as shown in FIG. As a result, a differential pulse indicated by e3 appears at the inverting input terminal of the operational amplifier 1. Conventionally, this differentiated pulse was input to the integrator 3 and caused an output error. In this circuit, in order to prevent this, first, the differentiated pulse is first supplied to the control circuit via the amplifier 21.
It is input to twelve comparators 24 and 25. The two reference levels Vref1, Vref2, Vref1>0> Vref2 are set. Therefore, an output pulse is first obtained from the comparator 24 by the first half differential pulse. In response to this, the sample-and-hold control circuit 26 adds an interval pulse IP having a constant width τ to the output pulse, and outputs a hold pulse HP that can sufficiently cover a transient period during which the differential waveform disappears. Similarly, an output pulse is obtained from the comparator 25 by the second derivative pulse, and in response to this, the sample hold control circuit 26 outputs a hold pulse HP obtained by adding an interval pulse IP having a constant width τ to the output pulse. The analog switch 23 is opened by these hold pulses HP, and the differential pulse is prevented from being input to the integrator 3. Also, since a constant error voltage e3 is held in the capacitor C2 except for the transient state, a stable integrator input signal e4 not affected by the differential pulse is obtained, and the reference voltage e5
Is suppressed.

FIG. 3 is an embodiment of another invention. This example is
This is an example in which a device having means for generating the input pulse signal e1 to the composite operational amplifier by digital-to-analog conversion of the digital signal DI suppresses the fluctuation of the error voltage of the first operational amplifier 1. The input data DI is latched by a first latch circuit 31, and is converted into an analog pulse signal by a D / A converter 32. The data latched by the first latch circuit 31 is subsequently latched by the second latch circuit 33. Each latch circuit 3
The outputs of 1, 33 are subtracted by a subtractor 34, where a change point of the input data is detected. The subtraction signal is given as an address of the ROM 35. The ROM 35 outputs the subtraction output of the subtractor 34, that is, pulse width data corresponding to the amplitude value of the input pulse signal to be generated from the digital signal DI, to the pulse generation circuit 36. The pulse generation circuit 36 outputs a pulse having a width corresponding to the given pulse width data to the analog switch 23 as a hold pulse HP.

FIG. 4 shows a timing chart of this circuit. Input data
DI is latched by the latch circuit 31 by the enable pulse EP. The output of the latch circuit 31 is an enable pulse.
It is latched by the latch circuit 33 by the EP. The pulse generation circuit 36 outputs a hold pulse HP based on the pulse width data output from the ROM 35 by catching the falling edge of the enable pulse EP. Thus, the input voltage e4 and the reference voltage e5 of the integrator 3 have constant values.

According to this configuration, the generation period of the differential waveform that changes according to the amplitude of the input pulse signal e1 is used as pulse width data in the ROM 35.
, The differential waveform in the transient period can be completely removed regardless of the amplitude of the input pulse signal e1.

FIG. 5 shows an embodiment of the second invention of the present invention. This circuit is different from the conventional circuit shown in Fig. 13 in that a delay circuit consisting of a resistor R5 and a capacitor C3 that delays the input pulse signal
14, a voltage dividing circuit 15 including a resistor R6 and a resistor R4 connected in series between an output terminal of the delay circuit 14 and an output terminal of the inverting amplifier 4, and a divided output of the voltage dividing circuit 15 having a low impedance. A voltage-follower-connected third operational amplifier 16 for converting the output into an output and input to the integrator 3 is newly added.

According to this configuration, as shown in FIG. 6, when the input pulse signal e1 is input, the delay output of the delay circuit 14 is obtained as shown by e6. The delay output e6 is substantially similar to the waveform of the output signal e2 of the inverting amplifier 4. So, for example,
By setting R5 + R6 = R1 and R4 = R2, a constant value is obtained as the divided output e4 of the voltage dividing circuit 15, and the reference voltage e5 output from the integrator 3 is also a voltage that does not fluctuate. According to this circuit, the signal source impedance to the integrator 3 is sufficiently reduced by the operational amplifier 16 connected between the output of the voltage divider 15 and the input of the integrator 3, so that the S / N is improved. Further, a highly accurate amplifier circuit can be configured.

If the open loop gain of the operational amplifier 2 constituting the integrator 3 is too large, oscillation may occur. For example, as shown in FIG.
Is divided by resistors R7 and R8 to attenuate the input level to the operational amplifier 1 to prevent oscillation.

FIG. 8 shows still another embodiment of the present invention. This embodiment is an example that suppresses fluctuations in the error voltage of the first operational amplifier 1 in a device having means for generating the input pulse signal e1 to the composite operational amplifier by digital-to-analog conversion of the digital signal DI. is there. In the circuit of FIG. 5, when determining the delay amount of the delay circuit 14, the integer is constant. However, in this circuit, the delay circuit 17 is composed of the resistor R5 and the varactor diode D, and the amplitude of the input pulse signal e1 is The time constant can be varied according to the time. Change point detection circuit 18 for detecting pulse amplitude
Are substantially the same as the change check output circuit 13 in FIG. 3, and therefore, the same parts are denoted by the same reference numerals. In this circuit, RO
M37 stores control voltage data of the varactor diode D that determines a time constant to be set according to the amplitude of the input pulse signal e1. And this data is D / A converter 38
Is converted into an analog control signal CS and applied to the anode of the varactor diode D.

FIG. 9 shows a timing chart of this circuit. When the amplitude of the input pulse signal e1 is small, it is indicated by a solid line, and when it is large, it is indicated by a two-dot chain line. According to the amplitude of the input pulse signal e1, D /
The level of the control signal CS from the A converter 38 changes, and the waveform of the delay output e6 of the delay circuit 17 changes. Thereby, it is possible to follow a change in the output signal e2.

FIG. 10 is a diagram showing an embodiment of the third invention of the present invention. This circuit differs from the conventional circuit of FIG. 13 in that a feedback capacitor C4 is connected in parallel with the feedback resistor R2 of the inverting amplifier 4.

According to this circuit, as shown in FIG. 11, the input signal e1
The output of the operational amplifier 1 is fed back to the inverting input terminal via the feedback capacitor C4 at the rise and fall of
The signal appearing on the inverting input terminal side is a bipolar pulse composed of a differential waveform generated by the delay of the inverting amplifier 4 and a pulse of the opposite polarity due to feedback. Therefore, the feedback capacitor
If C4 is set to an appropriate value, the occurrence of an error in the integrator 3 can be prevented as shown in FIG.

[Effects of the Invention] As described in detail above, according to the first invention, during the transient period of the inverting amplifier, the error voltage in the stationary period is held and given as the reference voltage of the inverting amplifier. And the delayed output of an input pulse signal similar thereto are divided, impedance-converted by a voltage follower, integrated, amplified, and given as a reference voltage of an inverting amplifier. Since a bipolar pulse is generated at the inverting input terminal by connecting a capacitor, the reference voltage of the inverting amplifier does not fluctuate due to changes in the input pulse signal, and the advantages of the composite operational amplifier circuit are utilized. A high-speed and high-accuracy amplifier circuit can be provided.

[Brief description of the drawings]

1 is a circuit diagram of a composite operational amplifier according to a first embodiment of the present invention, FIG. 2 is a waveform diagram of the circuit, and FIG. 3 is a circuit diagram of a composite operational amplifier according to another embodiment of the present invention. 4 is a waveform diagram of the circuit, FIG. 5 is a circuit diagram of a composite operational amplifier according to an embodiment of the second invention, FIG. 6 is a waveform diagram of the circuit, and FIG. 7 is a circuit diagram of FIG. FIG. 8 is a circuit diagram of a composite operational amplifier according to still another embodiment of the present invention, and FIG.
Fig. 10 is a waveform diagram of the circuit, Fig. 10 is a circuit diagram of the composite operational amplifier according to the third embodiment of the invention, Fig. 11 is a waveform diagram of the circuit,
FIG. 12 is a circuit diagram showing a general inverting amplifier, FIG. 13 is a circuit diagram of a conventional composite operational amplifier, and FIG. 14 is a waveform diagram of the circuit. 1... First operational amplifier, 2... Second operational amplifier, 3
…… integrator, 4 …… inverting amplifier, 11 …… sample and hold circuit, 12 …… control circuit, 13,18 …… change point detection circuit, 14 …… delay circuit, 15 …… voltage divider circuit, 16… ... Third operational amplifier, 17... Variable delay circuit.

Claims (3)

(57) [Claims] 1. An inverting amplifier comprising a first operational amplifier operable at high speed for inverting and amplifying an input pulse signal, and an error voltage appearing at an inverting input terminal of the first operational amplifier is inputted. A sample-and-hold circuit that transmits the error voltage thus obtained and holds and outputs the error voltage in the sample state in a hold state; and sets the sample-and-hold circuit in a hold state at least during a period when the inverting amplifier is in a transient state. And control means for controlling the sample-and-hold circuit to be in a sample state during other periods, and a second operational amplifier having a high amplification degree, integrating and amplifying the output of the sample-and-hold circuit, and outputting the result. And an integrator for outputting a reference voltage to a non-inverting input terminal of the first operational amplifier. Composite operational amplifier characterized. 2. An inverting amplifier comprising a first operational amplifier operable at high speed for inverting and amplifying an input pulse signal, a delay circuit for delaying the input pulse signal for a predetermined time, an output terminal of the delay circuit and the inverting circuit. A voltage divider circuit connected between the output terminal of the amplifier, a voltage follower circuit that converts the divided voltage output of the voltage divider circuit into a low impedance output and provides the input as an input to the integrator, An integrator comprising an operational amplifier, integrating and amplifying the output voltage of the voltage follower circuit, and outputting the output as a reference voltage to a non-inverting input terminal of the first operational amplifier. Operational amplifier. 3. An inverting amplifier comprising a first operational amplifier operable at high speed and inverting and amplifying an input pulse signal, and an inverting input terminal of said first operational amplifier comprising a second operational amplifier having a high amplification degree. And an integrator for integrating and amplifying the error voltage appearing in the first operational amplifier and outputting the output as a reference voltage to a non-inverting input terminal of the first operational amplifier. A composite operational amplifier comprising a feedback capacitor connected between a terminal and an output terminal.