JP2636709B2 - Logic optimizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic optimizing apparatus for optimizing a delay time and an area by replacing elements in a logic circuit according to rules in an optimization rule base.

[0002]

2. Description of the Related Art Conventionally, a logic optimization device that inputs connection information of a logic circuit to be optimized and sequentially applies the information to rules stored in an optimization rule base to optimize delay time and area has been known. Proposed.

FIGS. 12 to 15 are diagrams showing the state of optimization performed by the logic optimizing device. FIG.
In FIG. 15, IN1 to IN4 are input terminals, OUT
1, OUT2 is an output terminal, INV1 to INV4 are inverters, AND1, AND2 are AND circuits, NAND1,
NAND2 is a NAND circuit, NOR1 is a NOR circuit, OR1
Indicates an OR circuit.

FIG. 12 is a circuit diagram of a logic circuit indicated by the connection information input to the logic optimization device. This logic circuit is applied to the logic rules shown in FIGS. Sequentially changes to the logic circuit shown in FIG.

FIG. 13 shows a logic circuit after applying a rule for replacing a NAND circuit whose output is connected to an inverter with an AND circuit to the logic circuit of FIG. 12, and shows a NAND circuit NAD1 and an inverter in FIG. INV4 is replaced by an AND circuit AND2 in FIG.

FIG. 14 shows a logic circuit after applying a rule for replacing the AND circuit in which inverters are connected to both inputs to the NOR circuit with a NOR circuit to the logic circuit of FIG. The INV2 and the AND circuit AND1 are replaced with a NOR circuit NOR1 in FIG.

FIG. 15 shows a logic circuit after applying a rule for replacing the NOR circuit whose output is connected with an inverter with an OR circuit to the logic circuit of FIG.
The NOR circuit NOR1 and the inverter INV3 in the middle are replaced with an OR circuit OR1.

By performing such optimization, it is possible to reduce the number of elements, shorten the delay time, and reduce the area.

FIG. 16 is a block diagram showing an example of the configuration of a conventional logic optimizing device.
, A logic optimization unit 162, an output unit 163 that outputs the result of optimization to a file or the like, and a storage unit 164 including a connection information storage unit 165 and an optimization rule base 166.

[0010] When optimizing, the user first stores the connection information of the logic circuit to be optimized in the connection information storage unit 165 using the input unit 161, and then activates the logic optimizing means 162.

When the logic optimizing means 162 is started, as shown in the flow chart of FIG. 17, first, it focuses on the first output terminal in the logic circuit indicated by the connection information (steps S171 and S172).

Next, the logic optimizing means 162
As shown in (1), attention is paid to the first rule in the optimization rule base 166 in which a plurality of rules are stored (steps S174 and S175).

Thereafter, the logic optimizing means 162 performs a path trace from the first output terminal to the input terminal (step S178), and determines whether or not there is a portion to which the first rule can be applied. Yes (Step S17
9).

If it is determined that there is no applicable part, attention is paid to the second rule (step S182,
S175), the same processing as described above is performed.

If it is determined that there is an applicable portion, the element is replaced according to the first rule (step S180), and whether or not the replaced path satisfies the target such as the target delay value is determined. Is determined (step S181).

If it is determined that the target has been cleared, attention is paid to the second output terminal (step S17).
7, S172), the same processing as described above is performed.

If it is determined that the target has not been cleared, attention is paid to the second rule (step S18).
2, S175), the same processing as described above is performed.

When the above-described processing is performed for all the rules (YES in step S176), the logic optimizing unit 162 pays attention to the second output terminal (steps S177 and S172). The same processing is performed.

Hereinafter, the logic optimizing means 162 performs the same processing as described above for the third, fourth,... Output terminals, and performs the above-described processing for all output terminals. (Step S173 is YES), and the process is ended.

[0020]

As described above, conventionally, the applicable rules among the rules stored in the optimization database are applied in the storing order until the target such as the delay target value is cleared. However, there are the following problems.

In other words, conventionally, the order of accumulation of rules in the optimization rule base is determined by the designer based on experience, so that the order of accumulation of frequently applied rules is later than the order of accumulation of rules of low application frequency. There is. In such a case, processing for a rule with a small number of applications that is likely to be determined to be inapplicable is performed before processing for a rule with a large number of applications that is likely to be determined to be applicable. Therefore, there is a problem that the number of rules that must be referenced before the optimization target is cleared increases, and the time required for optimization increases.

The rules include a rule effective for optimizing the delay time, a rule effective for optimizing the area, and a rule effective for optimizing both the delay time and the area. However, conventionally, since the logic circuit is optimized using an optimization rule base in which these rules are mixed, when optimizing a logic circuit with strict delay constraints, the area is optimized. May not be able to clear the delay constraint due to the application of the rules for the delay.

Therefore, it has been proposed that when optimizing a logic circuit with strict delay constraints, optimization is performed by applying only rules for optimizing the delay time.

However, in this method, since a rule for delay time optimization is selected for the entire logic circuit to be optimized, a path with less severe delay constraints may be included in a logic circuit with severe delay constraints. Even if it exists, the rule for optimizing the delay is applied to the path and the rule for optimizing the area is not applied, so that the scale of the logic circuit increases. There's a problem.

An object of the present invention is to reduce the time required for the optimization processing of a logic circuit, and to provide a path that does not require a delay constraint even when optimizing a logic circuit with a strict delay constraint. An object of the present invention is to provide a logic optimizing device capable of reducing the circuit scale of an existing logic circuit.

[0026]

The present invention SUMMARY OF], in order to shorten the time required for the optimization process, the optimization rule base in which the rules are accumulated to perform a logical optimization, delay Yu
The previous rule base, and area priority rule base, the optimum
Out of the rules stored in the rule base
Mode rules are stored in the optimization rule base
In the delay priority rule base in the order
The rules of the previous mode are stored in the optimization rule base.
Rules stored in the area priority rule base in the order
Separation means and each output terminal of the logic circuit to be optimized
Is an output terminal that optimizes delay priority or an area priority
Output that indicates whether or not the output terminal performs optimization
Input terminal table and the delay priority rule base.
Rules are evaluated in the order in which they are stored, and targeted for optimization.
Of the paths in the logic circuit, the output terminal
Output terminal that stores information indicating that optimization is performed
Rules that are applicable for each path corresponding to a child
If the process is optimized by applying the rule,
Delay priority optimization until the delay clears the delay target value
Means, and optimization by the delay priority optimizing means is performed.
After that, the rules stored in the area priority rule base
Logic circuits that are evaluated based on their storage order
Of each path in the table, optimize the area prioritized in the output terminal table.
Corresponds to the output terminal that stores the information indicating that
Rules that can be applied to each path
The process of optimizing by applying
Area priority optimization means to continue until the product target value is cleared
And a rule sorting means for sorting the rules stored in the optimization rule base in the order of application times.

[0027]

[0028]

[0029]

First, the rule sorting means performs the optimization rule base.
The rules stored in the source are sorted in the order of application.
Next, the rule separation means accumulates in the optimization rule base
Out of the rules set in the delay priority mode
Priority rule in the order stored in the rule base
Accumulates in the base and optimizes area priority mode rules
Area priority rule base in the order stored in the rule base
To accumulate. After that, the delay priority optimizing means
The rules stored in the rule base are evaluated in the order of storage.
Of each path in the logic circuit to be optimized,
Information indicating that delay priority optimization is performed on the output terminal table
For each path corresponding to the output terminal where
Optimize by applying applicable rules if applicable
Processing, the path delay time clears the delay target value
Continue until. When optimization by the delay priority means ends,
Area priority optimization means are stored in the area priority rule base.
The rules that have been optimized are evaluated in the order
Of the paths in the logic circuit
Output terminal that stores information indicating that optimization is performed
If the rule is applicable to each path corresponding to the child
The process of optimizing by applying the rule is performed by the logic circuit.
Until the area of the area clears the area target value.

[0030]

[0031]

[0032]

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. An input unit 1 such as a keyboard, a control unit 2, and a storage unit 3
And an output unit 4 for outputting a result of the optimization to a file or the like.

The storage unit 3 includes a library 31, a target achievement table 32, a delay target storage unit 33, and an area target storage unit 34.
, Connection information storage unit 35, and optimization rule base 36
An output terminal table 37, a delay priority rule base 38,
The area priority rule base 39, the delay priority rule application count table 40, the area priority rule application count table 41, and the rule application count table 42 are included.

The optimization rule base 36 stores a plurality of rules for performing delay optimization and area optimization.

The rule application frequency table 42 stores the rule numbers and the application frequency of each rule stored in the optimization rule base 36 as shown in FIG.

The delay priority rule base 38 stores the rules in the delay priority mode among the rules stored in the optimization rule base 36.

The area priority rule base 39 stores the rules of the area priority mode among the rules stored in the optimization rule base 36.

The number-of-delay-priority-rules application table 40 stores the number of times each rule in the delay-priority rule base 38 has been applied from the start to the end of optimization processing for a certain logic circuit.

The area-priority rule application count table 41 stores the number of times each rule in the area-priority rule base 39 has been applied from the start to the end of optimization processing for a certain logic circuit.

The library 31 stores information (eg, delay time of each element, area of each element) and the like necessary for determining whether or not the delay constraint and the area constraint are cleared.

The delay target storage unit 33 stores a delay target value.

The area target storage section 34 stores an area target value.

In the goal achievement table 32, as shown in FIG.
Corresponding to the output terminal number of each output terminal in the logic circuit to be optimized, clear information indicating whether or not the path corresponding to the output terminal has cleared the delay constraint is stored.

In the output terminal table 37, as shown in FIG.
Stores the output terminal number of each output terminal in the logic circuit to be optimized, and information indicating whether the path corresponding to the output terminal performs delay priority or area priority optimization. Is done.

The control unit 2 comprises a rule separating means 21, a delay priority optimizing means 22, an area priority optimizing means 23, an application frequency updating means 24, and a rule sorting means 25.

The rule separating means 21 stores the rule in the delay priority mode among the rules stored in the optimization rule base 36 in the delay priority rule base 38, and stores the rule in the area priority mode in the area priority rule base 39. Has the function of storing.

The delay-priority optimizing means 22 provides a path delay to a path indicated by the output terminal table 37 to be subjected to delay-priority optimization among the paths in the logic circuit to be optimized. A function of performing an optimization by applying an applicable rule among the rules stored in the delay priority rule base until the time clears the delay target value stored in the delay target storage unit 33; When starting optimization for a logic circuit, a function of performing initialization processing on the goal achievement table 32 and the delay priority rule application count table 40, and a delay priority rule application count every time a rule in the delay priority rule base 38 is applied. And a function of updating the table 40.

The area priority optimizing means 23 applies a logic circuit to a path indicated by the output terminal table 37 to perform the area priority optimization among the paths in the logic circuit to be optimized. A function of performing optimization by applying an applicable rule among the rules stored in the area priority rule base 39 until the area clears the area target value stored in the area target storage unit 34; When the optimization process for a logic circuit is started, the area priority rule base 39
And a function of updating the area priority rule application count table 41 every time a rule in the area priority rule base 39 is applied.

When the optimization process for a certain logic circuit is completed, the application frequency updating means 24 uses the temporary application frequency stored in the delay priority rule application frequency table 40 and the area priority rule application frequency table 41. Rule application count table 4
2 has a function of updating.

The rule sorting means 25 has a function of sorting the rules stored in the optimization rule base 36 in the descending order of the number of applications based on the number of applications of each rule stored in the rule application table 42. Have.

FIG. 5 is a flowchart showing an example of processing by the rule separating means 21, FIGS. 6 and 7 are flowcharts showing an example of processing by the delay priority optimizing means 22, and FIGS.
3 is a flowchart showing a processing example of FIG. 3, and FIG.
4 is a flowchart showing a processing example of FIG. 4, and FIG.
5 is a flowchart showing a processing example of No. 5, and the operation of this embodiment will be described below with reference to the drawings.

When optimizing a logic circuit, the user uses the input unit 1 to store the connection information of the logic circuit in the connection information storage unit 35, and stores the target delay value in the delay target storage unit 3.
3, the area target value is stored in the area target storage unit 34, and whether the path corresponding to each output terminal of the logic circuit performs delay-first optimization or area-first optimization is performed. Is stored in the output terminal table 37.

Next, the user uses the input unit 1 to input information indicating rules used only for delay-first optimization and rules used only for area-first optimization to the rule separating means 21. And then the rule separating means 21
Start

When the rule separating means 21 is activated, as shown in FIG. 5, it is specified that the rule separating means 21 is to be used only for delay-priority optimization among the rules stored in the optimization rule base 36. The rules (delay-priority mode rules) that are not specified to be used only for the optimization with delay priority or the optimization only for area priority are stored in the optimization rule base 36. Are stored in the delay priority rule base 38 in the order described (step S1).

Next, the rule separating means 21 performs, out of the rules stored in the optimization rule base 36, the rule designated to be used only for the area priority optimization and the delay priority optimization. The rules (area-priority mode rules) which are not specified to be used only for area-priority optimization or area-priority optimization (area-priority mode rules) are stored in the optimization rule base 36 in the order stored in the optimization rule base 36. (Step S2).

Here, the rules in the optimization rule base 36 are sorted by the rule sorting means 25 in the order of the number of times of application, so that the delay priority rule base 38,
The rules in the area priority rule base 39 are also sorted in descending order of the number of applications.

When the processing of the rule separating means 21 is completed,
The delay priority optimizing means 22 includes a delay priority rule base 38.
Is set to "1" which indicates the rule number of the rule stored in "1" (FIG. 6, step S1).
1).

Next, the delay priority optimizing means 22 sets the application count of each rule stored in the delay priority rule application count table 40 to all “0” and sets the delay All the clear information indicating whether the target value has been cleared is set to “0” (indicating that the target value has not been cleared) (step S12).

Thereafter, the delay priority optimizing means 22 pays attention to the ith rule in the delay priority rule base 38 (step S13), and terminates the processing if the rule has been completed (step S14 is YES). I do.

If the rule has not been completed (NO in step S14), the delay priority optimizing unit 22 sets a variable j indicating the number of the output terminal of the logic circuit to be optimized to which attention is paid. Set to “1” (Step S1
5).

After that, the delay priority optimizing means 22
Attention is paid to the third output terminal (FIG. 7, step S16). If the output terminal is not terminated (step S17 is N
O), it is determined based on the contents of the output terminal table 37 whether or not the j-th output terminal corresponds to a path for performing delay-priority optimization (step S20).

When it is determined that the j-th output terminal does not correspond to the path for performing the delay priority optimization (NO in step S20), the variable j is incremented by 1 (step S2).
9) Attention is paid to the next output terminal (step S16).

When it is determined that the j-th output terminal corresponds to the path for performing the delay-first optimization.
(YES in step S20), it is determined with reference to the target achievement table 32 whether or not the path has already cleared the delay target value (step S21).

When it is determined that the game is cleared
If (step S21 is YES), the process of step S29 is performed, and if it is determined that clearing has not been performed (step S21 is NO), a path trace is performed from the jth output terminal to the input terminal (step S22). ), It is determined whether or not there is a part to which the i-th rule can be applied in the traced path (step S23).

If it is determined that there is no part to which the i-th rule can be applied (NO in step S23), the delay priority optimizing means 22 performs the processing of step S29, and determines that there is a part to which the i-th rule can be applied ( Step S23 is Y
ES) performs element replacement (conversion) according to the i-th rule (step S24).

When the processing in step S24 ends, the delay priority optimizing means 22 sets the delay priority rule application count table 40
Is updated (step S25). Here, if there are k portions to which the i-th rule can be applied to the path, the delay priority optimizing unit 22 sets the delay priority rule application count table 40
Is incremented by + k.

Thereafter, the delay priority optimizing means 22 estimates the delay time of each path from the j-th output terminal to the input terminal based on the delay time of each element stored in the library 31 ( Step S26), it is determined whether or not all of them have cleared the delay target value stored in the delay target storage unit 33 (Step S27).

If it is determined in step S27 that there is a path that has not cleared the delay target value (the determination result is N
O), the delay priority optimizing unit 22 performs the processing of step S29, and when it is determined that all the paths have cleared the delay target value (the determination result is YES), the jth of the target achievement table 32 After setting the clear information corresponding to the output terminal to "1" (indicating that the delay target value has been cleared)
(Step S28) Attention is paid to the next output terminal (Steps S29 and S16).

Thereafter, the same processing as described above is performed for all output terminals, and when the above-described processing is performed for all output terminals (YES in step S17), the delay priority optimizing means 22 sets the target With reference to the achievement table 32, it is determined whether or not the paths corresponding to all the output terminals have achieved the delay target value (step S18).

If it is determined that the paths corresponding to all the output terminals have achieved the delay target value (step S
18 is YES), the delay priority optimizing means 22 terminates the processing, and determines that the processing has not been achieved (NO in step S18), and determines the next rule stored in the delay priority rule base 38. Attention is paid (step S19 in FIG. 7, step S13 in FIG. 6), and the same processing as described above is performed.

When the processing of the delay priority optimizing means 22 is completed, the area priority optimizing means 23 sets the variable m indicating which rule of the rules stored in the area priority rule base 39 to pay attention to “1”. (FIG. 8, step S3
1) Then, the number of times of application of each rule stored in the area priority rule application frequency table 41 is set to "0" (step S32).

Next, the area priority optimizing means 23 pays attention to the m-th rule among the rules stored in the area priority rule base 39 (step S33), and when the rule has been completed (step S34). Is YES), the process is terminated, and when the rule is not terminated (step S
34 is NO), the variable n indicating the number of the output terminal of the logic circuit targeted for optimization is set to “1”.
(Step S35).

After that, the area priority optimizing means 23
Attention is paid to the third output terminal (FIG. 9, step S36). If the output terminal is not terminated (step S37 is N)
O), it is determined based on the contents of the output terminal table 37 whether or not the n-th output terminal corresponds to a path for performing area-priority optimization (step S41).

If it is determined that the n-th output terminal does not correspond to the path for performing the area-priority optimization (NO in step S41), attention is paid to the next output terminal (steps S46 and S36). .

When it is determined that the n-th output terminal corresponds to a path for performing area-priority optimization
(Step S41 is YES), a path trace is performed from the nth output terminal to the input terminal (step S42), and it is determined whether or not there is a portion to which the mth rule can be applied in the traced path. Judge (Step S
43).

If it is determined that there is no portion to which the m-th rule can be applied (NO in step S43),
The area priority optimizing means 23 pays attention to the next output terminal (steps S46 and S36), and if it is determined that there is an applicable portion (step S43 is YES), performs element conversion according to the m-th rule. (Step S44).

When the processing of step S44 is completed, the area priority optimizing means 23 sets the area priority rule application frequency table 41
Is updated (step S45), and the next output terminal is focused on (steps S46 and S36).

When the above-described processing is performed on all the output terminals (YES in step S37), the area priority optimizing means 23 determines the current stage based on the information indicating the area of each element stored in the library 31. Is estimated (step S38).

Then, when the estimation of the area has achieved the area target value stored in the area target storage unit 34
If (step S39 is YES), the processing is terminated, and if the processing is not achieved (step S39 is NO), the next rule is noticed (step S40 in FIG. 9, step S3 in FIG. 8).
3) The same processing as described above is performed.

When the processing of the area priority optimizing means 23 is completed, the application frequency updating means 24, as shown in FIG. 10, stores the delay priority rule application frequency table 40 and the area priority rule application frequency table 41 stored in the table 41. The temporary application count of the rule is obtained (steps S51 and S52), and the obtained temporary application count is added to the corresponding rule application count in the rule application count table 42 (step S53).

When the processing of the application frequency updating means 24 is completed, the rule sorting means 25 obtains the application frequency of each rule from the rule application frequency table 42 as shown in FIG.
(Step S61), the rules stored in the optimization rule base 36 are sorted in descending order of application number (Step S62).

In the above-described embodiment, the rule of the delay priority mode and the rule of the area priority mode stored in the optimization rule base 36 by using the rule separating means 21 are respectively used as the delay priority rule base 38, It is stored in the area priority rule base 39, and the delay priority optimization means 22 and the area priority optimization means 23 respectively store the delay priority rule base 3
8. The optimization is performed using the rules stored in the area priority rule base 39. However, the rules stored in the optimization rule base 36 are divided into a delay priority rule base 38 and an area priority rule base 39. It is needless to say that the optimization may be performed by the delay priority optimizing means 22 and the area priority optimizing means 23 using the rules stored in the optimization rule base 36 without separating them.

However, as in the embodiment, the rules stored in the optimization rule base 36 are separated into a delay priority rule base 38 and an area priority rule base 39, and the delay priority optimization means 22 and the area priority optimization means When the optimization is performed by using the rules stored in the delay priority rule base 38 and the area priority rule base 39 at 23, respectively, the number of times of referring to the rules is reduced, so that the processing speed is increased.

[0086]

As described above, according to the present invention,
The following effects can be obtained.

The delay priority rule base and area priority rule base
The rules stored in the source are sorted in order of the number of applications.
Delay priority optimization means, area priority optimization means
Are the delay priority rule base and the area priority rule base, respectively.
The process of optimizing by applying the rule, if the applicable rule for a logic circuit to be subjected to optimization by evaluating the rules in over scan in the storage order, continued until clearing the optimization target value Therefore, the number of rules to be evaluated before the optimization target value is cleared is smaller than in the conventional case, and as a result, the processing speed can be increased.

An output terminal table is provided to indicate whether each output terminal of the logic circuit to be optimized is a delay-first or an area-first one. First, the output terminal table indicates that the priority is delay-first. The optimization is performed using the delay priority optimizing means for the output terminal that has been set, and then the optimization is performed using the area priority optimizing means for the output terminal that is indicated to be area priority. Therefore, the logic circuit having a strict delay constraint has an effect of being easily optimized, and a logic circuit having a strict delay constraint and having a path that does not require a delay constraint has a large scale. There is an effect that the size can be reduced as compared with the related art.

[0089]

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a rule application count table 42;

FIG. 3 is a diagram showing a configuration example of a goal achievement table 32;

FIG. 4 is a diagram showing a configuration example of an output terminal table 37.

FIG. 5 is a flowchart showing a processing example of a rule separating unit 21;

FIG. 6 is a flowchart showing a processing example of the delay priority optimizing means 22;

FIG. 7 is a flowchart showing a processing example of the delay priority optimizing means 22;

FIG. 8 is a flowchart showing a processing example of the area priority optimizing means 23;

FIG. 9 is a flowchart showing a processing example of the area priority optimizing means 23;

FIG. 10 is a flowchart showing a processing example of an application count updating unit 24;

FIG. 11 is a flowchart showing a processing example of a rule sorting unit 25;

FIG. 12 is a diagram illustrating an optimization process.

FIG. 13 is a diagram for explaining an optimization process.

FIG. 14 is a diagram illustrating an optimization process.

FIG. 15 is a diagram illustrating an optimization process.

FIG. 16 is a block diagram of a conventional example.

17 is a flowchart showing a processing example of the logic optimizing unit 162. FIG.

FIG. 18 is a diagram illustrating a configuration example of an optimization rule base 166.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Input part 2 ... Control part 21 ... Rule separation means 22 ... Delay priority optimization means 23 ... Area priority optimization means 24 ... Application frequency update means 25 ... Rule sort means 3 ... Storage part 31 ... Library 32 ... Target achievement table 33 ... delay target storage unit 34 ... area target storage unit 35 ... connection information storage unit 36 ... optimization rule base 37 ... output terminal table 38 ... delay priority rule base 39 ... area priority rule base 40 ... delay priority rule application count table 41 … Area priority application count table 42… Rule application count table 4… Output section

Claims (2)

(57) [Claims] 1. An optimization rule base in which rules for performing logic optimization are stored, a delay priority rule base, an area priority rule base, and a rule stored in the optimization rule base.
Store the delay priority mode rules in the optimization rule base.
Stored in the delay priority rule base in the order in which they are stacked
And the rules of the area priority mode are
In the area priority rule base in the order in which
The rule separation means to accumulate and each output terminal of the logic circuit to be optimized
Output terminal for optimization of
An output terminal table that stores information indicating whether the terminal is an output terminal, and rules stored in the delay priority rule base.
Are evaluated in the order of accumulation of
In each path, delay priority optimization is performed on the output terminal table.
Corresponding to the output terminal that stores information indicating that
For each path, if applicable, apply the rule
Applying and optimizing processing, path delay time delay target
A delay priority optimizing means that continues until the value is cleared, and
The rules stored in the area priority rule base are
Each path in a logic circuit to be evaluated and evaluated in the order of accumulation is optimized.
Of the output terminal table should be optimized for area priority.
Corresponding to the output terminal storing the information indicating
Rules that are applicable to the rule
Optimizing the process, the area of the logic circuit is the target area value
And a rule sorting means for sorting the rules stored in the optimization rule base in the order of application times. 2. The data stored in the delay priority rule base
The delay priority optimizing means for each rule
That a delay priority rule application number table for holding a number of applications, each rule its accumulated in the area priority rule base
Of Re respectively, holding the number of applications by the area priority optimizing means
Table of the number of times the area priority rule is applied, and each rule stored in the optimization rule base
A rule application count table that holds each application count and the end of optimization processing for the logic circuit to be optimized
Each time, the delay priority rule application count table and the area priority
The rule application count based on the contents of the rule application count table
And a delay priority optimizing means , wherein the delay priority optimizing means includes a delay priority rule base.
Each time the rules stored in the
Of the application counts held in the rule application count table,
Configuration to update the number of applications corresponding to the rule used
The area-priority optimizing means is based on the area-priority rule base.
Each time the rules stored in
Of the application counts held in the rule application count table,
Configuration to update the number of applications corresponding to the rules used
2. The logic optimizing device according to claim 1, wherein: