JP2635995B2 - System with processor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system having a microprocessor, and more particularly, to a system having boards interconnected via a bus.

[Conventional technology]

August 31, 1985, p143-p of EDN
156 (title “Two busesvie for 32-bit system suprema
cy ". Author Jon Titus describes VME bus and Multi bus II.

[Problems to be solved by the invention]

In recent years, microcomputers have been used in response to a wide range of demands from various application fields. Process control and industrial automation require real-time response, image processing requires high-speed processing of large amounts of data, and computer graphics requires both. To meet these demands, computer architecture employs a system bus that electrically and mechanically connects modules such as CPU boards, memory boards, and I / O boats.

In the real-time data processing field, a function field type control method in which a dedicated processor is assigned to each function so as to optimize the response of each function is often used. on the other hand,
In the field of mass data processing, it is necessary to increase the average processing capacity. For this reason, in the field of large-volume data processing, a load-distribution control method for evenly distributing loads among processors having the same function is generally used.

As a system bus, VMEbus or Multi bus II has been proposed. However, these buses cannot provide satisfactory performance in both of the two fields mentioned above: real-time processing and large data processing.

An object of the present invention is to provide a general-purpose bus suitable for both of the two fields described above.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, the present invention provides a system for performing distributed bus arbitration by providing a function of managing a bus use right to all the modules that can be a bus master among a plurality of modules (boards) connected to a bus, The bus arbitration includes a first phase indicating an empty state of the bus, and arbitration for granting the bus use right to one of the plurality of bus masters that have simultaneously issued the bus acquisition request based on a predetermined priority. A second phase in which the bus acquisition request of the bus master is frozen, data transfer by the bus master to which the bus use right has been given in the second phase, and the bus use right can be obtained in the second phase. A third phase in which arbitration between other bus masters is performed in parallel; And a fourth phase in which data transfer is performed by the bus master having the lowest priority among the bus masters that have participated in the arbitration in the phase, and a bus acquisition request is released from being frozen. Is
A first priority that can issue a bus acquisition request only in the first and fourth phases;
A second priority capable of issuing a bus acquisition request in any of the third and fourth phases;
A third priority that can issue a bus acquisition request in any of the second, third, and fourth phases and that can request a bus master having the current bus use right to suspend bus use; Is to be ranked.

[Action]

According to the above-described means, uniform bus arbitration between boards can be realized by distributed bus arbitration, and load distribution in the field of mass data processing can be easily performed. In addition, by using three levels of bus arbitration priority, in an emergency, bus use can be interrupted, a higher priority bus use request can be handled, and a real-time data processing request can be handled.

〔Example〕

The mechanical specification of the system bus (hereinafter referred to as TOBUS) of the embodiment is used for the euro card specification generally used widely in the board system. FIG. 1 shows the outline of the board. The bus signal connector uses a IEC603-2 standard 96-pin connector. The 32-bit TOBUS has a signal distribution that can be connected with a single 96-pin connector. P2 is dedicated to a high-speed data transfer bus (hereinafter referred to as TOXBUS),
P3 is for 64-bit expansion of TOBUS and TOXBUS.

Table 1 shows the signal distribution in these pin connectors.

FIG. 2 shows a configuration example of a system using TOBUS.
This example is a function-distributed system, which includes a CPU board, a memory board, and an intelligent type input / output board (hereinafter, referred to as an I / O board). I / O
The board functions as a bus master and performs direct memory access (DMA) transfers. It is the function of the bus arbiter to determine the right to use the bus. In this system, there are two types of interrupt, a message interrupt dedicated line interrupt.

3 (A) to 3 (D) illustrate the development of a system using TOBUS.

In the following, data transfer, interrupt, and bus arbitration, which are the basic functions of TOBUS, will be described focusing on the protocol.

Bus arbitration The bus arbitration method has a great effect on the performance of the entire system. The methods are roughly classified into a decentralized type and a centralized type. In the decentralized system, all modules that become bus masters have the function of managing bus usage rights,
In the centralized system, one module collectively manages the right to use the bus. The centralized type is excellent in terms of responsiveness, but the number of bus masters that can be controlled is physically limited, and the existing bus is at most There are about five. Although the number of bus masters can be increased by the daisy chain, the responsiveness is significantly reduced. TOBUS adopted a decentralized system that is suitable for parallel processing systems and has excellent fault tolerance. In TOBUS, a unique priority number is given to a bus master, and a bus master requesting the right to use the bus outputs the priority number to the bus, and compares its own priority number with the priority number on the bus by an internal comparison circuit. Perform arbitration. Furthermore, in order to enhance the real-time response, the bus masters are assigned a normal priority (first priority), a high priority (second priority), and a super priority (third priority) in accordance with the priority.
Priority). FIG. 4 shows a state transition diagram of the bus arbitration. Tables 2 and 3 show the priority of bus arbitration.

In FIG. 4, PH1 (first phase) indicates an idle state, in which the data bus is free, and
(Second phase) indicates an arbitration phase, in which each bus master compares its own priority number with the priority number output to the bus, and determines the bus master with the highest priority number. At this time, the other bus masters
The bus request is frozen. PH3 (third phase) indicates a data transfer / absorption phase, and the bus master determined in the PH2 phase performs data transfer. At this time, the bus master that could not obtain the bus in the phase of PH2 compares the priority numbers again and determines the next bus master to obtain the bus. PH4 (fourth phase) is a data transfer phase in which the bus master with the lowest priority number performs data transfer. The freeze of the bus request from another bus master is released.

Among the normal priorities, the bus master having the highest priority number (WINNER) which has issued the bus acquisition request at the same time acquires the right to use the bus first. When the bus cycle starts, the remaining bus masters (LOSERs) that have issued the bus acquisition request start comparing the priority numbers again, and the bus master with the highest priority number uses the bus next.
In this way, every time a higher-level master starts using the bus, among the bus masters that have issued a bus acquisition request at the same time, the bus master that has not yet used the bus and is waiting determines the priority, and We use bus in order.

In normal priority, other bus masters freeze the bus request and cannot participate in arbitration until all bus masters that have simultaneously made the bus acquisition request have used the bus. This guarantees that the bus requester can use the bus at the same time.

However, if the bus request is frozen, even if the priority is high, it cannot participate in arbitration and cannot use the bus immediately. For this reason, processing that requires a real-time response such as a message type interrupt may not be performed. To solve this, TOBUS defined a high priority for emergency bus use. The high priority bus master does not freeze the bus request, even if another bus master has issued the bus request, and can participate in the arbitration cycle when the current bus master finishes the bus cycle.

In the arbitration of TOBUS, when the current bus master starts using the bus, the next bus master is determined. In other words, priority comparison, determination, and bus use are pipelined. Therefore,
After the arbitration phase is completed, even if the high-priority bus master participates in arbitration and starts comparing priority numbers, the bus master currently executing the data transfer finishes using the bus and the next one. After the master started using the bus.

To further enhance emergency response, TOBUS has defined a super priority that can notify the current bus master that the bus needs to be released urgently. The bus master receiving this report must immediately suspend bus use.

Table 2 shows participation in arbitration. For example, in normal priority, it is possible to participate in arbitration in phase PH1, but not in phase PH2. I have. Table 3 shows bus release requests. In super priority, bus release can be requested in all phases. However, in normal priority and high priority, bus release can be requested. Indicates that it cannot be done.

FIG. 5 shows a block diagram of the arbitration control circuit.

FIG. 6 shows a waveform diagram of bus arbitration between the four normal priorities, and FIG.
The figure shows a waveform diagram of bus arbitration between normal priority and high priority.

Table 4 shows the arbitration numbers of the bus masters in FIG. In the table, ANB1 to ANB4 are ma
Arbitration numbers of ster1 to master4.

In FIG. 6, TB1 to TB4 (TB) and BG11 to BG14 (BG)
Is a control signal for the bus arbiter. TB1 to TB4 are master1
Asserted when ~ master4 requests the bus. Also, BG1 to BG4 are arted when the arbiter grants master1 to master4 bus use. The number written on the BBSY signal indicates the current bus master.

BR, BRL, BLI, BAC, and BBSY are driven by the arbiter. When the arbiter issues a bus request, BR goes low. Normal priority freezes bus and BRL
To a high level. BRLI is a signal obtained by inverting BRL. All bus requests are frozen at the rising edge of BR1, and all bus requests are released at the rising edge of BRLI. When the BAC signal is at the LOW level, the bus arbiters compare their arbitration numbers. BAC
At the rising edge of the signal, [winner] starts using TOBASU and sets the BBSY signal to low level.

The number written on the BAC signal indicates the arbitration phase. Table 5 shows the bus masters and [winner] who participated in the arbitration phase.

Table 6 shows the arbitration numbers of the four bus masters in the waveform diagram shown in FIG.

In FIG. 7, the number written on the BBSY signal indicates the current bus master, and the number written on the BAC signal indicates the arbitration phase. Table 7 shows the bus masters and [winner] who participated in the arbitration phase.

Data transfer There are two types of data transfer protocols: synchronous and asynchronous.
In the clock synchronization method, it is necessary to change peripheral hardware when the clock frequency of the CPU is changed, or the number of boards connected to the bus, that is, the bus load varies depending on the usage conditions, so the clock phase difference varies. In addition to the problem, when the clock frequency exceeds 20 MHz, there is a serious disadvantage that it is impossible to operate the entire system in synchronization with the clock. Therefore,
The transfer protocol of TOBUS adopted an asynchronous protocol.

Using separate signal lines for address and data requires 32bi
If the bus width is changed to 64 bits in the future as well as the t bus, it is particularly disadvantageous in terms of the number of connectors and the mounting area of the board. Further, there is a disadvantage that the current consumption of the entire board increases because two sets of bus drivers need to be operated. Therefore, TOBUS shares signal lines for address and data.

By sharing addresses and data, performance degradation is a concern. However, data transfer in TOBUS is mainly block transfer such as data read into cache memory or message transfer at the time of cache mishit. In this case, if the address is transferred only once at the beginning, it is not necessary to transfer it every time. If the number of words is long, the multiplex overhead can be ignored.

FIG. 8 shows TOBUS read transfer and write transfer. At the time of address transfer, the bus master gives the timing at which the slave should latch the address with the ALT signal. Data transfer begins when the bus master asserts the DS signal, the slave asserts the DK signal, and the master responds.
It ends by negating the DS signal. At the time of address transfer, the transfer destination address and address space are transferred, and a data transfer type such as block transfer or broadcast transfer is specified. At the time of data transfer, in addition to the data, a status indicating an error occurrence status accompanying the transfer is also transferred. Note that the address space signal and the stator signal share a signal line. Generally, since a signal designating a byte sequence has a meaning as an address, the slave board is designed to start data transfer after a byte sequence control signal is asserted. In TOBUS data transfer, the byte string designation signal is valid during the period from the start of address transfer to the end of data transfer. As a result, the slave can generate the chip select signal inside the board immediately after receiving the address transfer. In particular, it is easy to secure the data setup time in the write cycle of the memory, which is advantageous for shortening the cycle time. In the figure, AD00: 63
Indicates an address / data, BC0: 7 indicates a byte length control, ALT indicates an address latch or timing, DS indicates a data strobe, DK indicates a data acknowledge, and WR indicates a data transfer direction.

Interrupts As interrupts of the TOBUS, as shown in FIG. 9, an interrupt due to a message transfer and an interrupt using a signal line dedicated to the interrupt are defined.

Interruption by a message is effective in realizing a multiprocessor system such as synchronizing between processors on TOBUS.

The message interrupt is realized as data transfer from an interrupt request source to an interrupt destination in a message interrupt space, which is one of the address spaces. That is, as shown in FIG. 10, in data transfer, a request destination number is put in an address, and a request source number and a message type are put in data, and then transferred. The message type is used to distinguish the transfer of interrupt messages from the transfer of other messages.

Interrupts using the dedicated signal line include an emergency interrupt such as a system reset or a bus fail and an interrupt using the interrupt request signals IRX and IRY. The former does not perform an interrupt acknowledge cycle on TOBUS. The latter is TOB
An interrupt acknowledge cycle is performed on the US, and the request source transfers the interrupt vector to the request destination.

FIG. 11 shows a conceptual diagram of the message interruption.

In the figure, when CPU-B generates an interrupt to CPU-A, CPU-B transfers the address of the receiver to the requester. The requester obtains the right to use TOBUS and forwards the message type and the address of the requester to the receiver. The receiver generates an interrupt to CPU-A.

FIG. 12 shows a configuration example of the above-described receiver, and FIG. 13 shows a configuration example of the requester.

 In FIG. 12, Reg1 to Reg4 indicate the following.

Reg1 (vector base register): Register that sets the external interrupt vector No. (# 80 to n) of the CPU.

Reg2 (source address register): Register that latches the source address that issued the interrupt to TOBUS.

Reg3 (message type register): Register that sets the message type of TOBUS that receives an interrupt to the CPU.

Reg4 (Receive message type register): Register that latches the message type in TOBUS message transfer.

Message interrupt reception operation (1) The CPU writes the start number of the vector No. to Reg1, the message to accept the interrupt to Reg3, and initializes the register. No interrupt is accepted until this initialization is completed. If an interrupt request is issued before initialization, an access error is returned to the request source.

(2) When the initialization of the registers is completed and the following conditions are satisfied, the interrupt receiver accepts the interrupt.

i The request destination number in the message transfer must match the receiver address.

ii One-to-one or message transfer by broadcast transfer in the message interrupt space.

iii The message type set in Reg3 and the message type at the time of TOBUS message transfer must match.

If ii and iii do not hold, an access error is returned to the request source.

(3) After the interrupt condition is satisfied, issue an interrupt to the CPU.

(4) The vector No. in the IACK cycle of the CPU is Reg1 and
The result of adding Reg2 is returned to the CPU as a vector No.

In Fig. 13, Reg5 (destination address register)
In, the CPU writes the transmission destination of the message interrupt as data.

Message interrupt transmission operation (1) Before requesting a message interrupt, the CPU must write the vector number to the vector number generation register.

(2) When the CPU issues a message interrupt to TOBUS, the CPU writes the transmission destination address as data in Reg5.

(3) When the CPU write is completed, the interrupt requester asserts a use request signal (TB) to the bus arbiter. (At the same time, IRQBUSYN) is also asserted.

(4) If the bus use permission signal (BG1) is asserted by the arbiter after the arbitration is completed, the interrupt requester sets the destination address (Reg5), message type,
The request source address is output to TOBUS.

(5) When an access error is returned from the transmission destination, the interrupt requester releases the bus (TB negation) and issues an interrupt to the CPU.

At normal end, release the bus and wait for the next CPU write.

(6) The status at the time of issuing the access error is latched in the error status register.

(7) If the CPU attempts to write the next data to Reg5 when the interrupt requester transmits a message interrupt, it returns a bus error to the next (message interrupt request) CPU. (DC, BUSERR generation block) [Effect of the Invention] By distributed bus arbitration, uniform bus arbitration between boards can be realized, and load distribution in the field of large-scale data processing can be easily performed. In addition, by using three levels of bus arbitration priority, in an emergency, bus use can be interrupted, a higher priority bus use request can be handled, and a real-time data processing request can be handled.

[Brief description of the drawings]

FIG. 1 is a diagram showing an external shape of a board, FIG. 2 is a block diagram showing one embodiment of the present invention, FIGS. 3 (A) to 3 (D) are diagrams for explaining TOBUS, FIG. 4 is a state transition diagram of bus arbitration, FIG. 5 is a block diagram of an arbitration control circuit, and FIGS.
FIG. 8 is a waveform diagram for explaining data transfer, FIG. 9 is a diagram for explaining interrupts, FIG. 10 is a diagram for explaining message interrupts, FIG. FIG. 11 is a conceptual diagram showing the configuration of a message interrupt, FIG. 12 is a block diagram showing one embodiment of a receiver, and FIG. 13 is a block diagram showing one embodiment of a requester.

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-62-133554 (JP, A) JP-A-60-198662 (JP, A) JP-T-62-501039 (JP, A)

Claims (1)

(57) [Claims] 1. A system for performing distributed bus arbitration by assigning a function of managing a bus use right to all modules that can become a bus master among a plurality of modules connected to a bus, the system comprising: The arbitration includes performing a first phase indicating an empty state of the bus, and arbitration for granting the bus use right to one of the plurality of bus masters that have simultaneously issued the bus acquisition request based on a predetermined priority. A second phase of freezing a bus acquisition request of the bus master, a data transfer by the bus master to which the bus right has been given in the second phase, and a bus transfer right in the second phase. Third arbitration between the other bus masters, which could not be obtained, to perform the arbitration in parallel And a fourth phase in which, among the bus masters that have participated in the arbitration in the second phase, data transfer is performed by the bus master having the lowest priority, and a freeze of the bus acquisition request is released. A plurality of the modules that can be the bus master include a first priority that can issue the bus acquisition request only in the first and fourth phases, and a first, a second, a third, and a fourth. A second priority at which the bus acquisition request can be issued in any of the phases, and a bus acquisition request that can be issued at any of the first, second, third and fourth phases. A third plug which can request the bus master having the right to use the bus to suspend the use of the bus. Oriti, characterized by comprising been ranked into one of,
A system having a processor.