JP2635622B2 - Power supply voltage switching circuit - Google Patents

Description

The present invention relates to a power supply voltage switching circuit, and more particularly, to a power supply voltage switching circuit used for an EEPROM.

(Prior art) A high voltage is required to rewrite and erase EEPROM memory cells, which are electrically programmable and erasable programmable ROMs, by injecting and extracting charges into the floating gate through a thin gate oxide film. Required.

FIG. 2 is a circuit diagram showing an example of a power supply voltage switching circuit used in an EPROM of a type for supplying a high voltage from the outside. This circuit is composed of four transistors T ₁ through T _4, the source and drain of n-channel MOS transistor T ₁ is connected to the node N ₁ and N ₂ respectively, transistors T ₁
The power supply voltage V _DD is applied to the gate of. here,
Node N ₂ is a high voltage output terminal, the node N ₁ is relatively circuit for generating a switching signal operating power supply voltage at a low voltage serves as an input end (hereinafter, referred to as low-voltage operation system.) Are connected I have. N-channel MOS transistor T ₂ and P-channel MOS
The transistor T ₃ is connected in series, the node N ₃ is the common connection point is connected to the gate of the P-channel MOS transistor T _4. The source and the drain of the transistor T ₄ are respectively connected to the high voltage terminal V _PP and node N _2, the drain of the transistor T ₃ is connected to the high voltage terminal V _PP. The gate of the transistor T ₂ are connected to the node N _1, the drain is placed, is configured to a high voltage is supplied from the source.

 The circuit configured as described above operates as follows.

The node N ₁ and the high level during the boosting node N _2, which is the output point. Then, the transistor T ₂ is turned on, the node N ₃ becomes a low level, the transistor T ₄ is conductive, the node N ₂ is boosted by the power supply voltage V _PP. Therefore, the transistors T ₁ and T ₃ are turned off, and the low-voltage operation system (not shown) connected to the node N ₁ is disconnected from the node N ₂ due to the non-conduction state of the transistor T ₁ , and the high voltage V _PP protected from, with breakdown of the device is prevented, the node N ₃ by the non-conducting state of the transistor T ₃ is a low level is maintained, so that the conductive state of the transistor T ₄ is maintained.

The node N ₁ and the low level in the case of step-down the node N ₂ to the low level. Thus, transistor T ₁ is turned, the node N ₂ is stepped down, the transistor T ₃ is turned on by a low level, a high level node N ₃ by the power source voltage V _PP, transistor T ₄ is rendered non-conductive, node N ₂ becomes to be stabilized at a low level.

As described above, the high-level voltage from the node N ₂ by the node N ₁ to a high level, it is possible to output a low level voltage by the node N ₁ to the low level.

However, this circuit has a problem that a through current flows transiently through the transistors T ₃ and T ₂ . This is the node N ₁
Occurs when the level changes from low to high. As described above, conducting the transistor T ₃ when the node N ₁ is at a low level, the transistor T ₂ has become non-conductive, when launching the node N ₁ to the high level, the transistor T ₂ is turned on, the transistor T ₃ becomes non-conductive,
Since a delay time occurs from the conduction of transistor T ₂ until the transistor T ₃ is turned off, the transistor
This is because there is a period in which T ₂ and T ₃ are simultaneously in a conductive state, and a through current flows through the transistors T ₂ and T ₃ only during that period.
Therefore, when such a circuit is used as a built-in voltage switching circuit of the EERPOM, a malfunction occurs.

Since power supplies that supply high voltage generally do not have sufficient current supply capability, circuits that do not allow excessive current to flow through the power supply voltage switching circuits provided for each word line or bit line desirable.

In recent EEPROMs, this high voltage is not supplied from the outside of the chip, but is supplied from a booster circuit provided inside the chip so that it can operate with a single power supply.

FIG. 3 shows a schematic circuit configuration of a power supply voltage switching circuit that has no through current and supplies a higher voltage than a booster circuit provided inside the chip. The n-channel MOS transistors T ₅ and T ₆
And a n-channel MOS transistor T ₇ and the capacitor C ₂ Metropolitan constituting the capacitor C ₁ and the charge pump circuit for charge storage and. Between the node N ₄ and N ₅ is connected to the source and drain of the transistor T ₅ is the power supply voltage V _DD is applied to the transistor T _5. The node N ₄ is an input terminal is connected to the output terminal of the low voltage operation system of the decoder, the node N ₅ is the high voltage output terminal. This circuit charges capacitor C ₁ connected to the node N _5, so that the high voltage is supplied.

The charge pump circuit is connected to the node N ₇ via the capacitor C _2.
The clock phi ₁ supplied from the node N ₅ is connected to the capacitor C ₁ via the transistor T ₇ is charged up. Drain and source of the transistor T ₆ are respectively connected to the high voltage terminal V _PP and node N _6, the gate node N ₅ is connected. In this circuit provides the clock phi ₁ to the amplitude of the voltage value of the power supply terminal V _DD as shown in FIG. 4 to the node N _7.

If the node N ₅ is boosted, and the node N ₄ to a high level, and supplies the clock phi ₁ to the node N _7. Then, the transistor T ₅ is to become nonconductive, the node N ₆ a low voltage operation system even when a high voltage is protected from the high voltage.
The clock phi ₁ is the electric charge of the capacitor C ₂ from the capacitor C ₂ and the node N ₆ by the charge pump circuit comprising a transistor T ₇ in the period of the high level to the node N ₅ is transferred, as the capacitor C ₁ is charged it is boosted node N _5. Thus the transistor T ₆ conducts, node the period of the clock phi ₁ is low level
N ₇ becomes a low level, so that the capacitor C ₂ is charged. Later, it is possible to clock phi ₁ is the node N _5, N ₆ are stepwise boosted by a predetermined level each time a high level, and outputs a predetermined high voltage from the node N _5.

When the node N ₄ to a low level, the transistor T ₅ is rendered conductive, the capacitor C ₁ is discharged, so that the node N ₅ is stepped down. When the node N ₅ becomes low level, the transistor T ₆ is turned off. Disconnected and the node N ₆ and the power supply voltage V _PP is, for the node N ₆ will not be boosted, and be stable at a low level.

(Problems to be solved by the invention) By the way, when the EEPROM is used for portable use, the power supply is usually a battery, so the voltage is as two dry batteries.
2.5-3V. Assuming that the voltage of the power supply terminal V _DD is 2.5 V, the charge transferred from the capacitor C ₂ to the capacitor C ₁ through the transistor T ₇ is very small because the amplitude of the node N ₆ is not so large.

On the other hand, has a relatively large value for capacitor C ₁ is configured with a load capacity of the normal word line or bit line. Therefore the potential of the node N ₅ and the charge is less transferred from the capacitor C ₂ to the capacitor C ₁ is increased becomes difficult. In particular, when a low-voltage power supply such as a dry battery is used as the voltage of the power supply decreases, it becomes impossible to switch to a high voltage by the circuit shown in FIG.

As described above, the power supply voltage switching circuit having the charge pump circuit as shown in FIG. 3 used in the conventional EEPROM has no through current but cannot be switched to a high voltage with a low voltage power supply. Had the disadvantage that

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to provide a power supply voltage switching circuit that can switch to a high voltage even with a low voltage power supply.

[Configuration of the invention]

(Means for Solving the Problems) A power supply voltage switching circuit according to the present invention is an N-channel type in which a voltage switching command input signal is provided at one end, an output terminal is provided at the other end, and a power supply voltage is provided at a gate. A first MOS transistor; a load capacitor connected to the output terminal;
A source is connected to the output terminal, a drain is connected to a high-voltage power supply, and N is turned on by an increase in the gate voltage.
A second MOS transistor of a channel type, and an N-channel type third MOS transistor having a gate commonly connected to the gate of the second transistor and a drain connected to the high voltage power supply.
An S transistor, a charge pump circuit connected between the source of the third transistor and the gate common connection point, an N transistor connected between the output terminal and the gate common connection point, and a power supply voltage supplied to the gate. Channel type 4th
And a MOS transistor.

(Operation) At the time of high voltage output, the voltage switching command input signal is set to the high level, the output terminal and the charge pump circuit are cut off by the fourth MOS transistor, and the potential of the gate common connection point of the second and third transistors is set. Is increased by the operation of the charge pump circuit, and the load capacitance is charged by turning on the second transistor, thereby increasing the potential of the output terminal. When outputting a low voltage, the voltage at the output terminal is released by setting the voltage switching command input signal to a low level to obtain a low voltage. Therefore, in one cycle of the clock supplied to the charge pump circuit, the boosted potential at the common gate connection point is increased, and a high voltage can be obtained even with a low voltage power supply.

(Example) Hereinafter, one example of the present invention will be described in detail. FIG. 1 is a circuit diagram showing an example of a power supply voltage switching circuit according to one embodiment of the present invention.

The gates of the n-channel MOS transistors T ₉ and T ₁₀ are commonly connected at a node N ₁₀ , and the drains are also connected to the high voltage terminal _VPP . This high voltage terminal V _PP is EE
A power supply terminal used for rewriting and erasing a memory cell such as a PROM, and an output terminal of a booster circuit separately provided inside the chip. Between the gate and source of the transistor T ₁₀ is connected likewise charge pump circuit to that shown in Figure 3. That is, the charge pump circuit includes the transistor T
₁₀ and n-channel MOS transistor T ₁₂ is connected between the gate and the source of, and a capacitor C ₄ is connected between the source and the clock pulse terminal N ₁₂ of the transistor T _10. N-channel MO further constituting the transfer gate between the source and the gate of the transistor T ₉
S transistor T ₁₁ is connected. This transistor T ₁₁
The power supply voltage V _DD is applied to the gate of.

Incidentally, the node N ₉ in the figure, the word line or bit line is connected to a high voltage output terminal, the capacitor C ₃ represents the load capacitance. The node N ₈ is connected to the output terminal of the decoder operating on low voltage system, the node N ₈ and node N ₉
And between the transistor T ₈ is connected to the power supply voltage V _DD is applied to its gate. Lifting the node N ₉ to a high voltage when the node ₈ becomes high level is a function required for the power supply voltage switching circuit.

 Next, the operation of the circuit shown in FIG. 1 will be described.

In order to output a high voltage, a high level signal of the decoder output is applied to the input terminal N _8. The transistor T which is turned on by applying the power supply voltage V _DD to the gate by this signal
The level of the node N ₉ rises through ₈ and the transistor T ₈
Turns off to protect the input side from high voltage. Node N ₉
Elevated levels of also rises again turned to that level of the node N ₁₀ transmitted to the node N ₁₀ via the transistor T _11. Since this time the level of N ₁₀ is considerably lower than V _DD, the transistor T ₁₁ is the completely not turned off, the transistor T ₉ is not fully turned on. Nodes in N ₁₂ Similarly clock phi ₁ is added to the conventional circuit shown in FIG. 3, the node N ₁₂ is a node through a transistor T ₁₂ charges the capacitor C ₄ is the charge pump when the high level N
Go to ₁₀ .

Thus, the charge generated by the charge pump circuit
Although the potential of node N ₁₀ rises by reaching the N _10,
Some of the charge to charge the load capacitance C ₃ through the transistor T _11, raising the potential of the node N _9. Therefore, the potential of the capacitor C ₃ and the transistor T _9, T amount corresponding node N ₁₀ a total capacity of the gate capacitance was charged ₁₀ rises.

Then the capacitor C ₄ When the node N ₁₂ becomes the low level is charged by the clock phi _1. Thereafter the same operation is repeated a node N ₁₀ will be is sequentially boosted. Then, as the increasing potential at the node N ₁₀ is, the transistor T
₉ and T ₁₀ are turned on, and the high voltage V _PP
9 through raising the potential of the node N ₁₁ causes rapid charge the load capacitor C _3. Also, when the threshold voltage of the transistor T ₁₁ and the V _th, the node N ₁₀ potential V _DD -V of
exceeds _th transistor T ₁₁ is turned off. As a result,
Since the load capacitance C ₃ by the electric charge transferred from capacitor C ₄ via the transistor T ₁₂ is not charged, the boosted voltage difference between the node N ₁₀ on each cycle of the clock phi ₁ is increased, the node Na is a high voltage output terminal Rises rapidly.

Further, in order to output a low voltage, low level signal of the decoder output is applied to the input terminal N _8. Nodes N ₉ and N ₁₀ in this case becomes transistors T ₈ and T ₁₁ are turned on
For lowering the electric potential, low voltage output appears at the output node N _9.

If this way, to obtain a high voltage by the step-up circuit on-chip in this embodiment, the amplitude of the clock phi ₁ is small due to the low supply voltage such as a battery, that is, the capacitor C ₄
Can is increased the potential of rapidly node N ₁₀ even when the charge is transferred to the node N ₁₀ via the transistor T ₁₂ is less from become.

〔The invention's effect〕

As described in detail based on the above embodiments, according to the power supply voltage switching circuit of the present invention, a low-voltage power supply and a booster circuit provided inside the chip are used while maintaining the characteristic that there is no through current. Even in such a case, the voltage can be quickly switched to a high voltage, so that a good operation can be performed particularly when the present invention is applied to a portable use EEPROM using a battery as a power supply.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a power supply voltage switching circuit according to the present invention, FIGS. 2 and 3 are circuit diagrams showing an example of a conventional power supply voltage switching circuit, and FIG. FIG. 3 is a waveform diagram showing a clock applied to a circuit. V _PP …… High voltage output terminal, V _DD …… Power supply terminal, N _{1 to} N ₁₁ …
… Node, T ₁ , T _{2 to} T ₁₂ …… transistor, C ₃ …… load capacitance, C ₄ …… capacitor.

Claims (2)

(57) [Claims] A voltage switching command input signal is provided to one end,
The other end is an output terminal, an N-channel type first MOS transistor having a gate supplied with a power supply voltage, a load capacitor connected to the output terminal, a source connected to the output terminal, and a drain connected to a high level. N connected to a voltage power supply and turned on by an increase in its gate voltage
A channel-type second MOS transistor; an N-channel type third MOS transistor having a gate commonly connected to the gate of the second transistor and a drain connected to the high-voltage power supply; and the third transistor A charge pump circuit connected between the source and the gate common connection point; an N-channel type fourth MOS connected between the output terminal and the gate common connection point and having a power supply voltage supplied to the gate
A power supply voltage switching circuit including a transistor. 2. A power supply voltage switching circuit according to claim 1, wherein a decoder output is connected to one end of said first MOS transistor, and a word line or a bit line is connected to said output terminal. .