JP2624178B2 - Data transmission system using multiple ISDN lines - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ISDN data transmission system, and more particularly to a high bit rate data transmission system using a plurality of ISDN lines.

[0002]

2. Description of the Related Art FIG. 17 shows a conventional data transmission system using a plurality of ISDN lines. Terminal (DTE) 4-
1 and 4-2 are respectively connected to the I / O through a multiplexer / demultiplexer.
It is connected to the SDN line 5. The multiplexing / demultiplexing device includes a multiplexing unit 2 and a demultiplexing unit 3. However, the multiplexing / demultiplexing here means multiplexing / demultiplexing performed between a plurality of ISDN line signals and one terminal signal.

First, a terminal signal a-1 output from a terminal 4-1 is input to a demultiplexing unit 3-1 and separated by a data demultiplexing unit 6 into data signals b-1 to b-6 corresponding to the line speed. At the same time, each of the flag signals c-1 to c-6 is generated, and these signals are input to the flag insertion unit 7. The flag insertion unit 7 adds the flag signal c to the data signal b to generate line signals d-1 to d-6, and outputs them to the network-side interfaces (INF) 8-1 to 8-3.

The network-side INFs 8-1 to 8-3 form network-side signals e- 1 to e- 3 based on the input line signal d, and this network-side signal e is transmitted via the ISDN line 5 to the other party's side. This is transmitted to the network side INFs 8-4 to 8-6 of the multiplexing unit 2-1.

The network-side INFs 8-4 to 8-6 generate line signals d-7 to d-12 based on the received network-side signal e and output them to the flag detectors 9-1 to 9-6, respectively. The flag detectors 9-1 to 9-6 detect the flag signals c-7 to c-12 from the line signals d-7 to d-12 and separate the data signals b-7 to b-12. Data assembling unit 10
Performs assembling of a data signal according to the detected flag signals c-7 to c-12, and assembles a terminal signal a-2.
To the terminal (DTE) 4-2.

FIG. 18 is a diagram showing a frame structure of a line signal d used in the conventional system. This configuration complies with the CCITT H221 recommendation used in video conferences and the like. As shown in FIG.
Each octet is composed of 80 octets, and one frame is composed of 80 octets. D _{1 to} D ₆₂₄ are data signals, and FAS
Is a flag signal, and BAS is a control signal between multiplexing / demultiplexing devices.

[0007]

However, in the above-mentioned conventional system, the flag signals c-1 to c-6 are added to the data signals b-1 to b-6 corresponding to the respective ISDN lines and transmitted. In addition, the sum of the transmission speeds of the data signals through the ISDN line 5 becomes smaller than the transmission speed of the terminal signal a-1 by the transmission speed of the flag signal.
There is a problem that the use efficiency of the N line is reduced.

An object of the present invention is to provide an ISDN transmission system capable of preventing a decrease in the transmission speed of a data signal to be transmitted when performing high bit rate transmission using a plurality of ISDN lines.

[0009]

A data transmission system according to the present invention separates a data signal to be transmitted into a B channel signal corresponding to each B channel and a D channel signal corresponding to each D channel of a plurality of ISDN lines. A data separation unit, a control signal insertion unit for adding a control signal to each of the B channel signals, a transmission unit for transmitting a B channel transmission signal and a D channel signal to which a control signal is added through a plurality of ISDN lines, Receiving means for receiving a B-channel transmission signal and a D-channel signal from a line, control signal detection means for detecting a control signal from the B-channel transmission signal, and assembling the B-channel signal and the D-channel signal based on the control signal Data assembling means for outputting an original data signal.

[0010]

The high bit rate data signal is transmitted by using the B channel signal and the D channel signal of a plurality of ISDN lines together. By treating the control signal added to the B channel signal and the D channel signal equally, the transmission rate of the high bit rate data signal can be made equal to the sum of the transmission rates of the B channel of the ISDN line.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a demultiplexing unit in an embodiment of a data transmission system according to the present invention.

In FIG. 1, terminals 4-1 to 384 Kb
ps terminal data signal a-1 is transmitted to the multiplexer / demultiplexer 1-1.
When the terminal data signal a-1 is output to the data signal b-6 of 62.4 Kbps,
1 to b-6 and a data signal b-13 of 9.6 Kbps. Further, the data separation unit 6 outputs the data signal b
Output 1.6 kbps flag signals c-1 to c-6 respectively corresponding to -1 to b-6, and output flag insertion units 7-1 to 7-
In step 6, the flag signals corresponding to the respective data signals are added, and line signals d-1 to d-6 of 64 Kbps are formed. The line signals d-1 and d-2 are sent to the network side INF 8-1.
The line signals d-3 and d-4 are input to the network-side INF 8-2, and the line signals d-5 and d-6 are input to the network-side INF 8-3, and a data signal of 128 Kbps is formed. Through the B channel.

On the other hand, the 9.6 Kbps data signal b-13 separated by the data separation unit 6 is input to the layer 3 control unit 11-1, and the 3.2 Kbps D channel signals f- 1 to f- 3 are output. Generated, and the network-side INFs 8-1 to 8-
3 is output. Thus, the data signal b-13 corresponds to each I
The packet is transmitted through the D channel of the SDN line.

FIG. 2 is a block diagram showing the configuration of the multiplexing unit in the present embodiment. As described above, the network-side data signals e-1 to e-3 transmitted through the B and D channels of each ISDN line are received by the network-side INFs 8-4 to 8-6, of which the line signal d-7 of 64 Kbps is received. ~ D-1
2 is output to the flag detectors 7-7 to 7-12 and 3.2.
D-channel signals f-4 to f-6 of Kbps are output to layer 3 control section 11-2.

Each of the flag detectors 7-7 to 7-12 outputs 1.
6 Kbps flag signals c-7 to c-12 are detected,
It is output to the data assembling unit 10 together with the data signals b-7 to b-12 of 62.4 Kbps. The layer 3 control unit 11-2 receives the D channel signals f-4 to f-6 and outputs a 9.6 Kbps data signal b-14 to the data assembling unit 10.

The data assembler 10 generates data signals b-7 to b-1 according to the detected flag signals c-7 to c-12.
2 and b-14 are assembled, and a terminal data signal a-2 of 384 Kbps is output to the terminal 4-2.

FIGS. 3 and 4 are frame diagrams of the terminal data signals a-1 and a-2. All terminal data signals are composed of data signals. For convenience of processing in the data separation unit 6 and the data assembling unit 10, 384 Kbps is set to 8
Divided by 64 Kbps in bit units (TS1 to TS
6) Each TS is divided into 80 octets.

FIGS. 5 and 6 show line signals d-1 to d-12.
FIG. 2 is a diagram illustrating a frame configuration of D _{1 to} D ₃₇₂₀ are data signals, FAS is a flag signal added by the flag insertion unit, and BAS is a control signal between multiplexing / demultiplexing devices. As shown in the figure, although the transmission data amount is reduced by the insertion of 48 bits of the FAS signal and 48 bits of the BAS signal, 96 bits are transmitted by the following D channel packet signal.

FIG. 7 is a diagram showing the frame structure of the D channel signals f-1 to f-6. In the D channel, the line signal FA
Since the data corresponding to 96 bits of S and BAS is divided into three lines and transmitted, the data amount per line is 3
It is 2 bits (4 octets). Further, in order to synchronize with the line signals shown in FIGS. 5 and 6, the FAS signal and the BAS signal are inserted into the D channel signal, and one frame is composed of a total of 48 bits and transmitted.

Next, the embodiment shown in FIG. 1 will be described in more detail.

FIG. 8 shows the data separating section 6 in the separating section 3.
FIG. 9 is a time chart showing the operation. The data separating section 6 sequentially increments the address value by the counter 14-1, and stores the frame structure of the line signal shown in FIGS. 5 and 6 in advance in the ROM 13-1.
Output the flag signals c-1 to c-6 and the separation signal g. The decoder 12 receives the separation signal g, and sequentially outputs the selection signals h-1 to h-7 ('L') to the OR circuits 15-1 to 15-7 as shown in FIG. Therefore, the terminal data signal a-1 is selected by the selection signals h-1 to h-7 and separated into the data signals b-1 to b-6 and b-13.

FIG. 10 is a block diagram showing a detailed configuration of the flag insertion unit. The selector 16-1 outputs the flag signal c
, The BAS signal i (i ₋₁ , i ₋₂ ),
Alternatively, one of the FAS signals is selected, and the line signal d is generated. However, the FAS signal is represented by “H” or “L”.

The BAS selection signal j is generated by the counter 14-2 and the ROM 13-2, and is input to the selectors 16-2 and 16-3. Selectors 16-2 and 16-3
Converts the BAS signal i to the selector 16 according to the selection signal j.
Output to -1. The reason why the BAS signal i is divided into i _-1 and i _-2 is that the content of the signal differs between the even frame and the odd frame according to the recommendation of CCITT H221.

FIG. 11 is a block diagram showing the detailed configuration of the flag detecting section 9, and FIG. 12 is a time chart showing the operation thereof. The line signal d is converted into FAS signals k-1 to k-8 each shifted by 8 bits by an 8-bit shift register 17 to which input / output terminals are connected as shown.
-7 is output to the ROM 13-3. Such an 8-bit shift is performed because the FAS signal is present in the last bit of each octet of the line signal d as shown in FIGS. As a result, as shown in FIG.
The timing at which the FAS signals are input to M13-3 together can be obtained. At this time, the ROM 13-3 adjusts so that the SC bit signal 1 is output from the counter 14-3. The details are described in JP-B-59-4903 (frame synchronization circuit). The ROM 13-4 outputs a flag signal c and a data selection signal n according to the output of the counter 14-3. The OR circuit 15-8 receives the data selection signal n and extracts only the data signal b from the line signal d. The D flip-flop 18 outputs a synchronization alarm signal m.

FIG. 13 shows the data assembling unit 1 in this embodiment.
FIG. 14 is a block diagram showing the configuration of a 0, and FIG. 14 is a time chart showing the operation thereof. The data signals b-7 to b-12 and b-14 are converted into FIFOs 19-1 to 19-1 according to the flag signals c-7 to c-12 and the data selection signals n-7 to n-12.
Input to 9-7 respectively. In accordance with the counter 14-4, the ROM 13-5 outputs an assembly timing signal o, a missing tooth selection signal q, and missing tooth enable signals r-1 to r-7, respectively. According to the assembly timing signal o and the omission enable signals r-1 to r-7, the FIFO 19-
The missing data signals p-1 to p-7 are output from 1 to 19-7 to the selector 16-4, and are selected according to the missing selection signal q to generate the terminal data signal a-2.

FIG. 15 is a block diagram showing the detailed configuration of the layer 3 control unit 11, and FIG. 16 is a packet signal configuration diagram of the D channel signal f shown in FIG.

First, in the demultiplexing unit 3-1 on the transmitting side,
The data signal b-13 is supplied to a serial / parallel converter (S
/ P) 20 converts the signal into an 8-bit parallel signal, and the parallel input / output unit (PI
O) 22 and a D-channel input / output unit (LAP-D) 24 to output to the network-side INF 8 as a D-channel signal f.

Conversely, in the multiplexing section 2-1 on the receiving side, the D-channel signal f input from the network-side INF 8 passes through the D-channel input / output section 24 and the PIO 22, and is converted into a parallel / serial converter (P / S) 21 converts the 8-bit parallel signal into a data signal b-14.
Output to

[0030]

As described above in detail, the data transmission system according to the present invention transmits a high bit rate data signal by using the B channel signal and the D channel signal of a plurality of ISDN lines. Furthermore, by treating the control signal added to the B channel signal and the D channel signal equally, the transmission rate of the high bit rate
It is possible to make the level equal to the sum of the transmission speeds of the B channels of the DN line, and it is possible to prevent a reduction in the transmission speed of the data signal to be transmitted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a demultiplexing unit in an embodiment of a data transmission system according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a multiplexing unit according to the present embodiment.

FIG. 3 is a frame configuration diagram of terminal data signals a-1 and a-2.

FIG. 4 is a diagram illustrating a frame configuration of terminal data signals a-1 and a-2.

FIG. 5 is a frame configuration diagram of line signals d-1 to d-12.

FIG. 6 is a diagram illustrating a frame configuration of line signals d-1 to d-12.

FIG. 7 is a frame configuration diagram of D channel signals f-1 to f-6.

FIG. 8 is a detailed circuit diagram of the data separation unit 6 in the separation unit 3.

FIG. 9 is a time chart illustrating an operation of the data separation unit 6 of FIG. 8;

FIG. 10 is a block diagram illustrating a detailed configuration of a flag insertion unit.

FIG. 11 is a block diagram illustrating a detailed configuration of a flag detection unit 9;

FIG. 12 is a time chart illustrating an operation of the flag detection unit in FIG. 11;

FIG. 13 is a block diagram illustrating a configuration of a data assembling unit 10 according to the present embodiment.

FIG. 14 is a time chart showing an operation of the data assembling unit in FIG. 13;

FIG. 15 is a block diagram showing a detailed configuration of a layer 3 control unit 11.

FIG. 16 is a diagram illustrating a packet signal configuration of a D-channel signal f illustrated in FIG. 7;

FIG. 17 is a configuration diagram of a conventional data transmission system using a plurality of ISDN lines.

FIG. 18 is a diagram illustrating a frame configuration of a line signal d used in a conventional system.

[Explanation of symbols]

 1-1 Multiplexing / demultiplexing device 2-1 Multiplexing unit 2-2 Multiplexing unit 3-1 Demultiplexing unit 3-2 Demultiplexing unit 4-1 Terminal 4-2 Terminal 5 ISDN line 6 Data demultiplexing unit 7-1 ７7-6 Flag insertion unit 8-1 to 8-6 Network side INF unit 9-1 to 9-6 Flag detection unit 10 Data assembling unit 11-1 Layer 3 control unit 11-2 Layer 3 control unit a-1 Terminal Data signal a-2 Terminal data signal b-1 to b-14 Data signal c-1 to c-12 Flag signal d-1 to d-12 Line signal e-1 to e-4 Network side signal f-1 to f -6 D channel signal

Claims (4)

(57) [Claims] 1. A system for transmitting a high bit rate data signal generated by one transmitting terminal to a receiving terminal using a plurality of ISDN lines, wherein the transmitting terminal transmits the data signal to the plurality of ISDN lines. Data separating means for separating a first channel signal corresponding to a B channel and a second channel signal corresponding to a D channel of the plurality of ISDN lines; control signal inserting means for adding a control signal to each of the first channel signals And transmitting means for transmitting the first channel transmission signal to which the control signal is added and the second channel signal through the plurality of ISDN lines, respectively, wherein the receiving terminal comprises: Receiving means for receiving a channel transmission signal and the second channel signal; Control signal detecting means for detecting a control signal; and data assembling means for assembling the received first channel signal and the received second channel signal based on the control signal and outputting the data signal. A data transmission system characterized by the following. 2. A system for transmitting a high bit rate data signal generated by one terminal to another terminal using a plurality of ISDN lines, wherein the data signal corresponds to each B channel of the plurality of ISDN lines. The plurality of first data signals and the plurality of ISDNs
Data separating means for separating the data signal into a plurality of second data signals corresponding to each D channel of the line; control signal inserting means for adding a control signal to each of the first data signals; One data signal is
Transmitting means for transmitting the N data through the B channel and transmitting the second data signal in packets through the D channel; and receiving the first data signal and the second data signal to which the control signal is added from the plurality of ISDN lines. Receiving means for receiving the control signal, control signal detecting means for detecting the control signal from the first data signal to which the control signal is added, and the first data signal and the second signal based on the control signal.
Data assembling means for assembling a data signal and outputting the data signal. 3. The transmission rate of said data signal is equal to said plurality I
3. The data transmission system according to claim 2, wherein the sum is equal to the sum of the transmission speeds of the B channels of the SDN line. 4. The data transmission system according to claim 1, wherein said control signal includes a flag signal.