JP2614123B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a TSL system capable of obtaining a smear-free image by reading a pixel signal through a signal read line wired in a horizontal scanning direction. The present invention relates to a solid-state imaging device.

[Conventional technology]

Conventionally, as a very common MOS type solid-state imaging device, a configuration shown in FIG. 5 is known.

That is, the solid-state imaging device is formed by a semiconductor manufacturing process, and includes a light receiving region 1 for receiving an optical image of a subject, a vertical scanning circuit 2 for scanning and reading out pixel signals, and a horizontal scanning circuit 3. ing.

The light receiving area 1, a plurality of photodiodes P ₁₁ to P
_nm (where n is the order of the rows and m is the order of the columns) are formed in a matrix and are formed between the photodiodes P _{11 to} P _{nm by} a vertical scan comprising a shift register. a vertical selection gate line L ₁ ~L _n that extends from each bit output contact b ₁ ~b _n circuit 2, the signal read line l ₁ to l _m are wired so as to intersect vertically and horizontally.

Also, as shown, between the photodiode P ₁₁ to P _nm and the signal read line l ₁ to l _m, the switching transistor M ₁₁ ~M _nm consisting of MOS-type FET is formed, the vertical selection gate line
According vertical scanning signal supplied from the vertical scanning circuit 2 through L ₁ ~L _n, by switching transistor M ₁₁ ~M _nm is turned on and off, the photodiode P ₁₁ to P
_nm pixel signals sequentially for each row to the signal read line l ₁ to l _m of transfers.

Furthermore, the end of each signal readout line l ₁ to l _m, together via a switching transistor N ₁ to N _m consisting of MOS-type FET according to the horizontal scanning connected to the output line 4, each bit output of the horizontal scanning circuit 3 horizontal selection gate lines a _1, which is extended from the contact h ₁ to h _m
~a _m is connected to the gate contact of the switching transistor N ₁ to N _m, in accordance with the horizontal scanning signal supplied from the horizontal scanning circuit 3 through these horizontal selection gate line a ₁ ~a _m, the switching transistor N ₁ by to n _m are turned on and off, to transfer pixel signals present in the signal read line l ₁ to l _m sequentially to the output line 4, the pixel signal from the output terminal 5 S (n,
m) in time series.

As described above, the photodiodes P _{11 to} P _nm
The vertical scanning circuit 2 and the horizontal scanning circuit 3 read and scan the pixel signals generated in the above at a predetermined timing so that all the pixel signals can be read.

However, in the MOS solid-state imaging device having such a configuration, the vertical scanning circuit 2 performs vertical scanning every predetermined horizontal scanning period, and within each horizontal scanning period, the horizontal scanning circuit 3 performs point-sequential horizontal scanning. since performing, signal output lines l ₁ to l _m each become to be scanned in a single timing for each horizontal scanning period of respective result, during the waiting period until the next scan reading is performed , the noise component is superimposed on the signal read line l ₁ to l _m, causing smear.

In order to prevent the occurrence of such smear, a MOS solid-state imaging device having a configuration as shown in FIG. 6 has been developed. This is a TSL (Transversal Signal Line) MO
An S-type solid-state image pickup device differs from the previous solid Sai image device shown in Fig. 5, two series of the switching transistor for each of the photodiodes P ₁₁ to P _nm connects to the photodiode When the switching transistor on the near side is vertically scanned by the vertical scanning circuit 2 and the other switching transistor is horizontally scanned by the horizontal scanning circuit 2, when both switching transistors are both turned on, the pixel signal of the photodiode corresponding to them is obtained. In that it is read out via a signal readout line extending in the horizontal direction.

Incidentally, L ₁ ~L _n is vertical select gate lines in FIG., L ₁ to l _n is the signal read line, a ₁ ~a _m horizontal select gate lines, Q ₁ to Q _n is the signal read line l ₁ to l _A switching transistor which is interposed between _n and the output line 4 and is sequentially turned on in synchronization with a vertical scanning signal transferred from the vertical scanning circuit 2 via the vertical selection gate lines l _{1 to} L _n .

That is, when described as a representative structure in accordance with one of the elements E, connecting two switching transistors f and g between the photodiode M ₁₁ and the signal read line l ₁ is in series, the gate of one of the switching transistors f vertical select gate line L ₁ is connected to the contact, a horizontal selection gate line a ₁ is connected to the gate contact of the other switching transistor g. Then, while turning on the switching transistor f and Q ₁ by the vertical scanning circuit 2 outputs a vertical scanning signal, the switching transistor by turning on the g, pixel signals a signal read line l of the photodiode M _{11 1} and read out to the output terminal 5 via the output line 4.

Then, transfer the vertical scanning signal for every predetermined horizontal scanning period from the bit output contact b ₁ ~b _n of the vertical scanning circuit 2 to the vertical select gate line L ₁ ~L _n, the horizontal scanning circuit in the period of the respective 3 a horizontal scanning signal from the respective bit output contact h ₁ to h _m by sequentially transferred to the horizontal selection gate line a ₁ ~a _m, it is possible to read out all pixel signals in time series of the.

According to such a solid-state imaging device of the TSL system, each pixel signal is output via a signal readout line in synchronization with a dot-sequential scanning cycle by horizontal scanning, so that the solid-state imaging device having the configuration shown in FIG. Compared with the image pickup apparatus, the period in which the noise charge is mixed into the signal readout line is shortened, so that there is an effect that the occurrence of smear is greatly reduced.

FIG. 7 shows a partial structure of a light receiving area of the TSL type solid-state imaging device shown in FIG. That is, a part of a layout when manufactured by a semiconductor manufacturing process, that is, a planar configuration of nine pixels is shown as an example.

In the figure, a portion M is an n ^{+ -type} impurity region buried in a surface region of a P-well layer formed in a semiconductor substrate, and each constitutes a photodiode corresponding to a pixel.

Further, one end of each n ^{+ -type} impurity region is extended in an L-shape, and the L-shaped end portion is contacted. Readout line consisting of a first aluminum layer through
l _i , l _{i + 1} , l _{i + 2} (indicated by a dashed line in the figure). The signal read lines l _i , l _{i + l} , l _{i + 2} are formed so as to run in the lateral direction between the n ^{+ -type} impurity regions constituting the respective pixels, and the switching transistor shown in FIG. Output line 4 via a predetermined switching transistor among Q _{1 to} Q _n
Connect to

Also, vertical selection gate lines L _i , L _{i + 1} , L _i made of a polysilicon layer (indicated by solid lines in the figure) adjacent to the signal read lines l _i , l _{i + 1} , l _{i + 2} . ₊₂ are stacked, and a polysilicon layer extending from a side end of each of the vertical selection gate lines L _i , L _{i + 1} , L _{i + 2} is formed.
n ⁺ -type covers the upper surface of the L-shaped portion of the impurity region, and f in the switching transistor (diagram MOS type FET according to the vertical scanning by performing ion implantation into the n ⁺ -type impurity region in the vicinity of the covered portion ) Are formed.
The vertical selection gate lines _Li , _{Li + 1} , and _{Li + 2} are connected to predetermined bit output contacts of the vertical scanning circuit 2 in FIG.

Further, horizontal select gate lines a _j , a _{j + 1} , a _j made of a second aluminum layer (indicated by a dotted line in the figure) running in the vertical direction between the n ^{+ -type} impurity regions constituting each pixel. ₊₂ are formed, and at the side ends of the respective horizontal select gate lines a _j , a _{j + 1} , a _{j + 2} ,
A gate portion (indicated by F in the drawing) made of a polysilicon layer covering the other upper surface of the L-shaped portion of each n ^{+ -type} impurity region is contacted. Connected through. Then, ion implantation is performed on the n ^{+ -type} impurity region in the vicinity of the portion covered with the gate contact, so that a MOS-type FET for horizontal scanning (indicated by g in the figure)
Are formed. Here, the horizontal selection gate lines a _j , a _{j + 1} ,
a _{j + 2} is connected to a predetermined bit output contact of the horizontal scanning circuit 3 in FIG.

The first and second aluminum layers and the polysilicon layer are
Formed according to each separate mask,
Further, they are laminated so as to be insulated from each other via a silicon oxide film layer.

In such a structure, the vertical scanning and the horizontal scanning by the above-described vertical scanning circuit 2 and horizontal scanning circuit 3 are performed, and the switching transistors f and g are sequentially turned on at a predetermined timing, thereby generating a voltage at each photodiode. Pixel signals can be read out in time series.

[Problem to be Solved by the Invention] However, such a conventional TSL type solid-state imaging device has a problem that a dynamic range of a saturated exposure amount cannot be sufficiently obtained. That is, in such a solid-state imaging device in which pixel signals (charges) integrated in a photodiode are read out via a signal readout line, if the charge capacity of the signal readout line is not sufficient, unread pixel signals may occur. Therefore, the magnitude of the charge capacity of the signal readout line determines the magnitude of the dynamic range. However, the charge capacity of the conventional signal read line is the signal read line l _i , l shown in FIG.
_{As shown in i + 1} and l _{i + 2} , it is determined by the pseudo capacitor existing between the aluminum layer forming them and the semiconductor substrate. And a silicon oxide layer for insulating the semiconductor substrate from the semiconductor substrate. And since such a silicon oxide film layer is formed thick, there arises a problem that the charging capacity is reduced and the dynamic range is not increased. In particular, as the number of switching transistors formed between the photodiodes constituting the pixels and the signal readout lines increases, in other words, the charging capacity of the signal readout lines increases as the number of pixels increases. However, it is difficult to take measures such as increasing the width of the signal readout line due to the high integration accompanying the increase in the number of pixels, and the dynamic range cannot be increased. On the other hand, if the width of the signal readout line is increased to increase the dynamic range, problems such as a decrease in aperture ratio and a decrease in sensitivity occur.

Further, since the structure requires a total of three layers of two aluminum layers and one polysilicon layer to form the vertical and horizontal gate lines and the signal read lines, the number of manufacturing processes increases. As a result, there have been problems such as a decrease in yield and an increase in manufacturing cost.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a solid-state imaging device capable of reducing the number of steps in a manufacturing process and improving a dynamic range.

[Means for solving the problem]

First, according to the present invention, a plurality of photodiodes forming a pixel group are arranged in a matrix and formed, and a vertical selection gate line extending from a vertical scanning circuit and a horizontal selection gate extending from a horizontal scanning circuit are provided. And a signal readout line between the respective photodiodes, and between each photodiode and a predetermined signal readout line, a vertical scan signal transferred from a vertical scan circuit via a vertical select gate line. Forming a first switching transistor that turns on and off in synchronization with the first switching transistor and a second switching transistor that turns on and off in synchronization with a horizontal scanning signal transferred from the horizontal scanning circuit via a horizontal selection gate line; Thus, the pixel signals of the photodiodes are read out in synchronization with the signal readout scan at a predetermined timing by the vertical scanning circuit and the horizontal scanning circuit. Target solid-state imaging device of the TSL scheme.

In order to achieve the object of the present invention for such a solid-state imaging device, a protrusion formed of the same impurity layer as the photodiode is formed at one end of each of the photodiodes. The first switching transistors are formed by arranging the vertical selection gate lines made of a polysilicon layer so as to cross over the upper surfaces, and the gate portions made of a polysilicon layer are stacked on the other upper surfaces of the respective projecting portions. By forming the second switching transistor, a conductor such as an aluminum layer or the like is laminated by insulating between the gate portions of the gate portions arranged in the vertical direction above the polysilicon layer. The horizontal selection gate line is formed by connecting to the wiring composed of layers, and the conductor layer formed by the same process as described above is used. And forming the signal read line, and a structure to be laminated so as to overlap the upper surface of the vertical select gate line via an insulating film made of a signal reading line each from silicon oxide film.

[Action]

According to the present invention having such a structure, the vertical and horizontal selection gate lines and the signal readout lines can be formed with only one conductor layer and one polysilicon layer in total. Can also reduce the number of conductor layers, so that
The manufacturing process is simplified.

Furthermore, the charge capacity of the signal readout line is determined by a pseudo capacitor formed between the insulating layer and the vertical select gate line formed below the insulating layer. In this case, the insulating layer is formed by a semiconductor manufacturing process. According to the experiments of the inventor of the present application, during manufacturing, since it is formed to be thinner than the insulating layer laminated on the semiconductor substrate described in the conventional example, a larger charging capacity can be realized as compared with the conventional example. In the structure of the conventional example and the structure of the present invention, as a result of measuring the charging capacity while making the width of the signal readout line equal, an improvement of about 30% was recognized, and at the same time, the effect of increasing the dynamic range was obtained.

〔Example〕

An embodiment of a TSL type solid-state imaging device according to the present invention will be described below with reference to the drawings.

First, the overall circuit configuration will be described with reference to FIG.
In FIG. 1, reference numeral 2 denotes a vertical scanning circuit comprising a shift register, and 3 denotes a horizontal scanning circuit comprising a shift register. In the light receiving area, a structure similar to the element E in FIG. 5, that is, a plurality of elements E '(shown in a dotted line in FIG. 1) composed of a photodiode and a pair of switching transistors connected in series thereto is shown. The elements E 'are arranged in a matrix in the vertical and horizontal directions.
, A vertical selection gate line is connected to the gate contact of a switching transistor (indicated by f in the figure) on the side close to the photodiode, and horizontal scanning is performed on the gate contact of the switching transistor (indicated by g in the figure) on the other side horizontal selection gate line which is extended from each bit output contact h ₁ to h _m circuit 3
a ₁ ~a _m is connected.

In this embodiment, eight output lines R _{1 to} R ₈ are provided, and _eight output lines R _{1 to} R ₈ are provided for each bit output contact of the vertical scanning circuit 2.
By arranging the vertical gate lines so as to correspond to each other, the configuration is such that the pixel signals of eight vertical rows are read out in parallel in synchronization with the horizontal scanning signal from the horizontal scanning circuit 3. since 8 × m pieces of photodiode cells CE of the group, such is formed corresponding to all the bits output contact b ₁ ~b _n, for convenience of explanation, the bit output contact b ₁ of the vertical scanning circuit 2 The configuration of such a cell CE will be described as a representative.

First, L _1b1 ~L _8b1 is 8 rows of photodiodes wired in correspondence to the vertical select gate line, l _1b1 to l _8b1 is a signal readout line, signal readout line l _1b1 to l _8b1 are switching transients Sita are connected to the respective output lines R ₁ to R ₈ through Q ₁₁ to Q _18.

Vertical select gate line L _1b1 ~L _8b1 is configured to connect to the gate contact and gate contact of the switching transistor Q ₁₁ to Q ₁₈ of a given switching transistor in each element E ', as described above, further, the vertical selection of the respective The gate lines L _{1b1 to} L _8b1 are switching transistors K _1a , K _2a , K _3a , K _4a , K _5a , K which are turned on / off by a vertical scanning signal from a bit output contact b ₁ of the vertical scanning circuit 2. _6a , K _7a , K
Switching transistor K _1b , K _2b , K _3b , K _4b , K _5b , K _6b , K _7b , which is connected to terminal VA through _8a and is turned on / off by a reset signal applied to terminal R , K _8b to the terminal VE.

Then, similar cell CE is formed corresponding for other bit output contacts b ₂ ~b _n of the vertical scanning circuit 2, each of the other cell signal read line group of even eight output lines R ₁ to R ₈ is connected in parallel.

Next, the reading scan of the pixel signal will be described with reference to the timing chart of FIG. The symbols in FIG. 2 indicate the waveforms at each terminal in the circuit.

First, a DC voltage of, for example, 5 volts is applied to the terminal VA, and the terminal VE is set to, for example, 0 volt. When applying the "H" level of the reset signal to the terminal R, all the vertical selection gate line is reset to 0 volts, the "H" level from the bit output contact b ₁ ~b _n of the vertical scanning circuit 2 vertical The voltage of the vertical selection gate line becomes the voltage of the terminal VA in synchronization with the scanning signal.

Then, receiving the object optical image into an appropriate period after the reset operation tau, then, a predetermined period of time T _1, when the first vertical scanning signal is outputted from the bit output contact b _1, the first cell CE
The switching transistor Q ₁₁ to Q _18, which is provided to the switching transistor and an output terminal connected to the vertical gate line L _1b1 ~L _8b1 are turned on according to. Then, while these switching transistors is turned on, by sequentially horizontal scanning signal at a predetermined cycle from each bit output contact h ₁ to h _m of the horizontal scanning circuit 3 outputs pixel signals every 8 rows Read in parallel. That is, the horizontal scanning signal from the bit output contact h _1, the first eight of the columns of the pixel signals S ₁ to S ₈ First, then, by a horizontal scanning signal from the bit output contact h _2, in the second column 8 Pixel signals S _{1 to} S ₈ ,
Further then, the horizontal scanning signal from the bit output contact h _3, and so on eight pixel signals S ₁ to S ₈ in the third column, by parallel pixel signals are read out, one horizontal 8 × m pixel signals are read out during the scanning period.

Then, the vertical scanning signal every vertical scanning period T ₂ through T _n from the bit output contact b ₂ ~b _n residual is outputted, by performing the same horizontal scanning in the vertical scanning period T ₂ through T _n each, Similarly, eight pixel signals are read out in parallel from the remaining cells.

As described above, in this embodiment, a plurality of pixel signals are read in parallel in horizontal scanning, so that high-speed signal reading is possible.

Next, the actual structure of the light receiving region will be described with reference to FIG. FIG. 3 is an enlarged plan view showing a part of the light receiving region.

In FIG. 3, a portion M is an n ^{+ -type} impurity region buried in a surface region of a P well layer formed in a semiconductor substrate, and each constitutes a photodiode corresponding to a pixel.

Further, one end of each n ^{+ -type} impurity region is formed so as to protrude (hereinafter, referred to as a protruding portion), and between each n ^{+ -type} impurity region, a polysilicon layer (shown by a dotted line in the figure) is provided. Vertical select gate line is formed. Each of the vertical select gate lines is formed by laminating a polysilicon layer via a gate oxide film on the upper surface of the projecting portion of the n ^{+ -type} impurity region arranged in the horizontal direction, as shown in FIG. By performing ion implantation, a first switching transistor (indicated by f in the figure) related to vertical scanning is formed.

Further, a substantially U-shaped gate portion (indicated by G in the figure) made of a polysilicon layer is laminated on the gate oxide film so as to cross the upper surfaces of the protrusions of the respective photodiodes. By performing ion implantation on the protruding portions of the respective stacked portions, a third switching transistor (indicated by g in the figure) for horizontal scanning is formed.

Then, both ends of these gate portions are sequentially connected by an aluminum layer (indicated by Al in the figure) extending in the vertical direction (the connection is made by Are performed by the contacts shown in FIG. 3), and the wiring by each connection becomes a horizontal selection gate line and is connected to each bit output contact of the horizontal scanning circuit 3.

In addition, the ends of the protrusions of each photodiode are contact , A signal readout line made of an aluminum layer (in the figure,
(Indicated by a dashed line). More specifically, each signal read line is stacked so as to overlap the upper surface of the vertical select gate line wired between the n ^{+ -type} impurity regions, and is connected to the aluminum layer Al serving as the horizontal select gate line. In order to avoid contact, cross the upper side of the gate portion G and contact It is formed so as to pass through the gap between the photodiodes, and further, is formed in a shape that covers the upper surface thereof in accordance with the shape of the protrusion of each photodiode.

The aluminum layer and the polysilicon layer are insulated from each other by a silicon oxide film layer as shown in FIG. 4, and in the manufacturing process, an aluminum layer for forming a horizontal selection gate line and a signal readout are formed. An aluminum layer for forming a line is formed simultaneously according to the same mask pattern, and a polysilicon layer for forming a gate portion G and a polysilicon layer for forming a vertical selection gate line are simultaneously formed according to the same mask pattern. As a result, these wirings are formed from one aluminum layer and one polysilicon layer.

As described above, according to this embodiment, since the semiconductor device is formed by a smaller number of manufacturing processes than in the related art, the yield can be improved. In addition, the signal readout line and the vertical select gate line are laminated to form a structure in which a pseudo capacitor is formed, and the silicon oxide film layer between them is thinner, so that compared with the conventional structure. As a result, the charging capacity can be increased, and the dynamic range can be improved.

Note that the vertical selection gate line is always kept at a constant voltage even when horizontal scanning is performed by a horizontal scanning signal from a horizontal scanning circuit during a horizontal scanning period, so that the potential of the vertical selection gate line does not fluctuate. The DC potential of the signal readout line is stably maintained. This means that the charging voltage of the signal readout line is constant and stable, and an effect that the pixel signal can be read out with high accuracy can be obtained.

〔The invention's effect〕

As described above, according to the present invention, a horizontal select gate line, a single conductive layer and a single polysilicon layer are used.
Since a vertical selection gate line, a signal readout line, a switching transistor for vertical scanning, and a switching transistor for horizontal scanning can be formed, the manufacturing process can be simplified and the yield can be improved.

Further, since the vertical selection gate line and the signal read line are stacked so as to overlap each other, the effect of increasing the charge capacity and improving the dynamic range can be obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of a solid-state imaging device of the TSL system according to the present invention, FIG. 2 is a timing chart for explaining the operation principle of the embodiment, and FIG. 4 is a partial plan view for explaining the structure of the light receiving region of FIG. 4, FIG. 4 is a cross-sectional view showing a vertical cross-sectional structure taken along line XX in FIG. 3, and FIG. FIG. 6 is an explanatory view of the structure of another conventional example showing the structure of another conventional example. FIG. 7 is a partial plan view for explaining the structure of the light receiving region in the conventional example of FIG. Reference numerals: 2; the vertical scanning circuit 3; horizontal scanning circuit CE; cell E '; element L _1b1 ~L _8b1; vertical select gate line l _1b1 to l _8b1; signal read line a ₁ ~a _m; horizontal selection gate line R ₁ to R _8; output line Q ₁₁ to Q _18; forming a horizontal gate lines; switching transistor f; gate portion Al; region G of the photodiode; switching transistor M of the horizontal scanning; switching transistor g of the vertical scan Aluminum layer for

Claims (1)

(57) [Claims] A plurality of photodiodes forming a pixel group are arranged in a matrix and formed, and a vertical selection gate line extending from a vertical scanning circuit and a horizontal selection gate line extending from a horizontal scanning circuit. And a signal readout line between each photodiode, and between each photodiode and a predetermined signal readout line, synchronized with a vertical scan signal transmitted from a vertical scan circuit via a vertical select gate line. Forming a first switching transistor that performs an on / off operation and a second switching transistor that performs an on / off operation in synchronization with a horizontal scanning signal transmitted from a horizontal scanning circuit via a horizontal selection gate line. A pixel signal of the photodiode is read out in synchronization with a signal readout scan at a predetermined timing by the vertical scanning circuit and the horizontal scanning circuit. In the solid-state imaging device, a protrusion formed of the same impurity layer as that of the photodiode is formed at one end of each of the photodiodes, and the vertical selection is made of a polysilicon layer so as to cross an upper surface of each of the protrusions. By wiring the gate line,
The second switching transistor is formed by forming the first switching transistor, and laminating a gate portion made of a polysilicon layer on the other upper surface of each protrusion, and forming the second switching transistor. The horizontal selection gate lines are formed by connecting between the gate portions arranged in the vertical direction to a wiring made of a conductor layer such as an aluminum layer that is insulated and laminated above the polysilicon layer, and the same as above. The signal read lines are formed by a conductor layer formed in a process, and the respective signal read lines are stacked so as to overlap the upper surface of the vertical select gate line via an insulating layer made of a silicon oxide film. Solid-state imaging device.