JP2614020B2 - Semiconductor wafer integration method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for integrating semiconductor wafers, and more particularly to a method for integrating a plurality of lots using an orientation flat (hereinafter, referred to as an orientation flat).

[0002]

2. Description of the Related Art An orientation flat is provided on the outer periphery of a semiconductor wafer in order to facilitate determination of crystal orientation and the like and alignment.

[0003] When a group of semiconductor wafers in a carrier is transferred to another carrier, for example, a boat for processing, the orientation flats are aligned in the same direction and placed on the boat. Such a transfer device in which the orientation flats are aligned is disclosed in, for example, JP-A-57-187948.

[0004]

However, in the prior art, these semiconductor wafers are transferred from a plurality of small first carriers each containing a group of semiconductor wafers to another large second carrier, and are unified. At this time, the orientation flats of all the semiconductor wafers are placed in the same direction. Therefore, after the predetermined processing is completed on the second carrier, when the semiconductor wafer is transferred from the large second carrier to the plurality of small first carriers and separated, the semiconductor wafer returns to the original small first carriers. Not only that, the lot management of the first carrier unit of the semiconductor wafer is hindered.

The above prior art will be described with reference to FIGS.

First, in FIG. 5, a small first carrier 1
0 are prepared. The semiconductor wafers A-1, A-2, and A-3 are arranged and stored in the lot A with the orientation flat 3 aligned downward in A, and the orientation flat 3 is aligned in the bottom direction B in the semiconductor wafer B-. 1, B-2, B-3, B-
4, B-5, and B-6 are arranged and stored to form a lot 22, and the orientation flat 3 is aligned downward at C, and the semiconductor wafer C-
1, lots C-2, C-3 are arranged and stored.

Next, these semiconductor wafers are accommodated in one large second carrier 20 in the order of first carriers A → B → C. In the prior art, as shown in FIG. 6, twelve semiconductor wafers A-1, A-2, A-3, B-1, B-2, B
-3, B-4, B-5, B-6, C-1, C-2, C-
The three orientation flats 3 are all arranged in the same direction (downward).

After performing predetermined processing on the large second carrier 20, when transferring to the original small first carriers A, B and C, the first small first carriers A and B are already used.
The lot configuration of the semiconductor wafers in B and C is unknown due to the arrangement of the second carriers 20. Therefore, even if the semiconductor wafers are arranged in the storing order as shown in FIG. 6 on the large second carrier, for example, the number of the semiconductor wafers is counted and each of the small first carriers 1 is equally distributed four by four.
0 (A, B, C).

As a result, as shown in FIG. 7, the orientation flat 3 is aligned downward on the first carrier A and the semiconductor wafer A-
Lots 1, 1, A-2, A-3, B-1 are arranged and stored.
The semiconductor wafers B-2, B-3, B-4, and B-5 are arranged and accommodated in the first carrier B with the orientation flats 3 arranged in a downward direction to form a lot 32. In C, the orientation flats 3 are aligned downward, and the semiconductor wafers B-6, C
-1, C-2 and C-3 are arranged and stored to form a lot 33.

First, the semiconductor wafers A-1, A-2, A- of the lot 21 stored in the first carrier (10) A
3 and the semiconductor wafers B-1, B-2, B-3, B-4, and B of the lot 22 stored in the first carrier (10) B.
B-5, B-6, and the semiconductor wafers C-1, C-2, C-of the lot 23 stored in the first carrier (10) C.
3 has different histories, it is necessary to perform lot management separately for each lot group, but in the above-described conventional method, after integrating and performing predetermined processing, the original first carrier After separation into A-1, A-2,
Lot 31, B-2, B-3, A-3, B-1
Lot 32 consisting of B-4 and B-5, B-6, C-1,
Since the lot 33 composed of C-2 and C-3 is formed and the groups constituting the lot are rearranged, the lot management of the semiconductor wafer in the first carrier unit becomes impossible.

On the other hand, it is not efficient to assign a lot number to each semiconductor wafer, confirm the lot number of each semiconductor wafer every integration-separation, and perform the transfer operation.

Accordingly, an object of the present invention is to integrate the transfer of semiconductor wafers from a plurality of first carriers each accommodating a group of semiconductor wafers to one second carrier, and from the second carrier to a plurality of first carriers. It is an object of the present invention to provide a method of integrating semiconductor wafers, which makes it easy to manage lots for each first carrier even if separation for transferring semiconductor wafers is performed.

[0013]

SUMMARY OF THE INVENTION A feature of the present invention is that a semiconductor wafer housed in a plurality of first carriers is converted into a single second wafer.
When integratedly housed in a carrier, the orientation flats of semiconductor wafers constituting a first lot in the first first carrier are aligned in a first direction and arranged on the second carrier, and the second The orientation flats of the semiconductor wafers constituting the second lot in the first carrier are aligned in a second direction different from the first direction and are accommodated in the first first carrier. Which of the plurality of first carriers is contained in the arrangement of the semiconductor wafers in the second carrier in the arrangement of the semiconductor wafers in the second carrier following the arrangement of the semiconductor wafers. In the direction of the orientation flat in a semiconductor wafer integration method. Here, the orientation flat of the semiconductor wafer constituting the third lot in the third first carrier is aligned in the first direction, and the semiconductor accommodated in the second first carrier is aligned. The orientation of the orientation flat of the semiconductor wafer in the odd-numbered first carrier and the orientation of the orientation flat of the semiconductor wafer in the even-numbered first carrier are arranged in the second carrier following the arrangement of the wafers. May be alternately arranged on the second carrier. Generally, the direction opposite to the first direction is the second direction.
Further, by identifying the direction of the orientation flat in the array, the semiconductor wafer integrated with the second carrier is provided with a plurality of third carriers having the same lot configuration as the lot configuration in the first carrier before integration. It is preferable to store them separately. In this case, the first carrier and the third carrier can be the same carrier.

Here, the semiconductor wafers can be arranged in a plane. In this case, the first and second directions are one direction and the other direction in the planar shape. Alternatively, the semiconductor wafers may be vertically aligned with their main surfaces facing each other. In this case, the first and second directions are, for example, vertical upward and downward directions.

[0015]

According to the above method, on the second carrier, the arrangement of the semiconductor wafers stored in the first first carrier and the arrangement of the semiconductor wafers stored in the second first carrier are: Since it is possible to identify where the direction of the orientation flat switches, it is possible to return to the original first carrier after performing a predetermined process on the second carrier. Therefore, lot management of the semiconductor wafer for each first carrier is facilitated.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG.
4 to 4 are views showing an embodiment of the present invention.

First, in FIG. 1, a small first carrier 1
0 are prepared. The orientation flats 3 are aligned downward with the first carrier (10) A, and the semiconductor wafers A-1, A-2, A
-3 are arranged and accommodated to form a lot 11, and the orientation flats 3 are aligned upward with the first carrier (10) B so that the semiconductor wafers B-1, B-2, B-3, B-4 and B-5 are arranged. , B-6 are arranged and stored to form a lot 12, and the first carrier (1
0) The orientation flat 3 is aligned downward at C and the semiconductor wafer C-
1, lots C-2, C-3 are arranged and stored.

Next, as shown in FIG. 2, these semiconductor wafers are stored in one large second carrier 20 in the order of first carrier (10) A → B → C.

In this embodiment, the first carriers 10 are arranged on the second carrier 20 in the direction of the orientation flats 3 arranged on the respective carriers. That is, the first carrier (10) A
Semiconductor wafers A-1, A-2 and A-3 transferred from the first carrier (10) B are successively arranged on the second carrier 20 with the orientation flats 3 aligned downward. Semiconductor wafers B-1, B-2, B-3, B-4, B-
5, B-6 are arranged on the second carrier 20 with the orientation flat 3 aligned in the upward direction, and then the first carrier (10).
The semiconductor wafers C- 1, C- 2, and C- 3 transferred from C are arranged on the second carrier 20 with the orientation flats 3 aligned downward.

After subjecting the integrated twelve semiconductor wafers to predetermined processing on a large second carrier 20, the semiconductor wafers are transferred to a plurality of original first carriers A, B and C as shown in FIG. Separate migration. At this time, the carrier may be separated and transferred to another plurality of carriers (third carriers) A ', B', and C 'instead of the first carriers A, B, and C which are the same as the original carrier.

In any case, when the semiconductor wafers are transferred in order from the upper side in the drawing of the second carrier 20, the semiconductor wafer A- in which the orientation flats 3 are arranged in a downward direction is arranged.
Transfer to the first carrier A (or the third carrier A ') in order from 1 to A-3.

The next semiconductor wafer, ie, semiconductor wafer B
-1, the orientation of the orientation flat 3 is changed, and it can be recognized that the orientation flat is oriented upward. Therefore, the semiconductor wafers B-1 to B arranged such that the orientation of the orientation flat 3 is oriented upward from this semiconductor wafer B-1. -6 to the first carrier B (or the third carrier B ').

The next semiconductor wafer, ie, semiconductor wafer C
Since the orientation of the orientation flat 3 is changed and it can be identified that the orientation flat 3 faces downward, the semiconductor wafers C-1 to C in which the orientation of the orientation flat 3 is arranged downward from the semiconductor wafer C-1. -3 to the first carrier C (or the third carrier C ').

Therefore, after the separation, the semiconductor wafers A-1, A- are stored in the first carrier A (or the third carrier A ').
2 and A-3, the first carrier B (or the third carrier B ') contains semiconductor wafers B-1, B-
2, a lot is composed of B-3, B-4, B-5, and B-6, and the semiconductor wafers C-1, C-2, C- in the first carrier C (or the third carrier C '). 3, lots have the same lot configuration as the lots 11, 12, and 13 shown in FIG.

According to the present invention, in the integrated arrangement in the second carrier 20 shown in FIG. 2, the direction of the orientation flat 3 between adjacent lots is different for each lot as a semiconductor wafer group in the first carrier 10 before integration. is important. Therefore, the arrangement in each first carrier 10 before integration is not limited to that shown in FIG.
Instead, the semiconductor wafers may be arranged as shown in FIG. 2 by rotating the semiconductor wafers while gripping and transferring the semiconductor wafers. However, if the arrangement direction of the semiconductor wafers in each first carrier 10 is the same as the integrated arrangement direction in the second carrier 20 in FIG. 2 as shown in FIG. 1, the gripping / transporting operation is simplified and there is no direction error. Operation. Similarly, as shown in FIG. 3 in the separation arrangement, if the gripping transfer arrangement is performed while maintaining the arrangement direction of FIG. 2 as it is, the operation of the next integrated arrangement is smoothly performed.

Further, in the above embodiment, the case where semiconductor wafers are arranged in a plane on each carrier is exemplified. However, it is also possible to vertically align the carriers with the main surfaces of the semiconductor wafers facing each other. In this case, in the integrated arrangement shown in FIG. 2, the orientation flats 3 of the semiconductor wafer group of a certain lot are aligned vertically upward, and the orientation flats 3 of the semiconductor wafer group of the adjacent lot are aligned vertically downward.

FIG. 4 is a schematic diagram exemplifying the operation of shifting to the integration of FIGS. 1 and 2 and the operation of shifting to the separation of FIGS. 2 and 3.

When integrating the semiconductor wafers in the plurality of first carriers 10 into one second carrier 20, the first carriers 10 (A, 10A) containing the semiconductor wafers to be integrated are stored.
B, C) are set in the first carrier setting section 41.
At the time of this setting, the semiconductor wafers are already arranged for each first carrier with the orientation flats 3 aligned in a predetermined direction as shown in FIG. Alternatively, the orientation flat position setting function may be added to the first carrier setting section 41, and after setting, the orientation flat 3 can be aligned in a predetermined direction in each first carrier. In the case of a carrier in which semiconductor wafers are arrayed vertically, this function can be achieved by using, for example, the technique disclosed in Japanese Patent Application Laid-Open No. 57-187948.

Next, the semiconductor wafers are sequentially transferred from the first carriers (10) A, B, C set in the first carrier setting section 41 to the arm 4 of the robot type semiconductor wafer transfer machine 43.
It is gripped by 3A, transferred to the second carrier 20 set in the second carrier setting section 42, and sequentially arranged as shown in FIG. That is, after the transfer of the semiconductor wafer A-1 is completed, the transfer arrangement of the semiconductor wafer A-2 is performed, and the integration operation is completed by the transfer arrangement of the last semiconductor wafer C-3. In the transfer of the semiconductor wafer, since the position (direction) of the orientation flat 3 is not changed before and after the transfer, the orientation direction of each semiconductor wafer in FIG. Is done.

Next, the second carrier 2 set in the second carrier setting section 42 and having the semiconductor wafers unifiedly arranged
The operation of separating the semiconductor wafer from 0 into the first carriers (10) A, B, and C set in the first carrier setting section 41 as shown in FIG. 3 will be described.

First, the semiconductor wafer A-1 located at one end of the semiconductor wafer array shown in FIG. 2 is gripped by the arm 43A of the robotic semiconductor wafer transfer device 43, and the optical automatic orientation flat position detection unit 45 detects the orientation flat 3. Then, the first semiconductor wafer is transferred to the first carrier (10) A to which the first semiconductor wafer was transferred at the time of lot integration, that is, the first carrier (10) A. Next, the second semiconductor wafer A-2 is gripped from the second carrier 20 and the optical automatic orientation flat position detector 45 is held.
To detect and identify the position of the orientation flat 3. Since the identification result is the same as that of the previous semiconductor wafer A-1, the semiconductor wafer A
Semiconductor wafer A- on the same first carrier (10) A as
Transfer to the next position and arrange. In this case, if the identification result is different from the identification result of the previous semiconductor wafer, the wafer is transferred and arranged on the next first carrier (10) B.

As described above, when the third and subsequent semiconductor wafers are transferred with the same regularity as the transfer of the second semiconductor wafer, the transfer is completed when the transfer is completed. The configuration separates the semiconductor wafer.

That is, in this embodiment, the position of the orientation flat 3 of the fourth semiconductor wafer B-1 is different from the position of the orientation flat 3 of the preceding third semiconductor wafer A-3.
From the first semiconductor wafer B-1 to the first carrier B, which is the second first carrier 10 set in the first carrier setting unit 41, the wafers are transferred and arranged. Similarly, the position of the orientation flat 3 of the tenth semiconductor wafer C-1 is 9
Since the position is different from the position of the orientation flat 3 of the sixth semiconductor wafer B-6, the third first carrier 1 set in the first carrier setting section 41 from the tenth semiconductor wafer C-1
The first carrier C, which is 0, is transferred and arranged. Thus, the lot configuration after separation shown in FIG. 3 becomes the same as the lot configuration before integration in FIG.

The positions of the carriers set in the first and second carrier setting units 41 and 42 need to be the same in the case of integration and the case of separation.
The operation control of the transfer machine including the processing of the identification information of the position of the orientation flat 3 is performed by the semiconductor wafer transfer control section 44.

[0035]

As described above, according to the present invention, the arrangement of the semiconductor wafers housed in the first first carrier on the second carrier integrating the semiconductor wafers in the plurality of first carriers. And the arrangement of the semiconductor wafers stored in the second first carrier are identified where the direction of the orientation flat is switched. You can return to your carrier. Therefore, semiconductor wafer lot management becomes easy.

[Brief description of the drawings]

FIG. 1 is a diagram showing a state before a semiconductor wafer is integrated in an embodiment of the present invention.

FIG. 2 is a diagram showing a state where a semiconductor wafer is integrated from the state of FIG. 1;

FIG. 3 is a view showing a state where a semiconductor wafer is separated from the state of FIG. 2;

FIG. 4 is a schematic diagram illustrating an apparatus used for integration and separation of the present invention.

FIG. 5 is a diagram showing a state before a semiconductor wafer is integrated in a conventional technique.

FIG. 6 is a diagram showing a state where the semiconductor wafers are integrated from the state of FIG. 5;

FIG. 7 is a view showing a state where the semiconductor wafer is separated from the state of FIG. 6;

[Explanation of symbols]

3 Ori-fla 10 First carrier A, B, C (or third carrier A ', B', C ') 11, 12, 13, 21, 22, 23, 31, 32, 3
3 Lot of Semiconductor Wafers 20 Second Carrier 41 First Carrier Set Unit 42 Second Carrier Set Unit 43 Robotic Semiconductor Wafer Transfer Machine 43A Arm 44 Semiconductor Wafer Transfer Control Unit 45 Optical Automatic Ori-Fla Position Detector

Claims (5)

(57) [Claims] 1. A semiconductor wafer constituting a first lot in a first first carrier when semiconductor wafers housed in a plurality of first carriers are integrated and housed in one second carrier. And the orientation flats of the semiconductor wafers constituting the second lot in the second first carrier are arranged in the second direction by aligning the orientation flats in the first direction with a direction different from the first direction. Aligned in the second direction, arranged on the second carrier following the arrangement of the semiconductor wafers contained in the first first carrier, and thus arranged in the second carrier. In the arrangement of the semiconductor wafers, which of the plurality of first carriers is contained in the first carrier can be identified in the direction of an orientation flat. A method for integrating semiconductor wafers, comprising: 2. A semiconductor wafer constituting a third lot in a third first carrier, wherein the orientation flats of the semiconductor wafers are aligned in the first direction and are accommodated in the second first carrier. The semiconductor wafer in the odd-numbered first carrier and the orientation of the even-numbered semiconductor wafer in the first carrier are arranged in the second carrier following the arrangement of the semiconductor wafers. 2. The semiconductor wafer integration method according to claim 1, wherein the orientation of the orientation flat is alternately changed and the orientation is arranged on the second carrier. 3. The diametrically opposite direction of the first direction is the second direction.
3. The semiconductor wafer lot integration method according to claim 1, wherein: 4. A plurality of semiconductor wafers integrated on the second carrier are identified by identifying a direction of the orientation flat in the arrangement, so as to have a same lot configuration as a lot configuration in the first carrier before the integration. 4. The semiconductor wafer integration method according to claim 1, wherein the third carriers are separately stored in the third carriers. 5. The method according to claim 4, wherein the first carrier and the third carrier are the same carrier.