JP2613257B2 - Multi-port RAM - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a multi-port RAM (random access memory) capable of reading and writing data independently or in parallel, and a high-speed data transfer therethrough. The present invention relates to a read technology, for example, a technology that is effective when applied to a multi-port RAM having static memory cells.

(Prior art)

A static multi-port RAM can be used to increase the arithmetic processing speed in a microphone computer or even a small and medium-sized computer.

This static multi-port RAM has a plurality of memory cells formed by coupling a write transfer gate and a read transfer gate to a data input / output terminal of a static latch circuit, and a write transfer gate of a memory cell selected by a write address. A dedicated write system for providing write data to a write bit line to which data is coupled, and a read system for externally reading data supplied to a read bit line from a read transfer gate of a memory cell selected by a read address. The data write operation and the read operation can be performed asynchronously and independently.

As an example of a document describing a static multi-port RAM, see “VLSI SY” issued in November 1987.
`` Embedded R '' described on pages 60 to 65 of `` STEMS DESIGN ''
AM in Gate Arrays: Oonfigurability and Testabi
lity ".

[Problems to be solved by the invention]

The present inventor has studied on speeding up of a data read operation in a static multiport RAM.

In a static multi-port RAM capable of performing a data write operation and a read operation independently and asynchronously, a write operation and a read operation may be performed at substantially the same timing for the same memory cell. In consideration of this, under the write priority, as is often the case, the access time of the static multi-port RAM is governed by the time until the information written in the memory cell to be accessed is read again. You. That is, the access time when the write operation and the read operation are not performed at the same timing on the same memory cell is also restricted by the slow access time, and the overall access time in the multiport RAM according to the timing rule is delayed.

To eliminate this delay in overall access time,
The read address and read address can be monitored and an alarm can be issued when they come close to each other to prohibit simultaneous access to the same memory cell.However, such a method limits access to multiport RAM. Conditions are added, so that access control for satisfying this restriction condition becomes complicated, and the usability of the multi-port RAM deteriorates.

As described above, in the conventional multi-port RAM, in order to use the same for high-speed access, it is necessary to set a restriction condition that prohibits simultaneous write and read access to the same memory cell. The present inventor has clarified that there is a problem that if it is neglected, the data read operation speed must be reduced.

Further, the present inventor precharges a bit line or a common data line to one of relatively higher power supply voltage levels from the viewpoint of low power consumption in a static multi-port RAM and prevention of erroneous writing during a data read operation. In consideration of this, a memory cell structure that allows a minute potential change corresponding to memory cell data to be applied as it is to a bit line precharged to the power supply voltage, and a potential difference of the bit line near the power supply voltage. Other means that contribute to speeding up the data read operation in a static multi-port RAM, such as a sense-up structure that can detect the signal at high speed and amplify and output it, were also studied.

An object of the present invention is to provide a multi-port RAM capable of reading data at high speed even when writing and reading operations to the same memory cell are performed at exactly the same or partially overlapping timing.

Still another object of the present invention is to provide a multi-port RAM having a configuration in which a bit line or a common data line is precharged to one of a relatively high power supply voltage level, a memory cell structure capable of speeding up a data read operation, It is intended to provide a sense-up structure and the like.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

In other words, it has a write system and a read system that can perform data write operation and read operation asynchronously and independently,
In response to detecting the coincidence between the write address and the read address, write data externally applied to the write system is directly applied to the read system via the transmission means.

The transmission means may be a switch element for transmitting data externally applied to the write system to the read common data line included in the read system via the write common data line. At this time, when the precharge level of the write bit line and the read bit line, and furthermore, the precharge level of the write common data line and the read common data line corresponds to one of the relatively high power supply voltage levels applied to the static memory cells The switch element constituting the transmission means is a p-channel MOSFET
It is good to be constituted by.

When the write data is directly supplied to the read system via the transmission means, it is desirable to control all the read selectors for selectively controlling the read bit lines to the read common data lines to be nonconductive.

Further, the data write operation and the read operation can be performed independently and asynchronously with respect to the static memory cell coupled to the write bit line and the read bit line having one of the relatively high power supply voltage levels as the precharge level. Multi-port RA with write and read systems
In M, a write transfer gate for coupling a write bit line and a static memory cell is set to n.
A memory cell structure is adopted in which a channel type MOSFET is used, and a read transfer gate for coupling a read bit line and a static memory cell is a p-channel type MOSFET.

At this time, the sense amplifier included in the readout system is supplied to the input terminal of the differential amplifier by shifting the precharge level of the differential amplifier and the read common data line to near the operating point of the differential amplifier. It is preferable to include a level shift circuit. Furthermore, a p-channel type read select switch for selectively controlling the read bit line to be connected to the read common data line is provided.
It is preferable to use an n-channel MOSFET as a MOSFET and a write select switch for selectively controlling the write bit line to be electrically connected to the write common data line.

(Operation)

According to the above-described means, when the write operation and the read operation are performed at the same timing in the same memory cell, the transfer means directly supplies the write data to the read-system sense amplifier. The obtained data is read out to the outside at high speed while substantially satisfying the write priority condition, and writing to the memory cells is performed in parallel.

At this time, the sense amplifier to which the write data is given via the transmission unit amplifies and outputs the data in accordance with the original data read operation timing, so that the transmission unit specially controls the timing of transmitting the write data to the read system. No need to work.

When write data is supplied from the write system to the read system while both the write common data line and the read common data line are precharged to one of the relatively high power supply voltage levels, the P-channel type MO
As a result of the transconductance of the transmission means constituted by the SFET being increased, this large transconductance is
It works to improve the transmission performance of write data.

When the transmitting means supplies the write data to the read system, if the read selector controls all the read bit lines to be non-conductive with respect to the read common data line, the non-conductive state corresponds to the memory cell data selected at this time. It works so as to avoid conflict with the write data given to the read system.

When memory cell data is supplied to a read bit line in a state where both the write bit line and the read bit line are precharged to one of the relatively high power supply voltage levels, a read transfer constituted by a P-channel MOSFET is performed. The gate has a large transconductance, which results in this large transconductance
It works to enhance the transmission performance of the memory cell data that changes near the power supply voltage. In a write operation, a write transfer gate composed of an n-channel MOSFET connected to a write bit line discharged from a precharge level has an increased transconductance. As a result, this large transconductance is discharged from the power supply voltage. This serves to enhance the performance of transmitting the change in the level of the write bit line and the level of the discharge reaching the static latch circuit. Similarly, the read select switch composed of a p-channel MOSFET and the write select switch composed of an n-channel MOSFET have a large transconductance during operation, and the large transconductance enhances the signal transmission performance. work.

The level shift circuit included in the sense amplifier converts a minute level change in the vicinity of the power supply voltage applied to the read common data line into a level change in the vicinity of the operating point at which the amplification operation of the differential amplifier is most sensitive. The differential amplifier that receives this level-shifted voltage can quickly determine its amplification operation without waiting for the read bit line or read common data line itself with a large load capacitance to reach the vicinity of the operating point of the differential amplifier. I do.

Embodiment 1 FIG. 1 shows a static type 2 according to an embodiment of the present invention.
A block diagram of the port RAM is shown. Although not particularly limited, the two-port RAM shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known MOS integrated circuit manufacturing technique.

First, the outline of the two-port RAM of the present embodiment will be described.
A memory cell constituting the memory cell array 1 is formed by coupling a write transfer gate and a read transfer gate to a data input / output terminal of a static latch circuit. The memory cell is connected to the write transfer gate via a write bit line. Writing system to combine,
A data write operation and a data read operation can be performed independently and asynchronously via a read system coupled to a read transfer gate via a read bit line.

According to the present embodiment, the write system selectively connects the write bit line to the write common data line CDw, ▲ ▼ and controls the write Y selector 2 to complement the write common data line CDw, ▲ ▼ according to the write data Din. It is composed of a write data driver 3 driven to the level. The read system includes a read Y selector 4 for selectively controlling the read bit line to conduct to the read common data line CDr, ▲ ▼, a sense amplifier 5 for detecting and amplifying a potential difference applied to the read common data line CDr, ▲ ▼, An output latch circuit 6 for holding the output of the sense amplifier 5 and an output buffer circuit 7 are provided.

The operation timing or operation cycle for the read system and the write system is not particularly limited, but is basically defined by the read clock CER for the read operation and the write clock CEW for the write operation, and the read clock CER and the write clock CEW are This has a meaning as a chip enable signal in a clock synchronous RAM. This read clock CER and write clock CEW
Are asynchronous clocks whose mutual phase relationship is determined by their supply conditions, internal and external delay conditions, and the like. Thus, it is generally assumed that the read cycle and the write cycle completely or partially overlap. Therefore, the write operation and the read operation are performed at the same or partially overlapped timing with respect to the same memory cell. Sometimes.

Regarding this point, in the multi-port RAM of the present embodiment,
In response to the address coincidence detecting circuit 8 detects the coincidence of the write address Aw ₁ ~Awn read address Ar ₁ ~Arn, directly via a short circuit 9 as a vehicle for writing data supplied from the outside to the write system The read common data lines CDr, ▲ ▼ of the read system are provided. The write information given to the read common data line CDr, ▼ via the short circuit 9 is supplied to the sense amplifier 5. In this way, the information given to the read system is read out to the outside at a high speed while substantially satisfying the write priority condition, and the write to the access target memory cell is performed in parallel.

Therefore, even when the write operation and the read operation are performed at the same or partially overlapped timing with respect to the same memory cell, the data read operation speed does not decrease. The two-port RAM can be used for high-speed access without providing a restriction condition of prohibiting access.

 The details of the two-port RAM will be described below.

 Details of the memory cell array 1 are shown in FIG.

Although the memory cell 10 is not particularly limited, the complementary MOS
A static latch circuit (hereinafter also simply referred to as CMOS) has its basic configuration. The static latch circuit is formed by cross-connecting one input terminal of a pair of CMOS inverter circuits constituted by a P-channel MOSFET Q1 and an N-channel MOSFET Q2 and an output terminal of the other CMOS inverter circuit to each other.

Each of the coupling nodes of the MOSFETs Q1 and Q2 has two sets of N
Channel type MOSFETs Q3, Q4, Q5, Q6 are coupled. MOSFETQ
3 and Q4 are write transfer gates and MOSFET Q
5 and Q6 are read transfer gates. Second
Although one memory cell is representatively shown in the figure, a plurality of memory cells 10 are actually arranged in a matrix in the X and Y directions.

The gate electrodes of the MOSFETs Q3 and Q4 forming the write transfer gate in the memory cells 10 arranged in a matrix are connected to a write word line for each X direction. The gate electrodes of the MOSFETs Q5 and Q6 forming the read transfer gate are connected to the read word line WLrα for each X direction. One of the drain or source electrodes of the MOSFETs Q3 and Q4 constituting the write transfer gate in the memory cells 10 arranged in a matrix is connected to the write bit line BLwβ, And one of the drain or source electrodes of the MOSFETs Q5 and Q6 constituting the read transfer gate is connected to the read bit line BLrβ, ▲ for every Y direction.
It is combined with ▼.

The above read word line Is controlled by the read X address buffer 13, the read X address decoder 14, and the read word driver 15 shown in FIG.

The read X address buffer 13 converts the read address signals Ar _{1 to} Ari into complementary address signals ar ₁ , ▲ ▼ to ari,
The data is converted to ▼ and supplied to the read X address decoder 14. FIG. 4 shows a configuration example for one bit of the address buffer 13. The address bit Arα is inverted by three serial CMOS inverter circuits 16 to 18 to form an inverted bit ビ ッ ト, and the serial two The non-inverted bit arα is formed by the CMOS inverter circuits 16 and 17 of FIG.

The read X address decoder 14 supplies complementary address signals ar ₁ , ▲ supplied from the read X address buffer 13.
▼ to ari, ▲ ▼ decoded and read word line Selection signal for selecting one from among To form

FIG. 5 shows a configuration example of the read X address decoder 14. The read X address decoder 14 shown in FIG.
A NAND gate 19 is provided for each pitch.
Internal complementary address signals ar ₃ to 19, ▲ ▼ ~ari, ▲
The predetermined bit of ▼ is supplied, and the output of one NAND gate 19 is set to a low level in accordance with the combination of the levels of the supplied bits. One NAND gate
The output of 19 is used for block selection using four word lines as one unit. To select one of the four word lines included in this one unit block, the lower two bits ar ₁ , ▲
The decoding result by AND logic of ▼, ar ₂ , ▲ ▼ is used. For example, four types of signals obtained as the decoding result are individually received by the gate electrode.
By commonly connecting channel MOSFETQ10~Q13 to the output terminal of one NAND gate 19, MOSFET Q 10 is an output gate of the word line selection signal WSR ₁ corresponding to the read word line WLr _1, likewise MOSFETQ11 read word A word line selection signal WSr ₂ output gate corresponding to the line WLr ₂ ,
Word line selection signal WSR ₃ of output gates MOSFETQ12 corresponds to the read word line WLr _3, MOSFET Q13 is a word line selection signal WSR ₄ output gates corresponding to the read word line WLr _4.

The read word driver 15 is provided with a word line selection signal supplied from the read X address decoder 14. , One predetermined read word line is driven to a selected level such as a high level.

FIG. 6 shows a configuration example of the read word driver 15. Although the word driver 15 is not particularly limited,
A drive inverter circuit 20 for inverting and driving the word line selection signal WSrα via an n-channel type gate MOSFET Q15 receiving the read clock CER at the gate electrode is provided. Further, the input of the drive inverter circuit 20 is instructed by a p-channel MOSFET Q16 for forcing a word line to a non-selection level during a precharge period indicated by a low level of the read clock CER, and a word line selection signal WSrα. A p-channel MOSFET Q17 for maintaining the state until a certain drive timing is connected.

The above write word line Is controlled by the write X address buffer 21 shown in FIG.
This is performed by the write X address decoder 22 and the write word driver 23.

The write X address buffer 21 converts the write address signals Aw _{1 to} Awi into complementary address signals aw ₁ ,
It is converted into awi, ▲ ▼ and output, and can be configured in the same manner as in FIG. The write X address decoder 22 decodes the complementary address signals aw ₁ , ▲ to awi, ▲ ▼ supplied from the write X address buffer 21 to write a write word line. Word line selection signal for selecting a predetermined one from among To form As the selection logic for this, the same logic as in the configuration of FIG. 5 can be adopted.

The write word driver 23 receives a word line selection signal supplied from the write X address decoder 22. And a predetermined write word line is driven to a selected level such as a high level on the basis of the above.

1 and 2, reference numeral 11 denotes a precharge circuit.

The precharge circuit 11 precharges the read bit lines BLrβ, ▼ and the write bit lines BLwβ, ▼▼ to one of the relatively high power supply voltages Vdd before the read or write operation. The precharge circuit 11 includes a pair of P-channel precharge MOSFs receiving a power supply voltage Vdd at a source electrode.
The drain electrode of ETQ8 is the read bit line BLrβ, ▲
A pair of P-channel precharge MOSFs coupled to one end of ▼ and receiving the power supply voltage Vdd at the source electrode
The drain electrode of ETQ9 is the write bit line BLwβ, ▲
It is connected to one end of ▼. Precharge
The MOSFET Q8 is switch-controlled by the read clock CER, and is turned on in response to a precharge period indicated by the low level of the read clock CER, so that the read bit lines BLrβ, ▲
▼ is precharged to the power supply voltage Vdd. On the other hand, the precharge MOSFET Q9 is switch-controlled by the write clock CEW, and is turned on in response to a precharge period indicated by the low level of the write clock CEW, so that the write bit lines BLwβ, ▲
▼ is precharged to the power supply voltage Vdd.

When the write bit lines BLwβ, ▲ ▼ and the read bit lines BLrβ, ▲ ▼ are precharged to the power supply voltage Vdd, the write common data lines CDw, ▲ ▼ and the read common data lines CDr, ▲ will be described in detail later.
▼ is also precharged to the power supply voltage Vdd. In the read operation of the memory cell data in this state, the read bit line and the read common data line CDr, ▲ ▼ which are made conductive with the selected memory cell, one of the selection bits which takes the on state according to the information held in the memory cell. MOSFETQ2
Starts a minute level change from the power supply voltage Vdd due to the discharge action of. In the write operation, one of the write bit line and the write common data line CDw, which is made conductive with the selected memory cell, is operated by the write data driver 3 to a level sufficient to invert the information held in the memory cell. Discharge is performed from the power supply voltage Vdd to the ground potential Vss.

The write bit lines BLw ₁ , Are commonly connected to a write common data line CDw, ▲ ▼ via n-channel type selection MOSFETs Q20, Q20 constituting a write Y selector 2 as shown in FIG. Read bit line BLr ₁ , Is a p-channel type selection constituting the read Y selector 4
Read out common data line CDr via MOSFET Q21, Q21, ▲
Connected to ▼.

Here, the write bit lines BLwβ, ▼ and the read bit lines BLrβ, ▼ are both precharged to a relatively high power supply voltage Vdd. Separately, the write common data lines CDw, ▼ and the read common data lines CDr, ▼ are also precharged to the power supply voltage Vdd. In this state, when the memory cell data is applied from the read bit line BLrβ, ▲ ▼ to the read common data line CDr, ▲ ▼, the mutual conductance of the p-channel type selection MOSFETs Q21, Q21 controlled to be on is increased. As a result, this large transconductance works to enhance the transmission performance of the memory cell data that changes near the power supply voltage Vdd. In the write operation, one of the write common data lines CDw and ▲ ▼ is finally discharged from the precharge level of the power supply voltage Vdd to the ground potential Vss of the circuit, and such a discharge level is transmitted to the memory cell. Is required to increase the reliability of the write operation. At this time, the n-channel type selection MOSFET Q2 controlled to be turned on.
0, Q20 has its transconductance increased,
This large transconductance is applied to the write common data line CDw, ▲ discharged from the power supply voltage Vdd.
▼ works to improve the performance of transmitting the level change to the write bit line.

The selection control of the write bit lines BLwβ, ▲ ▼ via the selection MOSFETs Q20, Q20 included in the write selector 2 is performed by the write Y address buffer 24 and the write Y address decoder 25.

The write Y address buffer 24 converts the write address signals Awj to Awn into complementary address signals awj, ▲ ▼ to
Convert to awn, ▲ ▼ and output. The write Y address decoder 25 outputs the complementary address signals awj, ▲ to awn, ▲ supplied from the write Y address buffer 24.
▼ is decoded and the write bit lines BLw ₁ , Bit line select signal for controlling the selection MOSFETs Q20, Q20 corresponding to a predetermined pair from the To form For example, as shown in FIG. 2, the output of the NAND gate 26 is inverted by the inverter circuit 27 to select the MOSFET Q2.
A logic in which a configuration for supplying to the gate electrode of 0, Q20 is provided for each write bit line pair can be employed. In such an address decode logic, any one of the write bit line select signals is set to the high level and the pair of select MOSFETs Q20 and Q20 are turned on regardless of the state of the combination of the levels of the write address signals Awj to Awn. take.

Selection control of the read bit lines BLrβ, ▼ via the selection MOSFETs Q21, Q21 included in the read selector 4 is performed by the read Y address buffer 28 and the read Y address decoder 29.

The read Y address buffer 28 converts the read address signals Arj to Arn into complementary address signals arj, ▲ to arn,
Convert to ▲ ▼ and output. The read Y address decoder 29 supplies the complementary address signals arj, ▲ to arn, ▲ supplied from the read Y address buffer 28.
▼ is decoded to read bit lines BLr ₁ , A read bit line selection signal for controlling the selection MOSFET Q21, Q21 corresponding to a predetermined pair from among To form For example, as shown in FIG. 2, it is possible to employ a logic in which an output of the NAND gate 30 is supplied to the gate electrodes of the selective MOSFETs Q21, Q21 for each read bit line pair.

In the present embodiment, the detection signal AC of the address coincidence detection circuit 8 is supplied to each NAND gate 30 included in the read Y address decoder 29. The detection signal AC is set to a low level when they match, and to a high level when they do not match. Therefore, the output of the NAND gate 30 if the write address Aw ₁ ~Awn read address Ar ₁ ~Arn match is forced to a high level, whereby all of the selected MOSFET Q 21, Q21 are off included in the read Y selector 4 Then, the read common data lines CDr, ▲ ▼ are all read bit numbers BLr ₁ , Disconnected from Therefore, when the write data applied to the write common data line CDw, ▲ ▼ is transmitted to the read common data line CDr, ▲ ▼ through the short circuit 9 when the write address and the read address match, all the read bits Since the line is made non-conductive with respect to the read common data line CDr, ▲ ▼, this non-conductive control state avoids competition between the read data of the memory cell selected at this time and the write data given to the read system. Acts to be.

Note that the write addresses Aw _{1 to} Awn and the read address Ar
_{In the} state where _{1 to} Arn do not match, the read address signal Ar
Any one of the combinations of the levels j to Arn
One read bit line select signal is set to high level and
By selecting the pair selection MOSFETs Q21 and Q21 in the ON state,
Read bit line BLr ₁ , Is precharged to the power supply voltage Vdd, the read common data lines CDr,
Precharged to d.

In FIG. 2, the write common data line CDw, ▲
A short circuit 9 for selectively conducting between ▼ and the read common data line CDr, ▲ ▼ is a pair of p-channel type transmission MOSFETs.
It is composed of Q22 and Q22. These transmission MOSFETs Q22, Q22
The switch is controlled by receiving the detection signal AC at the gate electrode.

The write data is read out via the transmission MOSFETs Q22, Q22 controlled to be in the on state, and the common data line CDr, ▲ ▼
Is transmitted to the write common data line CDw, ▲
▼ and the read common data line CDr, ▲ ▼ both have a write voltage. At this time, the transconductance of the p-channel type transmission MOSFETs Q22, Q22 controlled to be in the ON state is increased, and as a result, the large transconductance changes from the write common data line CDw, ▲ ▼ which changes from near the power supply voltage Vdd. It works to enhance the transmission performance of the complementary level change.

FIG. 7 shows an example of the write data driver 3.

The write data driver 3 includes two 2-input NAND gates 31 and 32 as drive output stages. Write data Din is supplied to one NAND gate 31 through two serial CMOS inverters 33 and 34 and the other NAND gate 31 is connected to the other NAND gate 31. Three
2, the inverted level of the write data Din is supplied via the CMOS inverter 33. Output control by the NAND gates 31 and 32 is performed by the write clock CEW and a write enable signal WE for instructing a write operation at a high level. The control logic for this is a two-stage CM
A two-input NAND gate 37 to which the write enable signal WE is supplied and the write clock CEW is supplied through the OS inverters 35 and 36 is provided. The output of the NAND gate 37 is inverted by the CMOS inverter 38 and the pair of NAND gates is provided.
Each of the input terminals 31 and 32 is supplied to the other input terminal.

When both the write enable signal WE and the write clock CEW are set to the high level, the write data driver 3 drives the write common data lines CDw, ▲ ▼ to the complementary level according to the write data Din. Otherwise, write common data line CDw, ▲
Both forces に to the power supply voltage Vdd equal to the precharge level.

FIG. 8 shows an example of the address coincidence detecting circuit 8.

The address coincidence detection circuit 8 calculates the complementary write addresses aw ₁ , ▲ to awn, ▲ and the complementary read addresses ar ₁ , ▲ to arn, ▲ by an exclusive OR 40 for each corresponding bit. The match is determined, and the match of each bit is determined by the NOR gate 41. When the write address and the read address all match, the output of the NOR gate 41 is set to the high level.
At this time, the output of the NOR gate 41 is output together with the write clock CEW to avoid the possibility that the transmission MOSFETs Q22 and Q22 are erroneously turned on except when the write operation and the read operation are performed on the same memory cell at substantially the same timing. The detection signal AC is input to the NAND gate 42 and is formed through NAND logic based on the input.

 FIG. 3 shows an example of the sense amplifier 5.

This sense amplifier 5 has a read common data line CDr,
Power supply voltage which is the precharge level in ▲ ▼
A differential amplifier 50 for detecting and amplifying a complementary level change generated near Vdd is included in the preceding stage, and the above-mentioned minute level change near the power supply voltage Vdd generated in the read common data line CDr, It is converted into a level change near the operating point where the amplification operation of the dynamic amplifier 50 becomes the most sensitive,
A level shift circuit 51 for providing this to the input terminal of the differential amplifier 50 is provided.

Although not particularly limited, the differential amplifier 50 includes a pair of N-channel input terminals forming a differential pair in which a common connection terminal of source electrodes is connected to the ground potential Vss via an N-channel power switch MOSFET Q30 as a current source. P-channel type MOSFETs Q33, Q33, Q31, Q32, which constitute a current mirror load, are provided at each of the drain electrodes of the input MOSFETs Q31, Q32.
The drain electrode of Q34 is connected. The source electrodes of the P-channel MOSFETs Q33 and Q34 constituting the current mirror load are connected to the power supply voltage Vdd, and the common connection terminal of their gate electrodes is coupled to the drain electrode of the input MOSFET Q31.
A pair of input terminals of the differential amplifier 50 are used as gate electrodes of the input MOSFETs Q31 and Q32. The output terminal of the differential amplifier 50 is MOSFET
Q32 and Q34 are combined drain electrodes and output inverter
It is connected to 52 input terminals. When the output voltage of the differential amplifier 50 reaches a level detectable by the output inverter 52, the output of the output inverter 52 is determined.

The power switch MOSFET Q30 is switch-controlled by a read clock CER supplied to its gate electrode. The power switch MOSFET Q30 is turned on by the high level of the read clock CER to activate the differential amplifier 50. The output terminal of the differential amplifier 50 is charged to the power supply voltage Vdd level by the P-channel MOSFET Q35 in response to the inactivation of the differential amplifier 50.

When the differential amplifier 50 is activated and a complementary signal is applied to the input terminal, the drain / current flowing through each of the MOSFETs Q31 and Q32
The source-to-source current is different, whereby the drain-source current of the MOSFET Q31 changes the source-drain voltage of the MOSFET Q33, and this change and the drain-source current of the MOSFET Q32
The change in the source-to-source current determines the source-drain voltage of MOSFET Q34. For example, when the gate input voltage of MOSFET Q31 is higher than the gate input voltage of MOSFET Q32, the drain voltage of MOSFET Q32, which is the amplified output of differential amplifier 50, is set higher than the drain voltage of MOSFET Q31. Conversely, when the gate input voltage of MOSFET Q32 is higher than the gate input voltage of MOSFET Q31, the drain voltage of MOSFET Q32, which is the amplified output of differential amplifier 50, is made lower than the drain voltage of MOSFET Q31.

As described above, the differential amplifier 50 has a pair of input MOSFETs Q31 and Q32.
The change in the current generated in the MOSFETs Q31 and Q32 due to the difference in the gate input voltages of the MOSFETs Q31 and Q32 is taken out to the output terminal as the change in the source-drain voltage of the MOSFET Q34.
The amplification degree or amplification sensitivity of the differential amplifier 50 is maximized because each of the MOSFETs Q31, Q32, Q33,
This is the saturation region of Q34. That is, the differential input level at which the amplification operation of the differential amplifier 50 has the highest sensitivity is
Approximate power supply voltage that allows the SFET to operate in the saturation region
A complementary level centered on the intermediate level of Vdd (range near voltage Vdd / 2).

The level shift circuit 51 includes a read common data line.
A minute level change in the vicinity of the power supply voltage Vdd as a precharge level generated in CDr, ▼ is converted into a level change in the vicinity of the operating point where the differential amplifier 50 has the highest sensitivity in the amplifying operation.

That is, although not particularly limited, the level shift circuit 51 includes, as a basic configuration, a pair of source follower circuits that change the source potential of the output so as to follow the input voltage.
The drain electrodes of MOSFETs Q40 and Q41 are coupled to power supply voltage Vdd, the gate electrode of one drive MOSFET Q40 is coupled to read common data line CDr, and the gate electrode of the other drive MOSFET Q41 is coupled to read common data line ▲ ▼. Then, N is applied to the source electrodes of the drive MOSFETs Q40 and Q41.
Connect the drain electrodes of the channel type MOSFETs Q42 and Q43 and connect the common connection terminal of the gate electrodes of the MOSFETs Q42 and Q43 to M
A current mirror circuit is formed by coupling to the drain electrode of the OSFET Q42. MOSFETs that make up this current mirror circuit
The common connection terminals of the source electrodes of Q42 and Q43 are connected to the ground potential Vss via an N-channel type power switch MOSFET Q44.
A pair of input terminals of the level shift circuit 51 is a drive MOSFET.
The source electrode of the drive MOSFET Q40, which is one output terminal of the level shift circuit 51, is connected to the gate electrode of the input MOSFET 31, which is one input terminal of the differential amplifier 50. The source electrode of the drive MOSFET Q41, which is the other output terminal of the circuit 51, is connected to the differential amplifier 5
It is connected to the gate electrode of input MOSFET Q32 which is the other input terminal of 0. The power switch MOSFET Q44 is switch-controlled by a read clock CER supplied to its gate electrode, and is activated in synchronization with the differential amplifier 50.

In the level shift circuit 51, the shift amount of the output voltage with respect to the input voltage is determined by the threshold voltage of the driving MOSFET Q40 (Q41), a constant determined by the gate oxide film capacity, carrier movement in the channel, and the like, and the MOSFET Q40 (Q41 )
Is determined by the drain-source current of the
For example, 2V for 5V power supply in relation to 50 differential points
It is set to about 2.5V. As a result, a small complementary level change near the power supply voltage Vdd occurring in the read common data line CDr, ▲ ▼ is caused near the operating point near the intermediate level of the power supply voltage Vdd, which is the most sensitive in the amplification operation of the differential amplifier 50. , And this is supplied to the input terminal of the differential amplifier 50.

As described above, the rel-bell shift circuit 51 detects the minute level change in the vicinity of the power supply voltage Vdd applied to the read common data line CDr, ▲ ▼ in the vicinity of the operating point where the amplification operation of the differential amplifier 50 becomes the most sensitive (in general, the power supply (A half level of the voltage Vdd), the differential amplifier 50 receiving this level-shifted voltage outputs the read bit lines BLrβ, ▲ ▼ and the read common data lines CDr, ▲ ▼ with large load capacitance. The amplification operation is determined at high speed without waiting for itself to reach the vicinity of the operating point of the differential amplifier 50.

In particular, since the relationship between the input and output in the level shift circuit 51 is of a source follower type, the output response becomes extremely fast if the load capacity of the output is small. In this embodiment, the output load of the level shift circuit 51 is different. Since only the input gate capacitance of the dynamic amplifier 50 is used, the time required for the level shift operation by the level shift circuit 51 is set to a time that is substantially negligible.

The output latch circuit 6 shown in FIGS. 1 and 3 converts the data output from the sense amplifier 5 during the high level period of the read clock CER into a precharge period (low level of the read clock CER) performed in the latter half of the memory cycle. This is to enable output to the outside also during the level period.

For example, as shown in FIG. 3, the output latch circuit 6 includes a latch circuit 54 that statically latches the output data of the output inverter 52 selectively supplied via a CMOS transfer gate 53. CMOS
The transfer gate 53 includes a p-channel MOSFET Q46 and an n-channel MOSFET Q47, and is switch-controlled by the read clock CER and its inverted signal from the CMOS inverter circuit 55. The latch circuit 54 includes:
It includes two series CMOS inverters 56 and 57, and the output of the rear CMOS inverter 57 is connected back to the input of the previous CMOS inverter 56, and the output of the rear CMOS inverter 57 is CMOS.
The output buffer circuit 7 constituted by the inverter 58 is provided.

Next, an example of a write operation and a read operation when the write address and the read dress do not match in the two-port RAM of the present embodiment will be described with reference to FIG.

In FIG. 9, the phases of the read clock CER and the write clock CEW are shifted, SYCr indicates a read cycle, and SYCw indicates a write cycle, and the low level period of the clock in each cycle is a precharge period.

When Figure 9 time t ₀ to the write clock CEW is a high level, the write X address buffer 21 in accordance with the write address signal Aw ₁ ~Awi at that time, the write X address decoder 22 and the write word driver 23, is operated As a result, the write address signals Aw _{1 to} Awi
Is driven to the selected level. Similarly, write address signals Awj-A
wn, write Y address buffer 24, write Y
When the address decoder 25 and the write Y selector 2 are operated, the write address signals Awj to Awn
, A predetermined pair of write bit lines BLwβ, ▲
▼ is controlled to be conductive to the write common data line CDw, ▲ ▼. At this time, the write data driver 3 enabled by the high level of the write enable signal WE and the write clock CEW drives the write common data line CDw, ▲ ▼ to the complementary level according to the write data Din. This drive signal is applied to the pair of bit lines BLw
When given to β and ▲ ▼, predetermined data is written to the memory cell selected in response to the write address signals Aw _{1 to} Awn.

When Figure 9 time t ₁ to the read clock CER of is the high level, the read X address buffer 13 in accordance with the read address signal Ar ₁ ~Ari at that time, read X address decoder 14 and a read word driver 15, is operated As a result, the read address signals Ar _{1 to} Ari
Is driven to the selected level. Similarly, read address signals Arj to A
rn read Y address buffer 28, read Y
When the address decoder 29 and the read Y selector 4 are operated, the read address signals Arj to Arn are read.
, A predetermined pair of read bit lines BLrβ, ▲
▼ is controlled to conduct to the read common data line CDr, ▲ ▼. Thus, the read address signal Ar ₁
When data of the memory cell selected in response to .about.Arn is transmitted to the read common data line CDr, ▲, the sense amplifier 5
Amplify by detecting the level change of ▼. Sense amplifier 5
Is output to the output latch circuit 6 and is supplied from the output buffer 7 to the outside as read data Dout.

In the read operation, the sense amplifier 5 immediately detects a minute level change near the power supply voltage Vdd of the read bit line and the read mon data line CDr, ▲ ▼ by the operation of the level shift circuit 51 to determine the output operation. The selection period of the read word line is relatively short, and the amplitudes of the read bit line and the read common data line, which are changed during the data read operation, are also kept close to the power supply voltage Vdd.

Access time of the time t ₁ from the read clock CER is asserted to read data Dout is determined is the tca ₁ of Figure 9.

In the operation shown in the time chart of FIG. 9, the write address does not match the read address during the high level period of the write clock CEW, and the read clock CE
Since the high-level period of R does not overlap with the high-level period of the write clock CEW, the detection signal AC is always at the high level, and the transmission MOSFETs Q22 and Q22 included in the short circuit 9 maintain the off state.

Next, an example of an operation of performing write and read operations on the same memory cell at the same timing in the two-port RAM of the present embodiment will be described with reference to FIG.

In FIG. 10, the read clock CER and the write clock CEW
Are completely the same, and the read cycle SYCr and the write cycle SYCw completely overlap.

Even when the high level period of the write clock CEW and the high level period of the read clock CER overlap, the basic operations for writing and reading are performed independently of each other as described above, but especially during the high level period of the write clock CEW. when a match of their addresses are determined by the address coincidence detecting circuit 8 for monitoring the coincidence of the write address Aw ₁ ~Awn read address Ar ₁ ~Arn the detection signal AC is at a low level, a detection signal of the low level The AC turns on the transmission MOSFETs Q22 and Q22 included in the short circuit 9. As a result, the transmission MOSFETs Q22 and Q22 in the ON state store the write data D
The drive signal of the write data driver 3 according to “in” is read from the write common data line CDw, ▲ ▼ and is directly transmitted to the common data line CDr, ▲ ▼.

The write data transmitted in this manner is applied to the sense amplifier 5 and externally applied according to the original data read timing. In this way, the externally applied data substantially satisfies the write priority condition, and the external data read operation is performed in parallel with the write operation. It is not necessary to wait for the read operation to be determined until the written data is read again to satisfy the write priority condition. Since this read operation does not use the read information of the memory cell, the access time at this time
tca ₂ is slightly shorter than the access time tca ₁ described in Figure 9.

The read bit line BLrβ, ▲ shown in FIG.
The change in ▼ indicates a state where the information held in the selected memory cell is inverted by the write data Din at that time. That is, at first, the level of the read bit line BLrβ, ▲ ▼ is changed according to the information held in the memory cell. After that, when the memory cell data is inverted by the write data Din, the read bit line BLrβ, ▲ ▼ is accordingly changed. The level change is reversed. When the level change of the read bit lines BLrβ, BLrβ is read outside through the read common data lines CDr, ▲ ▼ as in the prior art, the determination of the read data Dout is delayed as shown by the broken line, and the access time
tca ₃ becomes extremely long. Note that the read bit line
The state of the level change of BLrβ, ▲ ▼ is illustrated in an exaggerated manner.

Therefore, even if the two-port RAM of the present embodiment is used for high-speed access with the access time tca ₁ described in FIG. 9, there is no need to set the constraint that the same access of writing and reading to the same memory cell is prohibited. As a result, the port RAM of the second embodiment can be accessed at high speed under any access conditions.

[Embodiment 2] Data write operation and read operation are asynchronously and independently independent of a static memory cell coupled to a write bit line and a read bit line having one relatively high power supply voltage level as a precharge level. In a two-port RAM having a write system and a read system that can be performed in the same manner, a memory cell having the structure shown in FIGS. 11 and 12 can be adopted.

The memory cell 60 of FIG. 11 differs from the memory cell 10 in that p-channel MOSFETs Q50 and Q51 are used as read transfer gates.

The memory cell 61 of FIG. 12 differs from the memory cell 60 of FIG. 11 in that high resistance loads R and R are used.

When a two-port RAM is configured using the memory cells 60 and 61, the structure of the first embodiment can be applied as it is, except that the selection level of the read word line WLrα is changed to a low level.

In this embodiment, the write bit lines BLwβ, ▲
▼ and the read bit lines BLrβ, ▲ ▼ are both precharged to a relatively high level power supply voltage Vdd. In this state, the memory cell data is
When applied to BLrβ, ▲ ▼, the transconductance of the p-channel MOSFETs Q5, Q51 for the read transfer gate configuration controlled to the on state is increased, so that the large transconductance changes near the power supply voltage Ddd. It works to improve the transmission performance of memory cell data. In the write operation, the write bit line BLw discharged from the precharge level
The n-channel MOSFETs Q3 and Q4 for writing transfer gates, which are conducted to β and ▲ ▼, have their transconductance increased. As a result, this large transconductance causes the level change of the write bit line discharged from the power supply voltage Vdd. It works to enhance the performance of transmission to the static latch circuit.

In such a manner that the write bit line and the read bit line are precharged to one of the power supply voltages Vdd having a relatively high level, the write transfer gate is set to n.
By using a channel-type MOSFET and configuring the read transfer gate with a p-channel MOSFET, a minute potential change corresponding to the memory cell data can be applied to the read bit line precharged with the power supply voltage Vdd as it is. As a result, the data reading speed is improved. At this time, the write performance is not sacrificed.

In particular, when a memory cell is constituted by a CMOS static latch circuit as shown in FIG. 11, the write and read transfer gates are also CMOS circuits,
The transistor for the transfer gate configuration can be formed by extending and using the diffusion layer of the transistor for the static latch configuration, and the layout of the transistor for the memory cell configuration becomes easy.

The memory cell structure shown in FIG. 11 and FIG. 12 is explained in the first embodiment.
In combination with the read Y selector 4 composed of the SFET and the write Y selector 2 composed of the n-channel MOSFET, the data read operation of the two-port RAM can be further accelerated.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and it is needless to say that various modifications can be made without departing from the gist of the invention.

In the first embodiment, the transmission means has been described as the p-channel type transmission MOSFETs Q22 and Q22 for applying write data from the write common data line to the read common data line. However, as shown in FIG. 6 may be given. That is, the write common data line CDw,
CMO forming latch circuit 54 through MOSFETs Q22 ', Q22'
It is coupled to the input of S inverter 56 and the output of CMOS inverter 57.

Further, in the first embodiment, the read Y address decoder 29 for turning off all the selection MOSFETs Q21 constituting the read Y selector 4 in response to the turning on of the transmission MOSFETs Q22 and Q22 is employed. When the driving capability of the write data driver is extremely large as compared with the driving capability, such consideration may not be paid to the selection MOSFET Q21 in some cases.

The present invention is not limited to a two-port RAM, but can be applied to a three-port RAM by using a memory cell as shown in FIG. 14, and further to a multi-port RAM having more ports. The memory cell shown in FIG. 14, p-channel type coupled to the read word line WLr ₁ α MOSFETQ54, Q5
5 constitutes a first read port, and is connected to the read word line WLr ₂ α.
7 constitutes a second read port and is connected to a write word line WLwα.
A write port is configured by TQ58 and Q59.

Applying the memory cell of FIG. 14 to the first embodiment, a 3-port RA
When M is configured, the address match detection circuit can adopt a circuit configuration as shown in FIG. The address match detection circuit shown in FIG. 15 determines the read address and the write address for the first read port by using an exclusive OR 60 for each corresponding bit, and determines the match of each bit by the NOR gate 61. judge. Similarly, a match between the read address and the write address for the second read port is determined for each corresponding bit by the exclusive OR 62, and a match between the bits is determined by the NOR gate 63. Then, a logical sum 64 is obtained for the determination results of both NOR gates, and the write clock is
The detection signal AC is formed by taking the CEW and the NAND logic 65.

In the second embodiment, the transmission means is not an essential component.

The case where the invention made by the present inventor is applied to a two-port RAM, which is a field of application, has been described above. However, the present invention is not limited to this, and other multi-port RAMs and gate arrays and the like can be used. Can also be widely applied. The present invention can be applied to, at least, a device that can perform a write operation and a read operation independently.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

(1) When the write operation and the read operation are performed at substantially the same timing in the same memory cell, the transmission means directly supplies the write data to the sense amplifier of the read system.
It is possible to read out to the outside at high speed while substantially satisfying the write priority condition. Therefore, the multi-port RA can be set without setting the restriction condition of prohibiting simultaneous write and read access to the same memory cell.
M can be used for high-speed access.

(2) In a configuration in which the transmission means transmits data externally applied to the write system from the write common data line to the read common data line, the sense amplifier to which the write data is applied via the transmission means performs the original data read operation. Since the amplifying operation is performed in accordance with the operation timing, the transmission unit does not need to specifically control the timing of transmitting the write data to the read system, and the configuration of the transmission unit can be extremely simplified.

(3) When write data is supplied from the write system to the read system via the transmission means in a state where the write common data line and the read common data line are precharged to one of the relatively high power supply voltage levels,
As a result of increasing the transconductance of the transmission means constituted by the P-channel MOSFET, the large transconductance acts to enhance the transmission performance of the write data, whereby the write operation can be performed at substantially the same timing in the same memory cell. The speed of the read operation when the read operation is performed can be further increased.

(4) When the transmitting means supplies write data to the read system, the read selector controls all the read bit lines to be non-conductive with respect to the read common data line, so that the non-conductive state is selected at this time. It works so as to avoid competition between the memory cell data and the write data given to the read system, thereby further speeding up the read operation when performing the write and read operations on the same memory cell at substantially the same timing. be able to.

(5) In a multiport RAM capable of independently performing a write operation and a read operation by precharging a write bit line and a read bit line to one of a relatively high power supply voltage level, an n-channel type write transfer gate is used. By adopting a memory cell structure in which a MOSFET is used and a read transfer gate is a p-channel MOSFET, when memory cell data is applied to a read bit line that is precharged to a power supply voltage,
The read transfer gate composed of a p-channel type MOSFET has a large transconductance.As a result, this large transconductance works to enhance the transmission performance of memory cell data that changes near the power supply voltage, and precharges to the power supply voltage. A small potential change corresponding to the memory cell data can be applied to the read bit line as it is, so that the data read speed can be improved. At this time, the write performance is not sacrificed by the action of the write-only transfer gate composed of the n-channel MOSFET.

(6) In a multi-port RAM in which the write bit line and the read bit line, and furthermore the write common data line and the read common data line are precharged to one of the relatively high power supply voltages, the read bit line is read If the read select switch for selectively controlling conduction to the data line is a p-channel MOSFET, and the write select switch for selectively controlling conduction of the write bit line to the write common data line is an n-channel MOSFET, When the memory cell data is supplied from the read bit line to the common data line,
The read select switch composed of a p-channel MOSFET controlled to be turned on has a large transconductance, and this large transconductance acts to enhance the transmission performance of memory cell data that changes near the power supply voltage. In addition, the transconductance of the write selector composed of an n-channel type MOSFET which is controlled to be turned on in the write operation is increased. As a result, the large transconductance is used to set the discharge reaching level of the write common data line discharged from the power supply voltage. Improve the performance of transmitting to bit lines. Therefore, as compared with the case where each select switch is constituted by a CMOS transfer gate, the number of constituent elements can be halved without deteriorating the data transfer characteristics.

(7) The level shift circuit included in the sense amplifier converts a minute level change near the power supply voltage applied to the read common data line into a level change near the operating point at which the differential amplifier amplifies most. Because of the conversion, the differential amplifier receiving this level-shifted voltage performs its amplifying operation without waiting for the read bit line or read common data line with large load capacitance to reach the vicinity of the operating point of the differential amplifier. The determination can be performed at high speed, whereby the speed of the data read operation can be increased.

Further, the word line selection operation can be completed without the signal line having a large load capacitance coupled with the memory cell reaching the vicinity of the operating point of the differential amplifier. The amplitude can be kept to a change close to the power supply voltage, the speed of the precharge operation of the read bit line and the read common data line can be increased, and the power required for the precharge operation of the signal line concerned The consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the entirety of a two-port RAM according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing the main parts from the memory cells of the two-port RAM of FIG. FIG. 3 is a circuit diagram from the sense amplifier of the 2-port RAM to an output buffer circuit in FIG. 1, FIG. 4 is a circuit diagram showing an example of an address buffer, FIG. 5 is a circuit diagram showing an example of an address decoder, FIG. 6 is a circuit diagram showing an example of a word driver, FIG. 7 is a circuit diagram showing an example of a write data driver, FIG. 8 is a circuit diagram showing an example of an address match detection circuit, and FIG. FIG. 10 is a timing chart for explaining an example of a write operation and a read operation when addresses do not match. FIG. 10 shows the same timing for write and read operations for the same memory cell. FIG. 11 and FIG. 12 are timing charts for explaining an example of the operation to be performed. FIGS. 11 and 12 show a memory cell structure in which the conductivity types of the MOS transistors constituting the write transfer gate and the read transfer gate are different from each other. It is a circuit diagram showing an example. FIG. 13 is a circuit diagram showing another example of the transmission means, FIG. 14 is a circuit diagram showing an example of a memory cell structure that can be employed in a three-port RAM, and FIG. 15 is a diagram employing the memory cell of FIG. 3 port RA
FIG. 3 is a circuit diagram illustrating an example of an address match detection circuit in M. 1 ... memory cell array, 2 ... write Y selector,
3 ... Write data driver, 4 ... Read Y selector, Q21 ... Selection MOSFET, 5 ... Sense amplifier, 6 ...
... Output latch, 7 ... Output buffer circuit, 8 ... Address match detection circuit, 9 ... Short circuit, Q22 ... Transfer MOSFE
T, CER: Read clock, CEW: Write clock, A
C: detection signal, Ar _{1 to} Arn: read address, Aw ₁ to
Awn-Write address, BLr ₁ , CDw, ▲ ▼ …… Write common data line, CDr, ▲
▼… Read common data line, 10… Memory cell, 11… Precharge circuit, 13… Read X address buffer, 14… Read X address decoder, 15…
... Read word driver, 21 ... Write X address buffer, 22 ... Write X address decoder, 23 ...
Write word driver, 24 Write Y address buffer, 25 Write Y address decoder, 28 Read Y address buffer, 29 Read Y address decoder, 50 Differential amplifier, 51 Level shift circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masao Mizukami 1448, Kamizuhoncho, Kodaira-shi, Tokyo Within Hitachi Ultra LSE Engineering Co., Ltd. (56) References JP-A 1-285088 (JP, A JP-A-1-178193 (JP, A)

Claims (4)

(57) [Claims] A write system for applying write data to a write bit line of a memory cell selected by a write address; and a read system for externally reading data applied to a read bit line from a memory cell selected by a read address. A read system for independently writing and reading data; address match detecting means for detecting a match between a write address and a read address; and externally responding to the match detection by the address match detecting means. Transmission means for directly transmitting write data supplied to the write system from the write system to the read system, wherein the transmission means includes data supplied from the outside to the write system via the write common data line in the read system. Multi-point switch element that transmits to the read common data line In the RAM, the read system includes: a read selector that selectively connects a read bit line to a read common data line; and an address decoder that decodes a read address and controls connection by the read selector. A multi-port RAM for inhibiting a read bit line selecting operation by the read selector in response to the detection of a match between a write address and a read address by the address coincidence detecting means. 2. A write system for supplying write data to a write bit line of a memory cell selected by a write address, and a read system for externally reading data supplied to a read bit line from a memory cell selected by a read address. A read system for independently writing and reading data; address match detecting means for detecting a match between a write address and a read address; and externally responding to the match detection by the address match detecting means. Transmission means for directly transmitting write data supplied to the write system from the write system to the read system, wherein the transmission means includes data supplied from the outside to the write system via the write common data line in the read system. Multi-point switch element that transmits to the read common data line Memory, the memory cell includes a static latch, a write bit line and a read bit line individually coupled to data input / output terminals of the memory cell, and write common data selectively connected to the write bit line. The line and the read common data line selectively connected to the read bit line are precharged to one of the relatively high power supply voltage levels, and the switch element is connected to the write common data line. A read transfer gate for connecting the write bit line to a static latch of a memory cell selected by a write address is an n-channel MOSFET.
The read transfer gate for connecting the read bit line to the static latch of the memory cell selected by the read address is a p-channel type MO.
Multi-port characterized by being constituted as SFET
RAM. 3. The read system includes a sense amplifier coupled to a read common data line. The sense amplifier includes a differential amplifier and a precharge level of the read common data line near an operating point of the differential amplifier. 3. The multi-port RAM according to claim 2, further comprising a level shift circuit for level-shifting and supplying the level-shifted signal to an input terminal of the differential amplifier. 4. A read select switch for selectively controlling connection of a read bit line to a read common data line by a p-channel MOSFET, and selectively controlling connection of a write bit line to a write common data line. Write select switch of n channel type
4. The multi-port RAM according to claim 2, wherein the multi-port RAM is constituted by a MOSFET.