JP2610500B2 - Parallel vector calculator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a SIMD parallel computer for ultra-high-speed scientific and technical calculations.

2. Description of the Related Art Conventionally, science and technology calculations, especially simulation calculations using a PDE as a mathematical model, have required large-capacity and high-speed calculations. To meet this demand, array-type multiprocessor parallel computers have been proposed and developed. It has been.
Typical examples are ILLIAC-IV, DAP and PAX. They consist of a two-dimensional processor array. Basically, they are only connected by buses between adjacent processors. If data exchange is required between distant processors, they are passed to the processors one after another. This has the serious disadvantage that the control of the data transfer is complicated and time-consuming. Under such circumstances, various data path networks have been proposed in recent years to enable more diverse data transfer. The inventor has also previously filed a Patent Application No. 92927 “Parallel Processing Computer” (Patent No. 1386622) and a Patent Application No. 68044 “No. 68044” “Parallel Processing Computer” (Patent No. 1404753).
Issue), a unique MIMD-type parallel computer with a buffer memory array was proposed to effectively process universal algorithms for multidimensional simulation. However, even in these systems, as the number of processors increases, the number of network bus lines becomes enormous, the line length naturally increases, and the transfer speed decreases.

On the other hand, from the viewpoint of emphasizing versatility, the vector pipeline system, which is an extension of the conventional computer, has greatly developed and is now the mainstream of supercomputers. However, this method is approaching the physical limit of hardware, and it is difficult to obtain a significant speed increase, and in many cases, the effective speed is not so high in the simulation calculation. For this reason, there is a tendency to demand parallelization after all for the demand for large-capacity and high-speed calculation.

SUMMARY OF THE INVENTION Accordingly, the present invention alleviates the disadvantages of the prior invention by combining the idea of the parallel computer previously invented with the vector pipeline system pursuing extremely high speed as a single unit. It aims to provide the most natural parallelization method on the current supercomputer technology. This method will be regarded as the dominant architecture of the next generation supercomputer.

Means for Solving the Problems (Architecture) In the parallel vector computer of the present invention, one general-purpose computer is used as a front-end processor, and is used in addition thereto. Front-end processors usually have
I / O devices, disk storage devices, consoles, etc. are connected. The front-end processor performs input / output and compilation of data, and transfers an object code to the computer of the present invention, sends and receives a control message, and the like.

The parallel vector computer of the present invention includes a single block computer (claim 1) and a composite block computer (claim 2). The former includes a control unit CB including one control processor CU and a storage device CM for CU, and N
A processor unit PB comprising (a fixed integer) number of parallel operation vector processors PU [α], α = 1, 2,..., N, a scalar processor corresponding to each PU, and a scalar data memory PM [α]; and M ³ months, each with a certain storage capacity cubic array of memory units MU of (M = pN, p be a natural number in) {MU [i, j, k], i, j, k = 1,2, ..., M It has a main memory vector bank part MB consisting of に as a basic component. (1 ² , 1
³ )-Called a parallel vector computer. On the other hand, the latter ones, in units of the processor unit, the sequence of L ² unit of {PB [J, K], J, K = 1,2, ..., L} of the main memory bank portion as a unit and, L ³ units cubic array ｛MB [I, J, K], I, J, K
= 1, 2,..., L}, and is called (L ² , L ³ ) -parallel vector computer.

First, the configuration of the (1 ² , 1 ³ ) -parallel vector computer will be described. The control processor CU sequentially decodes the object code stored in the CM and issues the same control signal to all the operation vector processors. Which vector processor PU [α], α = 1,2,…, N
Also works in perfect synchronization. Each vector processor is
In addition to the scalar register and the scalar operation unit, some vector registers and vector pipeline operation units are provided. A private memory PM [α] corresponding to each PU [α] is provided for scalar data. An MB is provided in the main memory bank for vector data. The bank section MB is basically composed of a three-dimensional array {MU [i, j, k], i, j, k = 1, 2,..., M} of memory units MU having a fixed capacity. Second, PU [α] is a two-dimensional partial array {MU [i] of MUs in the _q-th (= p (α-1) + q) layer for each number α (α = 1, 2,..., N). , j, _q ], i, j = 1, 2,..., M｝ for q = 1, 2,..., p, and a set of high-speed “row” buses (i-direction connection via the called), column vector bank of memory units _{{MU [i, 1, 1} ], MU [i, 2, 1], ...,
_{MU [i, M, 1]} , MU [i, 1, 2], MU [i, 2, 2], ..., M
U [i, M, ₂ ], ..., MU [i, 1, _p ], MU [i, 2, _p ],
, MU [i, M, _p ], i = 1, 2,..., M, can access vector data by the interleave method. That is, for the given i value, a vector of length pN having data as a component at the designated same address in the memory unit of the column vector bank is accessed at high speed. Third, the same set of vector processors can also access the same main memory bank MB via another N sets of high-speed "column" buses (j-direction is referred to as "column"). . For each number α (α = 1,2,…, N),
PU [α] is obtained by _{adding q} = 1 (= p (α−1) + q-th two-dimensional subarray {MU [ _q , j, k], j, k = 1, 2,..., M} to q = 1 , 2,
, P, and the vertical vector bank of the memory unit {MU [ ₁ , j, 1], MU via a set of column buses
[ ₁ , j, 2],…, MU [ ₁ , j, M], MU [ ₂ , j, 1], MU [
₂ ,, j, 2],…, MU [ ₂ , j, M],…, MU [ _p , j, 1], MU
_{[I p ,, 2], ...} , MU [p, j, M]}, j = 1,2, ..., it is also possible to perform vector access by interleaving for each M. That is, for a given j value, a vector of length pN having data as a component at the same designated address in the memory unit of the row vector bank is accessed at high speed.

Next, the configuration of the (L ² , L ³ ) -parallel vector computer will be described. This includes (1 ^2, 1 ³⁾ - an extension system of the parallel vector computer, which gives a way of further large scale, as a unit (corresponding to 1 ²⁾ said processor unit PB, L ² The unit is a square array ｛PB [J, K], J, K = 1,2,
, L｝, and the main memory vector bank MB (1 ³
), And ³ units of L are arranged in a cube in MB
[I, J, K], I, J, K = 1, 2,..., L｝. The control processor CU on each PB sequentially decodes exactly the same object code held on each CM, drives the assigned PU, and operates in perfect synchronization as a whole. Each PB [J,
K] is a row (MB [1, J, K], MB [2, J, K],..., MB [L, J,
K]) and a set of common buses. At this time, PB
The way [J, K] is connected to each MB [I, J, K] is (1 ² , 1 ³ )
It is important to note that this is the same as the row bus system in the system, and that the set of row buses is common. As a whole PB, a long set of vectors can be accessed in parallel (in the row direction). Further, each PB [K, I] is a column of the main storage vector bank (MB [I, 1, K], MB [I, 2,
K],..., MB [I, L, K]) through a common set of column buses. Also in this case, the way that PB [K, I] is connected to each MB [I, J, K] is the same as the column bus system in the (1 ² , 1 ³ ) system, and the column bus group is common. The point is important. As a whole PB, a set of long vectors is parallel (in column direction)
Can be accessed. As a result, in both the (1 ² , 1 ³ ) -system and the (L ² , L ³ ) -system, one or more PBs are connected to the main storage vector bank (or bank row) through a set of row buses connected to each. ) Are accessed in parallel (row operation), and the parallel operation is also performed while simultaneously accessing the main storage vector bank (or bank column) through a set of column buses (column operation). The basic usage of the computer is to perform calculations while repeating.

Operation (centering on data structure and access expression) In order to express this calculation, the data structure of this computer is prepared.

The present computer has a distinctive feature in the arrangement data and the way of storing it in the main memory vector bank, and this will be described first. Now, assume that p = 1 in the (1 ² , 1 ³ ) -system.
N is a fixed number, and the number of PUs is equal to N.
At this time, the main memory vector bank has an N × N × N unit array MU. Now, consider a typical three-dimensional data array U that should normally be declared as REAL U (N, N, N,). Data array @U (I, J, K),
When I, J, K = 1, 2,..., N} are stored in the main storage vector bank, each element is stored in the corresponding memory unit MU [i,
j, k] at the same address. At this time, there are three types of “k-axis direction” fixed to the main storage hardware device, depending on which of the physical space coordinate axes K, J, and I directions corresponds. Things are conceivable. For convenience, they will be called a configuration, b configuration, and c configuration, respectively, and give different expressions as follows: a (match k axis in K direction): U (I, J, / K /) b (k axis Are matched in the J direction): U (I, / J /, K) c (k axis is matched in the I direction): U (/ I /, J, K) These are stored data array expressions. Yes, called stock expression. If you need all of this data, you must declare as many types as you need,
When declared, memory is allocated at different addresses in the memory unit. For example, to use the first two, declare REAL U (N, N, / N /), U (N, / N /, N).

Furthermore, as described above, the computer can use a set of row buses or a set of column buses when performing parallel processing while accessing a data array. A data expression for classifying the processing mode is provided, and is referred to as an access expression. Since two types of access expressions correspond to each of the a, b, and c arrangements, there can be a total of six types of access expressions. The following table shows their representation for data array U: According to this computer, data can be easily replaced between different stock representations. This is important when using this computer. For example, ｛U (I, / J
/, K)} to get the value of {U (I, J, / K /)} Process. Also, use U (/ I /, J, K) for U
(I, / J / .K) と す る And it is sufficient. Alternatively, when {U (I, J, / K /)} and {U (/ I /, J, K)} And it is sufficient. Each of the above reverse paths is also possible.

1 (a), 1 (b) and 1 (c) show models of the parallel vector computer in the arrangement state of a, b and c. In these figures, the central cube is the main storage vector bank MB. The three axes fixed to the cubic arrangement of the memory units are the i, j, and k axes. For easy understanding, one surface perpendicular to the k-axis is set as a reference surface and hatched. Square
ABCD is an array of vector computers PU, and each vector computer PU is indicated by a line segment parallel to ABCD. Two
In the ABCD, a state where the direction of each slice (PU) is parallel to the main storage bank (i, j) plane is a row access state,
A state parallel to the (j, k) plane is a column access state. A corresponding access expression of the array U is illustrated beside each figure.

 An example of a parallel operation instruction will be given.

Or in shorthand And give. This indicates a parallel operation based on a row access in the arrangement a. The vector processor corresponding to each of the numbers K processes the operation in the D0 statement in parallel with a vector (a partial array corresponding to each of K and I) having a component corresponding to a change in J. Take. Naturally, this PD
The data access expressions in the expression appearing in the paragraph 0 must be of the same kind, and the indices in parentheses of each array must be of the same variable name ( Expressions are not allowed.) Given this condition, (I) '
Simple forms such as are also possible. Expressions are allowed for indices that appear in parentheses.

In the above, a case where an expression is allowed for the first subscript is exemplified. However, when an expression is to be written in a form that allows the expression for the second subscript, processing is performed in the b arrangement.

Here, the ΔV obtained by the previous program (I) ′
Using (I, J, / K /)｝, the program (II) can be written immediately. This is because it is only necessary to switch from the row access state to the column access state.
However, using {V (I, J, / K /)} obtained in (I) ′, an assignment expression that allows the expression to be added to the index with // (in this case, the third one) To continue, it is necessary to edit the data array in advance. In this case, To obtain b placement data {V (I, / J /, K)}, Or To obtain c placement data {V (/ I /, J, K)}, And so on.

In the example we have seen so far, the size of the data array (N ×
N × N) is, in the case that matches the size of the memory unit array of the main memory banks, moreover p = 1 that (1 ^2, 1 ³⁾ -
We have seen the case where the system suffices. In general, this is not the case, and the magnitude of any dimension is smaller or larger than N. If it is smaller than N, a mask operation may be performed on the dimension, or a short-length vector process may be performed. If it is larger than N, the main memory is multiplexed (modulo N, but those with the same indices are provided to different addresses of the same unit), and the set of vector processors is also multiplexed (only for each single serial processing. If the main memory is large, p> 1 and
The memory multiplicity is reduced, and processing with a large vector length (pN) is performed. In order to further increase the degree of parallelism and reduce the degree of multiplicity of vector processing, the extended (L ² , L ³ ) −
Use the system.

The computer can also handle two-dimensional array data. It is realized by mapping to four-dimensional array data. Here also, an example will be described. For simplicity, it is assumed that p = 1 in the (1 ² , 1 ³ ) -system. It is assumed that the number of PUs is N. Now, consider a typical two-dimensional array that would normally be declared as REAL U (N ** 2, N ** 2). In this case, there are two types of arrangement, a 'and b', and the access expression is one for each.
Seeds.

In order to allocate this two-dimensional array to the three-dimensional main memory unit array, two fixed pairs of arrangements (for example, a and c arrangements are selected) are mapped and mapped as follows. : The indices I and J are expressed as I = P * N + I ', J = Q * N + J', and I and J are expressed as pairs (P, I ') and (Q, J'), respectively. Then, the access expression U (, / J /) (I)
And U (/ I /,) (J) for each of U (, J ', / Q /) (I)
And U (/ P / ,, I ') (J). Data editing Is represented as follows: {U (, J ′, / Q /) (I)} is transformed into a four-dimensional row access array {U (, J ′, / Q /) (I ′).
(P)｝ (P is the index of multiplicity)
This is the column access array {U (I ',, / Q /) (J')
(P)}, but {U (I ′ ,, / Q /) (J ′) (P)} → {U (/ P / ,,
The editing work of I ') (J') (Q)｝ may be performed. At this time, for a change in P,
Includes the task of editing the vector component whose address jumps N steps into one that jumps one step (each vector can be accessed in an interleaved manner).

Embodiment A specific architecture of a parallel vector computer according to the present invention will be described with reference to the drawings. In FIG. 2, the basic configuration of the parallel vector computer shown in a broken line frame includes a control unit CB, an operation unit PB, and a main storage unit MB.
Is connected to a general-purpose front / end computer 2 by a bus and a communication line 1. Therefore, data input / output, program compilation, and the like are handled by this front / end computer. The control unit is a single control unit processor CU
3 and the program memory CM4. The program code sent from the front-end computer is stored in the program memory. CU3 sequentially decodes the code in CM4,
In addition to performing a control operation by itself, a control signal is transmitted to the arithmetic unit PB via the signal line 5. That is, CU3 plays the role of a window for data input / output between the front / end computer and the parallel vector operation device. The operation unit PB includes a scalar operation unit 6 and a vector operation block 7. The scalar operation unit 6 performs scalar operation and scalar data input / output. The vector operation block 7 performs a vector pipeline operation and vector data input / output. A scalar memory 8 is connected to the scalar operation unit 6, and a cubic array of vector memory units MU9 is connected to the vector operation block 7, and the array of the vector memory units MU forms a main storage unit MB.

Regarding the arithmetic processing, the scalar arithmetic unit 6 is controlled by a control signal (instruction) issued from CU3.
And the entire vector operation block 7 is a SIMD system in which the units operate completely synchronously, and each unit processes only in response to an instruction to be processed by itself. The central part of the apparatus of the present invention is a vector system, and a scalar system is the same as a conventional computer. Therefore, the vector system will be described in detail below. Note that 2 after the control unit CB
Double lines 10 to 14 are a data bus and a communication line.

FIG. 3 is a diagram showing an outline of each vector unit PU (related parts of the vector operation block 7). The vector unit PU receives the instruction received from the control processor CU via the bus 15 corresponding to the signal line 5 in FIG. 2 to the register 16, and operates the vector processing unit 17 and the DMA controller 18 according to the internal control signal. The PU is also connected to the CU by the data bus 11 as an outward line, the instruction bus 15 and the unit selection line 19, and is connected to the vector memory block MB by the data buses 13 and 14 as the inward lines and the address bus 20.

FIG. 4 shows a schematic diagram of a cubic array 21 of memory units MU and a data bus connection between the cubic array 21 and one PU unit 22. However, it is assumed that the MUs are respectively located on the grid points in the figure. In the figure, a horizontal rectangular area surrounded by a thick solid line frame is defined as a k-th real board 23,
It is assumed that the partial memory array MU (.,.,. Alpha.) Of the layer (array of black circles 24) is placed. Similarly, the vertical rectangular area surrounded by the thick broken line frame is regarded as the α-th virtual board 25, and the partial memory array MU (α, α,
・, ・) (Array of white circles ○ 26).
Each black circle and white circle represent a single memory unit.In the figure, only the intersection of both boards is surrounded by a cubic box 27, and it is particularly noted that the overlapping black circle 24 and white circle 26 are a single memory unit. It is shown. On the real board 23,
A row bus 28 is formed as indicated by a solid line, whereby each memory unit on the board is connected to the PU (α) 22. PU
Based on the i-selection address from (α), each column vector
MU (i, ·, α) receives interleaved access. In FIG. 4, each unit arranged in each branch 29 connected to a common row bus 28 has a vector component. Which unit in the memory unit array each component occupies is specified by a point address from the PU (α) 22. On the virtual board 25, a column bus indicated by a double dashed line 30 is formed, whereby each memory unit 26 on the board 25 is connected to the PU (α) 22. J from PU (α)
Based on the selected address, each row vector MU (α, j ,.)
Receive interleaved access. In FIG. 4, each unit arranged in each branch 31 connected to the common column bus 30 has a vector component corresponding to a common point address.

Next, a description will be given of a parallel vector operation device based on an extended system which can be called a multiple array type of the parallel vector computer described above with reference to the drawings.

FIG. 5 shows that as an arithmetic unit, an arithmetic block (scalar arithmetic unit + vector arithmetic block) PB is 2 × 2 = 4 blocks, that is, PB (J, K), J, K = 1,2 and the main memory is 2
× 2 × 2 = 8 blocks, ie, MB (I, J, K), I, J, K
1 shows a conceptual configuration in the case of = 1,2. In the following, focusing on the vector system, the arithmetic unit is referred to as a vector processor. (J, k) plane 3 on the left side of the drawing
Above 2, four processor blocks 33 are depicted. In the processor block, N vector processor units 22 shown in a bar shape are arranged. Also, (i,
(j, k) A main storage device is a collection 35 of several memory boards 34, which are drawn in a hollow shape in the space. In the figure, in order to avoid complexity, only the vector processor having the largest number “α” and the row bus connecting the main memory board are indicated by solid lines 36 in block units. The unit of a vector to which each tooth drawn in a comb-teeth shape on the memory board 34 is accessed is shown. Similarly, the broken line 37 indicates only the vector processor having the largest number “α” and the column bus connected to the vertical (virtual) memory board of the main memory which has the largest number of i. In this case as well, each tooth drawn like a comb in the memory board group 35 is a unit of a vector to be accessed. This is because the term “virtual” refers to a set of memory unit rows that are formed in a vertical plane in the form of skewing real memory boards. About row bus (solid line), PB (1,1) and MB (1,1,1), MB (2,1,1), PB (2,1)
MB (1,2,1), MB (2,2,1), PB (1,2) and MB (1,1,2), MB
(2,1,2), and PB (2,2) and MB (1,2,2), MB (2,2,
2) leads. PB (1,1) for the column bus (dashed line)
And MB (1,1,1), MB (1,2,1), PB (2,1) and MB (1,1,2), M
B (1,2,2), PB (1,2) and MB (2,1,1), MB (2,2,1), and PB (2,2) and MB (2,1,2) , MB (2,2,2) is connected.
In this way, in an arithmetic unit in which a vector processor having a double vector length is doubled in combination, the arithmetic unit having the basic configuration shown in FIGS. An extended computing device with high-speed performance is created.

Example 1 This, p of M = pN defining a memory unit line M ³ is an example of a case 1. As shown in FIG. 6, in this implementation example, a processor PU101 that performs a vector pipeline process of a vector length of 16 words (1 word and 64 bits) and 16 × 16 = 2
An array of 56 memory units (64 k words per memory unit) is mounted on one board, and all the row buses 102 are arranged on the board. The processor can perform vector access to the 16 memory unit length strings 103 on the same board. Also, each of the columns of the unit has an edge terminal that connects to a common column bus 104 and that the 16 column buses connect outside the board. A total of 256 terminals, 16 terminals per board, for 16 boards, and 16 column bus terminals of the vector processor are inserted into one motherboard 105. Column bus wiring is performed on the motherboard. In this case, since the column bus wiring length is longer than the row bus, it is necessary to provide a difference in the margin of the access time. The main storage capacity is 256M words in total.

Implementation Example 2 This implementation example is a second example in the case of p = 1 as well. As shown in FIG. 7, four vector operation units 20 are used.
Vector memory unit 202 with 1 and 4 units each
Are arranged on the same board. Both the row bus 203 and the column bus 204 can be wired on the same board, so that problems relating to main memory access are reduced.

Implementation Example 3 This example is also a parallel vector computer according to the basic form of the present invention, but is an example when p = 2. As shown in FIG. 8, this shows a system that has the same main storage capacity as that of the implementation example 2 and is based on vector calculation in units of 8 units with two vector operation units 301. That is, a vector memory unit 30 having a length of 4 units
2 is combined two by two to store a vector of length 8. For this purpose, the connection between the row bus 303 and the column bus 304 is devised.

Implementation Example 4 This is an extension of the so-called basic form (L ² , L ³ )
This is an example of the system, and as shown in FIG. 9, a (2 ² , 2 ³ ) system using a unit corresponding to p = 4 having a single vector processor in the unit processor section. A single vector processor can access a vector memory unit column (vector length, 4) for 4 columns (vector length, 16) per block. Processors 401 and 402 each have a row bus 403
And 404, a typical vector memory column (vector length, 32) accessed in parallel is indicated by r in the figure. Similarly, processors 401 and 402 have column buses 405 and 4, respectively.
A typical vector memory column (vector length, 32) accessed in parallel using 06 is indicated by c in FIG.

Effects of the Invention (Performance Evaluation) A system that is sufficiently possible at the current technical level and is considered to be practically used as a next-generation supercomputer is presented, and its performance is evaluated.

(1) When N = 16 and p = 4 in a parallel vector computer of the basic type (1 ² , 1 ³ ), a single vector computer requires 64
A plurality of word registers (one word is 64 bits) are held, and the machine clock is 3.125 ns. This means that it has the ability to perform 320 million floating point operations per second (320 MFLOPS) when repeating simple operations on infinite length vectors. On the other hand, a column vector bank (or row vector bank) having a length of 64 units is arranged in the main memory vector bank unit, and the access time of each element memory unit is 200 ns. (This value is a normal level. It aims at minimizing power consumption by CMOS technology or the like.) Since p = 4, four column vector banks (or row vector banks) are used. Provides four paths, each 64 bits wide. At this time, the maximum bandwidth of the main storage vector bank is 1.28 G words.

To see the effective performance of a single vector computer, simple four arithmetic operations on the components of the vector, for example, a) Ai ^(p) + Bi ^(p) → Ci ^(p) (i = 1,2,3, ..., 64) Or b) ^Let the form of A ^(p) + Bi ^(p) → Ci ^(p) be repeated with p = 1,2,3,4,1,2,3,4, ... At this time, 64 words of memory access and operation , The flow of calculation is expressed as follows.

Here, L means loading from the main storage bank to the vector register, R means the stage of deriving the calculation result (Result), and S means storing from the vector register to the bank. Looking at the effective speed where repetition continues in a steady state, a) is 160 MFLOPS since 64 floating operations are performed in 400 ns, and b) is 320 MFLOPS since b) is performed 64 floating operations in 200 ns.

An effective performance of a) 2.56 GFLOPS b) 5.12 GFLOPS is obtained in the entire parallel system including N = 16 vector computers.

(2) An extended type (L ² , L ³ ) type parallel vector computer, in which the above (1) is used as a unit system, and when L = 2, the effective speed for the above operations a) and b) Is four times the performance of (1), and a) 10.2
4GFLOPS b) It becomes 20.48GFLOPS.

These performances show that the parallel vector computer of the present invention promises the next generation supercomputer.

[Brief description of the drawings]

1 (a), 1 (b) and 1 (c) are schematic diagrams respectively showing three logical arrangement states of a basic configuration in a parallel computer of the present invention, and FIG. 2 is a block diagram showing an entire system of the basic configuration. FIG. 3 is a diagram showing the functional configuration of one vector unit PU, FIG. 4 is a schematic diagram showing a cubic arrangement of memory units and a pattern of bus connection with one vector unit, and FIG. FIG. 6 and FIG. 7 are schematic diagrams showing two implementation examples of a parallel vector computer (when p = 1) having a basic configuration, and FIG. 8 is a schematic diagram of a bus connection in a system example in which basic configuration blocks are combined. Similarly, FIG. 9 is a schematic diagram showing an implementation example of p = 2, and FIG. 9 is a schematic diagram showing an implementation example of a parallel vector computer in an extended form. DESCRIPTION OF SYMBOLS 1 ... Bus and communication line 2 ... Front end computer 3 ... Control processor (CU) 4 ... Program memory (CM) 5 ... Signal line 6 ... Scalar operation unit 7 ... Vector operation block 8 ... Scalar memory (PM) 9: Vector memory unit (MU) 10 to 14: Data bus and communication line

Claims (2)

(57) [Claims] 1. A high-speed computer for use in addition to a front-end processor comprising a general-purpose computer, comprising: (a) a control unit CB comprising a control processor CU and a CU storage device CM; (A certain natural number) parallel processing vector processors PU [α] (α = 1,2,…, N) and each
Scalar memory PM that holds scalar data for PU
[Α] (α = 1,2, ..., N) the processor unit consisting of PB, as well as cubic array of memory units MU each M ³ months with a constant storage capacity (M = pN, also natural numbers with p) {MU [I, j, k],
Main memory vector bank MB consisting of i, j, k = 1,2,…, M｝
(B) the control processor CU is directly connected to a front-end processor to mediate input and output of data and the like, and has an instruction decoding device for decoding a program on the CU storage device CM. And the same control command sequence is transmitted to all the vector processors PU to instruct synchronous parallel operation. (C) Each vector processor PU includes a scalar operation device and a fixed-length vector pipeline. (D) Each PU [α] has an MB number corresponding to the number.
2 in the ij plane of the _q (= p (α-1) + q) layer
Dimensional subarray {MU [i, j, _q ], i, j = 1,2, ..., M}
1, 2,..., P, and connected via a set of high-speed “row” buses (where i-direction is “row”), a column vector (eg, j
Column vector bank is a sequence of a "column" direction) {MU [i, 1, 1], MU [i, 2, 1], ..., MU [i, M,
_{1], MU [i, 1} , 2], MU [i, 2, 2], ..., MU [i, M,
₂ ], ..., MU [i, 1, _p ], MU [i, 2, _p ], ..., MU
[I, M, _p ]｝, i = 1,2, ..., M, vector data access by interleave method, PU [α]
⇔MU [i, j, _q ] is possible, and (e) In another aspect, each PU [α]
The two-dimensional partial array {MU [ _q , j, k], j, k = 1, 2,..., M} in the ik plane of the _q (= p (α-1) + q) column is represented by q
= 1,2, ..., p, and connected through another set of high-speed "column" buses (again, j-directions are "columns") to form a vertical vector of memory units. A vertical vector bank {MU [ ₁ , j, 1], MU [ ₁ , j, 2],... MU
[ ₁ , j, M], MU [ ₂ , j, 1], MU [ ₂ , j, 2],…, MU [
₂ , j, M],…, MU [ _p , j, 1], MU [ _p , j, 2],… MU
For each of [ _p , j, M]｝, j = 1,2, ..., M, vector data access by the interleave method and PU
[Α] ⇔MU [ _q , j, k] is possible, (f) since every PU performs parallel operations while accessing MBs in parallel through each set of row buses in the above item (d). A row operation and a column operation consisting of performing a parallel operation while accessing the MB simultaneously and in parallel through each set of column buses in the above item (e), in a time-division manner. SIMD parallel vector calculator. 2. A control unit CB comprising a control processor CU and a storage device CM for CU, and N (a predetermined natural number)
Vector processors PU [α] (α = 1,2,
, N) and a processor unit PB consisting of a scalar memory PM [α] (α = 1, 2,..., N) for holding scalar data for each PU, and ^two L units are arranged as a unit. ｛(CB [J,
K], PB [J, K ]), J, K = 1,2, ..., the memory unit MU of the set of L}, M ₃ months, each with a predetermined storage capacity (M = pN, natural numbers is also p) ｛MU [i, j, k], i, j, k = 1,2, ...,
L ³ in units of main memory vector bank MB consisting of M｝
Individually cubically arranged {MB [I, J, K], I, J, K = 1, ..., L}, and (b) CU in all CBs is It is directly connected to the front-end processor to mediate input / output of data, etc., and has an instruction decoding device that decodes the same program on the CU storage device CM.
The B｝ pair performs a parallel synchronous operation according to the clock signal of the front-end processor. (C) Each vector processor PU has a scalar operation device and a constant-length vector pipeline operation device, (D) PU [α] belonging to each PB [J, K] is the row {MB of the main storage vector bank corresponding to the number pair [J, K].
I-th of the _q-th (= p (α-1) + q) layer of the MB in each of [1, J, K], MB [2, J, K],..., MB [L, J, K]}
Two-dimensional sub-array in the j-plane ｛MU [i, j, _q ], i, j = 1,2,
..., M} for q = 1,2, ..., p can be accessed via a common set of high-speed "row" buses, and for a selected MB the memory in that MB column vector of unit (however, j direction and "columns") column vector bank _{{MU [i, 1, 1} ] is a sequence _{of, MU [i, 2, 1} ],
..., MU [i, M, 1], MU [i, 1, 2], MU [i, 2, 2],
…, MU [i, M, ₂ ],…, MU [i, 1, _p ], MU [i, 2,
_p ], ..., MU [i, M, _p ] i, i = 1,2, ..., M, vector data access by interleave method, PU [α] ⇔MU [i, j, _q ] It is possible to perform parallel vector access for all the PUs over the entire PB in parallel, and (e) PU [α] belonging to each PB [K, I] has its number pair [ K, I] column of the main storage vector bank (MB
[I, 1, K], MB [I, 2, K], ..., MB [I, L, K] of the MB in the respective} The _{q (= p (α-1} ) + q) th column i-
Two-dimensional subarray in the k-plane ｛MU [ _q , j, k], j, k = 1,2,
.., P are accessible via a common set of high-speed “column” buses and the memory in that MB for the selected MB A vertical vector bank ｛MU [ ₁ , j, 1], MU [ ₁ , j, 2], which is a sequence of vertical vectors (where k is vertical) composed of units
…, MU [ ₁ , j, M], MU [ ₂ , j, 1], MU [ ₂ , j, 2],…, M
U [ ₂ , j, M], ..., MU [ _p , j, 1], MU [ _p , j, 2], ... MU
For each of [ _p , j, M]｝, j = 1,2, ..., M, vector data access by the interleave method and PU
[Α] ⇔MU [ _q , j, k] is possible, and these PUs perform vector access in parallel over the entire PB in parallel. (F) All PBs A row operation consisting of a parallel operation while simultaneously accessing a main storage column vector bank through a row bus leading to a column bus, and a column operation consisting of a parallel operation while simultaneously accessing a main storage vertical vector bank through a column bus. A SIMD parallel vector computer characterized by being realized in a divided manner.