JP2599679B2 - Multi-quadrant multiplier operating in charge domain - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-quadrant multiplication device operating in a charge region applicable to analog signal processing, a neural network circuit, and a multiplication device.

[0002]

2. Description of the Related Art Conventionally, charge transfer devices typified by CCDs have been widely used in the form of imaging devices and delay lines, but their applications are currently limited to analog shift registers and analog memories. Although some applications to matched filters and multi-valued digital logic circuits are being studied, their use in such signal processing fields is extremely small.

[0003] CCDs are generally said to have excellent characteristics in that power consumption is low and high-density integration is possible.
The establishment of more advanced signal processing functions is expected. In particular, with respect to multiplication between signals, at present, a sufficiently rational implementation method has not been proposed due to lack of accuracy and complexity.

For example, in the CCD matched filter shown in FIG. 6, the filter characteristics are adjusted by the shape of a pair of floating electrodes arranged on a CCD analog shift register, and the charge signal on each stage and the area of the electrode are adjusted. Analog multiplication is performed in parallel at each stage using the function indirectly, and the operation speed is relatively high.However, since errors in the electrode area directly affect the individual multiplication accuracy, However, as the circuit becomes finer, the calculation accuracy tends to deteriorate, and it is considered that high-density integration has a limit. Also, with this method, the multiplier cannot be changed,
The range of applications is quite limited.

[0005] The use of a CCD in a multi-valued logic circuit is as follows.
While we are currently exploring the basic logic operations, the prospect of achieving advanced processing like a multiplier is:
Still unknown.

In addition to this, for example, a Hopfield type neural network using a CCD has been studied. In this case, the main element of the multiplication is a resistance network and an operational amplifier, and the CCD stores these parameters. It is just an analog memory to make it work and is not used as an arithmetic function.

[0007]

SUMMARY OF THE INVENTION The present invention relates to a charge region for realizing high-precision analog multiplication with a simpler circuit mainly by directly multiplying a charge signal transmitted by a charge transfer element by a digital signal. The goal is to obtain a multi-quadrant multiplying device that works.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned point of view, and comprises a separator device for dividing a charge signal on a charge transfer element into at least two portions having a specific ratio. And an output circuit group for selectively applying the divided charge signals to a common addition circuit, and a digital signal line for controlling the selection. It is assumed that.

[0009]

Next, the operation of the present invention will be described. CCD
Is a representative element of a charge transfer element (CTD).
In the structure of the CD, a thin insulating layer was provided on the surface of a semiconductor region surrounded by an inactive region, a plurality of gate electrodes were continuously arranged with the insulator interposed therebetween, and an appropriate potential was applied to these electrodes. At this time, a charge signal injected into a depletion layer (potential well) which is excessively generated in a closed region inside the semiconductor due to the electric field causes a deformation (expansion) of the closed region caused by an appropriate operation of the gate electrode potential. , Reduction, etc.), and generally, two-phase, three-phase, or three-phase, based on the relative timing of the potential change of each gate electrode when focusing on the movement of the charge signal. 4
Classification such as phases is performed.

In the case of a CCD, when a plurality of gate electrodes adjacent to each other form a potential well, the potential wells are continuous and form one large potential well. An independent storage unit of one analog charge signal, including a continuous potential well, is generically called a stage hereinafter.

Hereinafter, the theoretical configuration of the operation will be described. One stage of the charge transfer element plays a role equivalent to a capacitor as a function of retaining electric charge, and its capacity is determined mainly by the area of the stage like a capacitor, but on a stage having sufficient accuracy, The electric charges are distributed almost uniformly, and when a potential is applied to the separator electrode arranged at the position where the stage is divided, the electric charge on the divided electrode is also divided in proportion to each divided area.

Various methods can be considered for this dividing method.
However, the simplest way is to use "n-division" with a radix of 2.
To illustrate by way of example, the above division is 1/2: 1/4: 1/8:. . . : 1/2ⁿ  And if the original charge amount is C, it is divided into n
The charged amounts are C / 2, C / 4, C / 8,. . . . . , C / 2ⁿ  Becomes

[0013] Here, binary n-bit digital signal to a _{d 0} and LSB D (dn-1, dn -2, .... d
The operation of selecting the above-mentioned n charge signals with each bit of (2, d1, d0) and accumulating only those whose bit is 1 is represented by the expression 1). Similarly, the operation of accumulating the bits of 0 is represented by Expression (2).

Specifically, for a 4-bit D, D and S1
The following table 1 shows the relationship between / C and S2 / C.

As can be seen from Table 1, when the outputs of the two systems are regarded as differential output signals (S1-S2) / C, the intermediate point between the digital data 7 and 8 is set as the neutral point, the lower part is negative, and the higher part is positive. In this device, "two-quadrant multiplication" in which the positive charge signal C is multiplied by digital data of both positive and negative polarities can be realized by this device.

Further, in the case where the input charge signals are the differential signals C1 and C2, when the processing of the equations (1) and (2) is applied to each input, the result is the following equation (3)- There are four types of outputs of (6).

Here, the total output signals S1 and S2 are represented by S1
= S11 + S22, S2 = S12 + S21, and the results of the above equations (3)-(6) are summarized as follows.
Equation (8) is obtained.

The second term on the right side in the above equations (7) and (8) is common and has no meaning as a differential signal, and can be ignored.
This is a formula in which C in formulas (1) and (2) is substantially replaced with (C1-C2).

From this result, this arithmetic processing is a processing of similarly providing differential outputs S1 and S2 corresponding to the product of the positive and negative differential input signals C1 and C2 with the bipolar digital signals. It is shown that.

Therefore, it can be seen that "four-quadrant multiplication" can be executed by combining two two-quadrant multipliers of the equations (1) and (2).

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a processing circuit according to an embodiment of the present invention; A charge transfer device (CTD) is generally configured based on an operation in which a charge amount modulated by an input signal is transferred from one stage to another stage, and various methods are derived from the difference in the moving mechanism. doing.

Since the present invention is a concept that can be applied irrespective of such a moving mechanism, a specific charge transfer mechanism between the stages is omitted in the following description for the purpose of avoiding complication. It is illustrated.

FIG. 1 shows an operation according to the above equation (1) performed by CT
4 shows an example of a circuit executed on D. In this example, the input charge is first injected into a separator formed on one stage 1 of the CTD. The separator is provided with a separator electrode G for dividing charges at a predetermined ratio, and at the time of charge injection, the electrode G is kept at a neutral potential and no barrier is formed. After the completion of the charge injection, a potential is applied to the electrode G, and the charge in the stage 1 is divided at a predetermined ratio by the barrier.

Each of the divided charge signals is moved to an independent CTD stage 2. The CTD stage 2 is controlled by each bit of the digital signal D. Is configured to be moved to the summing node 3, and conversely,
The signal held by the stage whose bit is 0 is not used, and is discharged from the CLR terminal 4 at the same time as the next input is injected.

As a result, the summing node 3 has the formula (1)
Are output, and a signal corresponding to the equation (2) is output from the CLR terminal 4 with a delay.

The example shown in FIG. 1 is a simple example for explaining the case of executing a multiplication for multiplying a positive analog value by a digital value. However, when the number of divisions is large, it becomes difficult to control the accuracy of the separator. As with the matched filter, there is a limit to miniaturization of the circuit.

FIG. 2 shows an example in which this point is improved. In FIG. 2, an input charge signal is applied to n 分割 -divided separators 11 that divide the input charge in series into two equal parts, and are applied to a separator electrode G commonly arranged on each separator 11. According to the divided gate potential VG, each is independently divided into two equal parts. One of the outputs is transferred to the next-stage separator 11 by an operation of shift 0 as an input signal of the next-stage separator 11, and the other output is output. Is
As in the case of FIG. 1, while being controlled by each bit of the digital signal D, the shift register array 14 is controlled via the independent CTD stages Ri + and Ri- corresponding to the bit 0/1.
The above are accumulated respectively, and finally collected in the two systems of summing nodes 12 and 13 respectively. At this time, the shift register array 14 shifts (shift 1) adopts a configuration in which shift 0 is performed twice during one time. That is, this circuit is configured to execute signal processing corresponding to both of the above-described equations (1) and (2) in parallel.

In this configuration, since the operation is performed only by the operation of dividing the electric charge into two, the electrode size becomes uniform, so that the division accuracy can be easily controlled and is suitable for miniaturization of the circuit. In this case, since the bit selection output from each separator stage is not output at the same time, in this example, another CTD shift register row 14 which operates in synchronization with data movement between separators is used.
Is used to dynamically accumulate the results while moving the accumulated data.

FIG. 2 shows an example in which the charge signal injected from the input gate is multiplied by a 7-bit digital signal D (1, 0, 0, 1...) At the timing indicated by <*>. The operation will be described with reference to FIG. First, the injected charge has the first 1 because the divided gate potential VG is neutral.
The dispersion is performed over the entire area of the stage constituting the / 2 split separator 11. Thereafter, the divided gate potential VG forms a barrier in the separator, and halves the injected charge. One of the separated charge signals is connected to two stages or transfer channels indicated by R6 + and R6-, and is additionally injected into another CTD shift register row 14 via either of them. However, here, the most significant bit (MS
B) is 1, the first charge signal divided into two is R
It is assumed that it is configured to be transferred via a 6+ path.

The other divided signal is supplied to a second-stage half-divided separator 11 in synchronization with the injection of the next charge signal.
Is transferred to the CTD shift register row 14 from the stage of R5- in correspondence with the bit 0 next to D as described above.
4 moves to the right by two stages by the drive of the shift 1, and moves rightward while being added to the signal injected by the first separator.

After repeating the above process, the rightmost two summing nodes 12, 1
Finally, the signals shown in the above equations (1) and (2) are accumulated and output to No. 3. The processing of another input signal input before and after * is also performed independently in parallel with the above, so that this device functions as a kind of semi-analog pipeline multiplier.

FIG. 3 shows only one half of the example of FIG.
This is an example of a configuration in which a division separator is processed by time division multiplexing. In FIG. 3, the charge signal injected from the left end into the separator 21 is once diffused throughout the separator,
Thereafter, the divided gate potential V applied to the separator electrode G
The G-generated barrier is divided into two stages 22 and 23 each having an equal amount of charge signal.

The rightmost section in FIG. 3 is composed of two independent summing nodes 24 via two paths R + and R-, respectively.
25, and D1, D2
Is accumulated in any one of the summing nodes based on any one of the transfer commands. The transfer commands D1 and D2 are controlled by the most significant bit (MSB) of digital data which is a multiplier. Is the transfer instruction D1
However, when the bit is 0, the transfer instruction D2 is generated.

After the end of the transfer, the divided gate potential VG becomes the neutral potential again, so that the charge signal remaining in the left section of FIG. 3 is diffused to the entire area of the separator, and is again divided by the next rise of the divided gate potential VG. Is done.

The above operation is repeatedly executed while sequentially switching the control sources of the transfer commands D1 and D2 to the lower bits of the input digital data. When the accumulation operation is completed for all the bits, the two summing nodes 24 and 25 are completed.
Above, differential output signals corresponding to the above equations (1) and (2) are held.

In this example, 4-bit digital data is used as the multiplier. However, as can be seen from the results shown in Table 1, in this case, it is impossible to perform multiplication using a multiplier of completely zero. For this reason, in the example of FIG. 3, a configuration is adopted in which, after a series of halving processes, the charge signal remaining in the left section is finally discharged through the R-path. The neutral point is adjusted to exactly 8.

In the case of the example shown in FIG. 3, digital data having an arbitrary bit length can be theoretically handled only by adjusting the number of halving operations by software, which is excellent from the viewpoint of flexible operation of the apparatus. It has the simpler circuit configuration than the example of FIG. 2 and is most suitable for application to a high-density integrated circuit. Further, since there is only one separator, the configuration is extremely advantageous in terms of accuracy control. In particular, it is easy to use the division ratio eye movement adjusting system as shown in FIG.

In FIG. 4, the charge signals of the two summing nodes are directly or indirectly transmitted to the comparator X, and the relative relationship between them is detected, for example, in the form of a difference. If 8 is selected as the multiplier, ideally the outputs of the two summing nodes should eventually be equal. However, if the division ratio of the separator is different from 1/2 and has an error, Since the difference does not become zero and becomes a finite numerical value indicating the error tendency inherent in the separator, it is possible to improve the accuracy of the dividing ratio by adding feedback control to the fine adjustment device of the dividing ratio of the separator from this numerical value. it can.

In the example of FIG. 4, an electrode GA for fine adjustment is provided in a part of the half-divided separator, the electric capacity of one section of the separator is controlled, and the feedback signal is applied to the control voltage. The case where it is realized by the configuration is shown. Of course, since this control is effective only when the digital data is 8, it is necessary to cut off the feedback circuit while maintaining the adjustment result after the ratio calibration, and the terminal CAL indicates a control terminal for that.

FIG. 5 shows a configuration of a system for performing four-quadrant multiplication corresponding to the above equations (7) and (8) by combining the example shown in FIG. 3 in two series. The differential input signals C1 and C2 are applied to the respective series of multipliers, but the internal operations applied to each are exactly the same as in the example of FIG. The respective differential outputs are mutually summing nodes 31, 32
The above is added to form a total differential output of S1 and S2.

[0041]

According to the present invention, a multi-quadrant multiplying device, which is low in power consumption and is difficult to realize using the CTD in the prior art using the CTD which is advantageous in terms of the integration density, is extremely compared with the conventional multiplying device. It can be configured with a simple circuit, which helps to reduce the circuit size.

Further, the multi-quadrant multiplication device according to the present invention has a configuration in which a charge input is directly received and all multiplication processes can be executed in a charge region. The ability to fully utilize the low power consumption characteristics of CTD, such as no need to install
Another important advantage is that there is no need for any signal conversion between charge and voltage, which contributes to a decrease in accuracy.

The multi-quadrant multiplication device according to the present invention is suitable for constructing a massively parallel analog processor chip centering on the product-sum processing from the above-described characteristics, and further, as an optical signal input device which has been a main application of the conventional CTD. By using these functions together, it can be effectively used for applications such as image processing and neural networks.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of one embodiment for executing a predetermined operation of the present invention on a CTD.

FIG. 2 is a circuit configuration diagram of another embodiment of the present invention.

FIG. 3 is a configuration diagram of an example in which the example of FIG. 2 is processed by using only one half-split separator by time division multiplexing.

FIG. 4 is a configuration diagram illustrating a division ratio automatic adjustment system according to an embodiment of the present invention.

FIG. 5 is a configuration diagram of a system that performs a predetermined four-quadrant multiplication by combining two examples of the example illustrated in FIG. 3;

FIG. 6 is a configuration diagram showing an example of a conventional CCD matched filter.

[Explanation of symbols]

1 stage 2 CTD stage 3 summing node 4 CLR terminal 11 1/2 splitting separator 12 summing node 13 summing node 14 shift register row 21 separator 22 stage 23 stage 24 summing node 25 summing node 31 summing node 32 summing node CTD charge transfer element D Digital signal VG Divided genito potential Rx + Transfer channel Rx on the plus side, controlled by bit x of digital data, Transfer channel on the minus side, controlled by bit x of digital data MSB Most significant bit LSB Least significant bit G1, G2 Comb separator G Separator electrode D1, D2 Transfer command X Comparator GA Fine adjustment electrode CAL Calibration control terminal C1, C2 Differential input signal S1, S2 Differential The Power C input charge signal

Claims (5)

(57) [Claims] An input charge signal on a charge transfer element is divided by 1 /
2, 1/4, 1/8,... 2 ^(-n) (n is an arbitrary natural number), a separator device for dividing into two or more portions having a ratio, and a separate digital signal for the divided charge signals. 2 selectively according to a selection control signal supplied through a signal line.
An output circuit group to be applied to any of the two types of adder circuits, and a charge region which forms a differential output signal expressing both positive and negative polarities by two charge output signals from the two types of adder circuits. A working two-quadrant multiplier. 2. A two-quadrant multiplier operating in a charge domain according to claim 1, wherein said separator device simultaneously divides the input charge into n parts. 3. The above-mentioned n = 2, that is, m separator devices for bisecting an input charge signal are connected in series, and at each connection stage, one of the divided outputs is used as the input of the next stage, and n is sequentially determined.
A separator device that repeats a half-split operation twice, and selectively accumulates and adds the other divided output from each stage of the separator device according to digital signal bits, and performs a soft operation in synchronization with the split operation of the separator device. 2. A two-quadrant multiplication device operating in a charge domain according to claim 1, comprising an analog shift register to be implemented. 4. One of the divided outputs of one separator device for dividing n = 2, that is, the input charge signal into two equal parts, is again input to the separator device, and the n divided operations are sequentially performed n times. 2. The charge according to claim 1, comprising: a cyclic separator device that repeats the above operation; and two charge signal accumulating means for selectively accumulating and adding the output of the cyclic separator device according to a digital signal bit supplied with the most significant bit at the top. A two-quadrant multiplier operating in the domain. 5. A two-quadrant multiplying device according to claim 4, wherein two charge signals in a differential form, that is, a charge form in which a signal having both positive and negative polarities is represented by a difference between the two signals, As a result of performing multiplication independently as an input charge signal of each of the two, the two elements of the two differential outputs output from the respective multipliers are added to each other to form a single differential output signal 4-quadrant multiplier operating in the domain.