JP2595169B2 - Plant safety protection system safety protection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a security device is operated in the pulp plant safety protection system on the safe side the load when a failure occurs in the device.

[0002]

2. Description of the Related Art Fail-safe circuits have been applied to various fields including railways. One example is
There is a fail-safe load control device described in Japanese Patent Application Laid-Open No. Sho 60-222923. In this prior art, the operation of an oscillator that outputs a high-frequency signal is controlled by a relatively low-frequency pulse signal output from a microcomputer. Therefore, if the pulse signal which is the output of the microcomputer is stopped and the output signal is stuck at a logic "1" or "0", the output of the oscillator is stopped. When the output of the oscillator is a pulse signal, a DC voltage rectified by the rectifier circuit and the smoothing circuit via the pulse transformer is obtained. The load is driven by this DC voltage, but if the output of the pulse signal stops, no DC voltage can be obtained, and the load operates on the safe side. However, the pulse output from the microcomputer is not directly input to the oscillator, but is input via a filter having a constant time constant.

Another prior art for determining whether an abnormality has occurred in a control microcomputer is disclosed in Japanese Patent Application Laid-Open No. Sho 61-43348. In this prior art, a signal of a predetermined frequency is output from a control microcomputer, and it is determined by a comparator whether or not the frequency of this signal is within an allowable range. If the frequency is within an allowable range, a logic "1" is output. Then, when the value deviates from the allowable range, the control microcomputer is made to output logic "0" as an abnormality has occurred.

[0004]

SUMMARY OF THE INVENTION The above-mentioned Japanese Unexamined Patent Publication No.
In the prior art described in Japanese Patent No. 229102, a filter is provided between the output of the microcomputer and the input of the oscillator. For this reason, even if the pulse output of the microcomputer is stopped, the oscillation of the oscillator is stopped with a delay corresponding to the time constant of the filter, so that the response of the entire system is delayed. Also, even if an abnormality such as an increase in the frequency of the output pulse from the microcomputer occurs, the oscillator does not stop in response to this abnormality, so the oscillator continues to oscillate and the load continues to operate. However, fail-safe performance is not ensured.

The prior art described in Japanese Patent Application Laid-Open No. 61-43348 has a configuration in which a program for outputting a signal for fail-safe determination separately from a load control signal from a control microcomputer is periodically executed. However, the determination of fail-safe is not made directly by the load control signal. That is, it is indirectly determined whether or not an abnormality has occurred in the control microcomputer. Therefore, even if no abnormality is found in the output of the determination signal, an abnormality may occur in the control signal.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-speed response that does not cause a delay in system response, and a reliable safety protection that can reliably operate a fail-safe function when an abnormality occurs in a load control signal. It is to provide a device.

[0007]

SUMMARY OF THE INVENTION The above objects are achieved by a security device for generating a switch of the DC driving voltage for controlling the load of the plant safety protection system, whether the frequency of the input signal is within the reference range Frequency monitoring means for monitoring, gate means for outputting the input signal only when the frequency monitoring means detects a frequency within a reference range, and generating the DC drive voltage from an output signal of the gate means, in Rukoto and means for outputting to the switch is achieved (claim 1). The above objective is also intended to reduce the load on the plant safety protection system.
The DC drive voltage of the switch that controls the
Or rectify and generate an input signal consisting of
In the safety protection device, the frequency of the input signal is a reference.
Frequency monitoring means for monitoring whether the frequency is within the range,
Wave number monitoring means determines whether the frequency of the input signal is in the reference range.
Rectification of the input signal when the deviation is detected.
And gate means for blocking output to the means,
Is achieved (claim 2).

The above object is also achieved by a rectangular wave signal or an AC signal.
Use the signal as an input signal and rectify the input signal for plant safety
As the DC drive voltage of the switch that controls the load of the protection system
In the output safety protection device, the frequency of the input signal
Monitoring means for monitoring the frequency, and monitoring of the frequency monitoring means
When the frequency is within the reference range,
The generated DC drive voltage is output and the frequency is
When the input signal deviates from the reference range, the input signal is
Means to control the load on the safe side.
(Claim 3) .

The above object is also achieved by a rectangular wave signal or an AC signal.
A frequency that takes a signal as an input signal and monitors the frequency of the input signal
Number monitoring means, and the frequency monitoring means
Output the input signal when the
A gate that shuts off the output when the value deviates from the reference range
Means, and an AC component of the output signal from the gate means.
And the output signal of this transformer is rectified
DC of the switch that controls the load on the plant safety protection system
By providing rectification means that outputs as drive voltage,
(Claim 4) .

The above object is also achieved by a rectangular wave signal or an AC signal.
A frequency that takes a signal as an input signal and monitors the frequency of the input signal
Number monitoring means, and the frequency monitoring means
Output the input signal when the
A gate that shuts off the output when the value deviates from the reference range
Means, and a DC component of an output signal from the gate means.
Transformer to cut and output, and output signal of the transformer
Switch that rectifies the load and controls the load on the plant safety protection system
Rectifying means for outputting as a DC drive voltage of
(Claim 5) .

The above object is also achieved by a rectangular wave signal or an AC signal.
A frequency that takes a signal as an input signal and monitors the frequency of the input signal
Number monitoring means, and the frequency monitoring means
Output the input signal when the
A gate that shuts off the output when the value deviates from the reference range
Means, and an AC component of the output signal from the gate means.
And the output signal of this transformer is rectified
DC of the switch that controls the load on the plant safety protection system
Rectifying means for outputting a driving voltage;
The output signal of the stage deviates from the reference range of the input signal
A first diagnostic means for outputting a fault occurrence when
The DC voltage output from the rectifier is monitored and the DC voltage is
The second diagnosis that outputs a failure occurrence when the voltage does not reach the predetermined voltage
This is achieved by providing a disconnecting means (claim 6) .

[0012] The above-mentioned object is also intended to reduce the safety of
Safety protection device with fail-safe circuit to control load
A square wave signal or
Transmits an AC signal and generates a trip signal when the
Frequency generating means for interrupting a signal;
The received signal is converted to an optical signal, propagated through an optical cable, and received.
An optical transmission system for converting the optical signal into an electrical signal on the transmitting side;
Input the signal received through the transmission system and converted to an electric signal
7. The signal according to claim 1, wherein the signal is a signal.
Achieved by providing all protection devices (claim
7) .

[0013]

[Function] Generates the DC drive voltage of the switch from the input signal itself.
Monitor the frequency of the input signal and
When deviating from the box, shut off the output to the subsequent stage of the input signal.
Switch off DC drive voltage output
The safety protection device is more fail-safe and reliable.
Further improve. Set the reference frequency to a relatively high frequency
By setting, deviation from the reference range is instantaneous
Detection, and the responsiveness of the system can be increased .

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. In the configuration of each embodiment shown in each drawing, the same reference numerals are given to the same components or corresponding parts.

FIG. 1 is a configuration diagram of a safety protection device (hereinafter, also referred to as a fail-safe circuit) according to a first embodiment of the present invention. The fail-safe circuit according to the present embodiment includes a frequency monitoring unit 14 that monitors the frequency of an input signal, a signal amplifying circuit 4 that amplifies an output signal of the frequency monitoring unit 14,
The rectifier circuit 1 includes a transformer 5 that receives the output signal of the frequency monitoring unit 14 amplified by the signal amplifier circuit 4 and a rectifier circuit 11 that rectifies the output signal of the transformer 5.
The switch 9 is driven by the DC voltage which is the output of
0 and power supply 8 (AC or DC power supply, load 1
The type of the power supply is determined according to the type of the drive voltage of 0. )
It is designed to control the connection with. Rectifier circuit 11
Is a signal rectifier 6 for rectifying an output signal of the transformer 5,
Consists of a capacitor 7.

The transformer 5 that outputs the drive voltage for the switch 9 outputs the drive voltage for the switch 9 if the signal input to the transformer 5 is an AC or pulse signal, but the input signal is cut off or becomes DC. When an abnormality occurs, the drive voltage of the switch 9 is not output, and the switch 9 controls the system to a safe side. However, transformer 5
However, even if an abnormality occurs in which the frequency of the input signal is out of the allowable range, the drive voltage of the switch 9 is continuously output as it is because the input is an AC or pulse signal. Therefore, in the fail-safe circuit of the present embodiment, the frequency monitoring means 14 is provided in a stage preceding the transformer 5.

The frequency monitoring means 14 according to the present embodiment includes a frequency tuning circuit 2 and a two-input AND gate 3, and a signal obtained by processing an input signal applied to an input terminal 1 through the frequency tuning circuit 2 and the input signal. The logical product with the signal is taken by the AND gate 3 and the output is inputted to the signal amplifying circuit 4.

The frequency tuning circuit 2 detects whether the frequency of the input signal is within an allowable range with respect to a predetermined reference frequency, and outputs a logic "1" if the frequency is within the allowable range, If the value deviates from the allowable range, the logic "0" is output. A PLL is used for the specific configuration of the frequency tuning circuit 2. PLL is superior in terms of high-speed response characteristics, safety, and miniaturization. There are various books on PLL, for example, "Basics and Application of PLL" published by Tokyo Denki University Press (March 15, 1978,
(1st edition 1st printing issuance) will be helpful.

The input signal applied to the terminal 1 is shown in FIG.
Suppose that the signal is a rectangular wave signal of the reference frequency until time t0, and thereafter an abnormality occurs in which the frequency falls outside the allowable range. Here, for simplicity,
An explanation will be given assuming that an abnormality that the frequency becomes infinite, that is, an abnormality that becomes a DC signal occurs. When the frequency of the input signal is out of the allowable range, the output signal of the frequency tuning circuit 2
(b). The output signal of the frequency tuning circuit 2 becomes logic “0” after a short time has passed after time t0, but this is a delay of the frequency tuning circuit 2. For example, when a PLL is used, the delay is delayed by the time related to the time constant of the low-pass filter constituting the PLL. However, if the reference frequency is set high, the time constant of the low-pass filter can be reduced. It can be shorter.

The AND gate 3 calculates the logical product of the input signal applied to the terminal 1 and the output signal of the frequency tuning circuit 2, and outputs the signal shown in FIG. This output signal is amplified by the signal amplifier circuit 4, applied to the rectifier circuit 11 via the transformer 5, and converted into a DC voltage by the rectifier circuit 11. Here, if the input signal is set to a rectangular wave signal having a frequency at which the transformer 5 does not saturate,
Also becomes a rectangular wave signal, and becomes a DC voltage by full-wave rectification by the rectifier 6. Actually, the rise and fall of the rectangular wave signal output from the transformer 5 are not completely vertical, but are slightly inclined. For this reason,
The DC voltage output from the rectifier 6 has a slight ripple. To suppress this ripple, a capacitor 7
However, for that purpose, the capacitor 7 may have a very small capacity, and it can be considered that there is almost no delay in fail-safe response. Therefore, the output signal of the rectifier circuit 11 is as shown in FIG.

The output signal of the rectifier circuit 11 is output to the switch 9 to control the load 10. The switch 9 is a semiconductor switch (IGBT, FE) when a high-speed response of the system is required or when the power capacity of the rectifier circuit is small.
T is valid). After the time t0, the DC voltage of the rectifier circuit is lost, so that the switch 9 operates and the load 10 operates on the fail-safe side.

With the configuration shown in FIG. 1, even if a failure occurs in which the output of the frequency tuning circuit 2 keeps the logic "1", if the input signal is a signal of the reference frequency, the rectifier circuit A DC voltage is obtained as an output, and the switch 9 continues to operate, so that there is no problem. When the frequency of the input signal becomes DC, the output voltage of the rectifier circuit is lost, and the switch 9 operates.

Even if a DC failure occurs in the circuits subsequent to the AND gate 3, the load can be operated on the safe side by the operation of the transformer 5 and the non-power supply configuration of the rectifier circuit.

A failure occurs in which the output of the frequency tuning circuit 2 remains at logic "1" and a failure occurs in which the frequency of the input signal deviates from the reference frequency. When an extremely low failure occurs, sufficient fail-safe performance cannot be ensured in the above-described embodiment. This is dealt with by adding a diagnostic circuit, which will be described later, to distinguish between the two faults and detect them in advance. In this case, if the frequency of the input signal changes to a value sufficiently lower than the reference frequency, only the rising and falling of the rectangular wave will be transmitted to the rectifier circuit 11 due to the saturation characteristics of the transformer. No DC voltage is obtained from the rectifier circuit 11, and a fail-safe operation is performed.

With the above-described configuration, high-speed response can be ensured, and a fail-safe operation can be realized even if a failure occurs such that the frequency of the input signal deviates from an allowable value.

FIG. 3 is a configuration diagram of a fail-safe circuit according to a second embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is that the input signal is an AC signal, and a waveform shaping circuit 13 is provided between the input terminal 1 and the AND gate 3. The waveform shaping circuit 13, the frequency tuning circuit 2,
The D gate 3 constitutes the frequency monitoring means 14.

If the frequency of the input AC signal is within the allowable range of the reference frequency, a signal of logic "1" is output from the frequency tuning circuit 2 as shown in FIG. Waveform shaping circuit 13
Shapes the waveform of the input AC signal and outputs a rectangular wave signal as shown in FIG. As a result, a signal shown in FIG. 4D is output from the AND gate 3. The operation of the circuits after the AND gate 3 is the same as that of the first embodiment shown in FIG. Therefore, even if the input signal is not a rectangular wave signal but an AC signal, a fail-safe operation with a high-speed response can be realized. If the frequency of the input signal deviates from the allowable range,
A fail-safe operation can be performed. In this embodiment, a sine wave AC signal is used as an input signal. However, even if the input signal is a triangular wave or other waveform signal, the waveform shaping circuit can output a rectangular wave signal from the input signal. Can be dealt with.

The same result can be obtained by providing the waveform shaping circuit 13 immediately after the terminal 1 and outputting the output signal of the waveform shaping circuit 13 to the frequency tuning circuit 2 and the AND gate 3. Can be In this case, the frequency tuning circuit 2
Is always a rectangular wave signal, so that it is sufficient to configure a frequency tuning circuit dedicated to this rectangular wave. According to the present embodiment, since the waveform shaping circuit 13 is provided on the input side of the frequency monitoring means 14, there is an effect that it is not necessary to limit the waveform of the input signal.

FIG. 6 is a configuration diagram of a fail-safe circuit according to a third embodiment of the present invention. This feature is that the frequency monitoring means 14 is constituted by the frequency tuning circuit 2 itself, and the input signal applied to the terminal 1 is a signal obtained by combining two frequency components, that is, a frequency-modulated signal.

In this embodiment, the frequency-modulated signal shown in FIG. This input signal has a frequency f1 (a value of 1 / ΔT1) and a signal having a frequency f2 (1 / ΔT2).
Is a signal modulated by the signal of Even if f2 is modulated by f1, the same input signal (FIG. 7A) is obtained. If the reference frequency of the frequency tuning circuit 2 is set to f1 within the allowable range, the output of the frequency tuning circuit 2 becomes logic "1" when this frequency f1 exists, and logic "0" otherwise. And the signal shown in FIG. 7B is obtained. If the frequency (1 / ΔT2 value) of the signal shown in FIG. 7B is determined in advance so as to match the transfer characteristic of the transformer 5, FIG.
Are obtained from the rectifier circuit 11. When the frequency of the input signal deviates from the allowable range after time t0, the output of the frequency tuning circuit 2 is fixed to logic "0" and the rectifier circuit 11
DC voltage is lost, and a fail-safe operation is performed.

When the input signal of the terminal 1 becomes a signal of only the frequency f1, the frequency tuning circuit 2 tunes to the signal of the frequency f1, and the signal of logic "1" is continuously output. As a result, the input signal of the transformer 5 becomes DC, so that a DC voltage from the rectifier circuit 11 cannot be obtained, and a fail-safe operation is performed. Conversely, when the input signal of the terminal 1 becomes a signal having only the frequency f2, the frequency tuning circuit 2
Synchronization with the signal of 2 stops, and the signal of logic “0” continues to be output. Also in this case, the DC signal is not obtained from the rectifier circuit 11 because the input signal of the transformer 5 is DC-like.
The operation becomes fail-safe.

In the present embodiment, the input signal is combined with a signal of a different frequency, that is, a so-called frequency-modulated signal, so that the normal operation mode is set only when both signals are correct, and the fail-safe operation is performed otherwise. become.

In the above description, the input signal is a rectangular wave signal. However, the present invention is not limited thereto. It works without any problem even if the signal is.

In FIG. 6, the DC detecting means 24 and the display means 25 connected to the output of the frequency tuning circuit 2 monitor whether the output of the frequency tuning circuit 2, that is, the frequency monitoring means 14 is DC, that is, abnormal. Means. The reason why the abnormalities can be monitored by the very simple means 24 and 25 is that the output of the frequency monitoring means 14 becomes a square wave signal only in a normal state. With this detecting means, it becomes possible to monitor the abnormality on the input side, including the frequency monitoring means 14.

FIG. 8 is a block diagram of a fail-safe circuit according to a fourth embodiment of the present invention to which a diagnostic circuit for evaluating the soundness of the fail-safe circuit is added. This is the same as the first embodiment.

NO provided at the output stage of the frequency tuning circuit 2
The T circuit 27 and the display means 28 connected thereto constitute a first diagnostic circuit including the frequency monitoring means 14 and provided for detecting an abnormality on the input side. When a failure occurs in which the frequency of the input signal deviates from within the reference range, the output of the frequency tuning circuit 2 is fixed to logic "0", which is a so-called logic "0" stuck-at fault. In this case, the output of the NOT circuit 27 is always "1", the display means 28 is turned on, and an abnormality can be detected. Since this diagnostic function can be realized by providing the circuits 27 and 28 at the output stage of the frequency tuning circuit 2, it can be applied to the second embodiment in FIG. It should be noted that when the frequency tuning circuit 2 fails in logic "1", it is necessary to distinguish it from the case where the frequency tuning circuit 2 operates correctly, which will be described later.

Further, in the fourth embodiment, the voltage detecting means 16 constituting the second diagnostic circuit is provided at the output stage of the rectifier circuit 11, and the DC voltage output from the rectifier circuit 11 is monitored, so that the rectifier circuit Abnormalities in the preceding stages, including 11, are detected. Normally, a DC voltage of a constant level is output from the rectifier circuit 11 as shown in FIG. When abnormal,
This DC voltage is lost. If the output of the frequency tuning circuit 2 is stuck at a logic "1" and the frequency of the input signal is sufficiently low, the output of the transformer 5 outputs only the rising and falling edges of the input signal.
Outputs a pulsed voltage or a voltage of almost 0 volts. Even when the voltage becomes pulsed, there is a time zone in which the voltage is about 0 volt. That is, if an abnormality occurs, the output voltage of the rectifier circuit 11 may be reduced to about 0 volts, and the voltage detector 16 detects the 0 volt voltage. .

The voltage detecting means 16 includes a resistor 26, an optical coupler 18,
It consists of a resistor 22 and a buffer 23. If the DC voltage of the rectifier circuit 11 is a predetermined voltage, the optical signal from the light emitting element 19 is propagated to the light receiving element 20, and the light receiving element 20 becomes conductive. As a result, the output of the buffer 23 becomes logic "0" and the display means 17
Does not show any abnormality. However, when the DC voltage becomes substantially 0 volt, no light signal is output from the light emitting element 19, so that the light receiving element 20 does not conduct. As a result,
The output of the buffer 23 becomes logic "1", and the display means 17 indicates an abnormality. Here, in order to hold this abnormality, a latch circuit may be provided at the output stage of the buffer 23.

As described above, by monitoring the level of the DC voltage from the rectifier circuit 11, it is possible to detect abnormalities in the preceding stages including the rectifier circuit. The second diagnostic circuit can be applied to the second embodiment of FIG. 3 and the third embodiment of FIG. 6 in the same manner.

FIG. 9 is a block diagram of a fail-safe circuit with a diagnostic circuit according to a fifth embodiment of the present invention. This embodiment is basically different from the fourth embodiment in FIG. 8 in that a test signal output means 31 for applying a short-time test signal to the frequency tuning circuit 2 is provided, and the frequency tuning circuit 2 for applying a test signal is provided. , A rectifier circuit 11 and a circuit for detecting each response of the switch 9.

First, the operation when the frequency tuning circuit 2 is normal will be described. The input signal shown in FIG. The frequency of this input signal is set within an allowable range of the reference frequency of the frequency tuning circuit 2. When the test signal shown in FIG. 10B is applied from the test signal output means 31 to the AND gate 29, the output signal of the AND gate 29 becomes as shown in FIG. As a result, the frequency tuning circuit 2
As shown in FIG. 10 (d), while the test signal is being applied (specifically, it is delayed by ΔT4), the tuning stops and a signal of logic “0” is output. The initial state of the output of the latch circuit 42 is logic “1”, and FIG.
As shown in (2), when the output signal of the frequency tuning circuit 2 falls from logic "1" to logic "0", the output becomes logic "0". The NOT circuit 40 and the delay circuit 41 output the output signal of the delay circuit 41 as shown in FIG.
The signal is delayed by ΔT3 due to 1. This ΔT3 is ΔT4
The setting is made longer so that the output signal of the latch circuit 42 does not overlap with the time when the output signal is at logic "1". As a result, the output signal of the AND gate 43 becomes as shown in FIG.
As shown in FIG. 10G, the logic is "0", and the output of the latch circuit 44 is also logic "0" as shown in FIG. Thus, the display means 30 can indicate that the frequency tuning circuit 2 is normal.

Next, a case where the output of the frequency tuning circuit 2 causes a stuck-at fault to logic "1" will be described. FIG. 11 (a)
11 (b) is applied to the AND gate 29, and the output signal of the AND gate 29 becomes as shown in FIG. 11 (c), regardless of this. The output signal of the frequency tuning circuit 2 has a stuck-at fault of logic "1" as shown in FIG. As a result, the latch circuit
The output signal of 42 remains at the initial value of logic "1". Since the signal shown in FIG. 11F is output from the delay circuit 41,
The output signal of the AND gate 43 is as shown in FIG.
As a result, the latch circuit 44 continues to output a signal of logic "1" after time t1. This signal is output to the display means 30, and the abnormality of the frequency tuning circuit 2 is displayed.

Further, a case where the output of the frequency tuning circuit 2 causes a stuck-at fault to logic "0" will be described with reference to FIG. FIGS. 12A to 12C are the same as FIGS. 11A to 11C. Since the output of the frequency tuning circuit 2 has failed to logic "0" as shown in FIG. 12 (d), the output signal of the latch circuit 42 has the initial value of logic "1" as shown in FIG. 12 (e). Will remain. Since the signal shown in FIG. 12F is output from the delay circuit 41, the output signal of the AND gate 43 is as shown in FIG. 12G. As a result, the latch circuit 44 continues to output a signal of logic "1" after time t1. This signal is output to the display means 30, and the abnormality of the frequency tuning circuit 2 is displayed.

Next, in the fifth embodiment shown in FIG. 9, the diagnosis of circuits upstream of the rectifier circuit 11, including the rectifier circuit 11, will be described. First, the case where all circuits are normal will be described. When the input signal shown in FIG. 13A is applied to the terminal 1 and the test signal shown in FIG. 13B is output, the output signal of the frequency tuning circuit 2 becomes the same as that shown in FIG. Become like Delay circuit 36
Outputs a signal delayed only when the test signal rises as shown in FIG. The rectifier circuit 11 is a frequency tuning circuit 2
13 (d), the output signal is as shown in FIG. 13 (f). As a result, the output signal of the voltage detection circuit 16 is
(g). As a result, the output of the AND gate 37 always becomes logic "0" as shown in FIG.
The output signal of 8 also becomes logic "0" as shown in FIG. Accordingly, the display means 46 indicates that no abnormality has occurred.

Next, a case where the input signal becomes abnormal will be described. It is assumed that the input signal applied to the terminal 1 is as shown in FIG. As a result, the output signal from the frequency tuning circuit 2 is as shown in FIG. Since the test signal is not output from the test signal output means 31 as shown in FIG. 14 (b), the output signal of the delay circuit 36 remains at logic "1" as shown in FIG. 14 (e). is there. Since the output signal of the rectifying circuit 11 becomes almost 0 volt at time t2 as shown in FIG. 14 (f), the output signal of the voltage detecting circuit 16 becomes
become that way. As a result, the output signal of the AND gate 37 becomes as shown in FIG.
As shown in (i), the signal of logic "1" is continuously output after time t2. The display means 46 displays at time t2 that there is an abnormality in circuits upstream of the rectifier circuit 11, including the rectifier circuit 11.

In the above-mentioned abnormal example, the case where the input signal becomes abnormal is shown. However, if an abnormality occurs such that the DC voltage of the rectifier circuit 11 is lost, the output signal of the voltage detecting circuit 16 becomes the signal shown in FIG.
Since it changes as shown in (g), it is possible to detect an abnormality based on this change.

Finally, the diagnosis of the circuits before the switch including the switch 9 will be described. First, the case where the entire circuit is normal will be described. When the input signal shown in FIG. 15A is applied to the terminal 1 and the test signal shown in FIG. 15B is output, the signal shown in FIG. Is output. The delay circuit 45 outputs a signal delayed by ΔT5 from the test signal of FIG. 15B, as shown in FIG. The rectifier circuit 11 outputs the voltage shown in FIG. 15F because the output signal of the frequency tuning circuit 2 has the waveform of FIG. As a result, the load current flowing through the load 10 is as shown in FIG. 15 (g), and this current is detected by the current transformer 47.

The signal detected by the current transformer 47 is input to the test signal output means 31 and the current change detection means 35. The test signal output means 31 determines whether the load current is zero based on the detection signal (time t3 in FIG. 15).
Then, a test signal is output. This is because the load current does not greatly change when a test signal is applied, and electromagnetic noise is not generated. If the power supply 8 is a DC power supply, this cannot be realized, so that it is not necessary to apply the output signal of the current transformer 47 to the test signal output means 31.

The current change detecting means 35 detects a change in current when a test signal is applied. For example, an input described in “Online Diagnosis Apparatus for Electromagnetic Devices and Their Drive Circuits” of Japanese Patent Application No. 1-232880 is disclosed. It can be constituted by current change detecting means using a signal following comparison circuit. In this case, the current change detection means 35
Is as shown in FIG. 15 (h). As a result, the output signal of the latch circuit 34 becomes as shown in FIG.
The output signal of the D gate 32 is as shown in FIG. Therefore, the output signal of the latch circuit 33 is as shown in FIG. 15 (k), and the display means 39 indicates that the entire circuit is normal.

Next, a case where the switch 9 has a closed fault will be described. When the input signal shown in FIG. 16A is applied to the terminal 1 and the test signal shown in FIG. 16B is output, the signal shown in FIG. 16D is output from the frequency tuning circuit 2 as in FIG. As a result, the output of the rectifier circuit 11 has the voltage waveform shown in FIG. Since the switch 9 has a closed failure, the load current is an alternating current that does not change at all with respect to the test signal during the period from time t3 to t4, as shown in FIG. For this reason,
The output signal of the current change detecting means 35 is as shown in FIG.
It always becomes a signal of logic "1". As a result, the output of the latch circuit 34 also remains at the logic "1" as shown in FIG.
The AND gate 32 outputs the signal shown in FIG. For this reason, the latch circuit 33 continues to output a signal that becomes logic "1" after time t4. The display means 39 displays after the time t4 that there is an abnormality in the circuits at the preceding stage including the switch 9. In this case, since the operation up to the rectifier circuit 11 is correct, the display means 46 indicates that the circuits at the preceding stage including the rectifier circuit 11 are normal. Therefore, it is possible to determine that the switch 9 is abnormal from the display results of the display means 46 and the display means 36.

In the above example, the case where the switch is closed is shown. However, when the switch is opened, no load current flows and the output signal of the current change detecting means 35 becomes the same as that shown in FIG.
A similar result is obtained, and abnormality of the switch 9 can be specified.

As described above, by applying a test signal having a time width during which the load does not operate to the input stage of the frequency monitoring means 14 and detecting the response of each circuit to this,
An abnormality in each circuit can be detected and displayed.

Further, although the fail-safe circuit shown in FIG. 9 is an example of the fail-safe circuit shown in FIG. 1, the circuits subsequent to the frequency monitoring means 14 are the same as those shown in FIG. Nine diagnostic functions and diagnostic circuits can be applied to these fail-safe circuits.

FIG. 17 shows an embodiment of the safety protection device according to the sixth embodiment of the present invention. This safety protection device has a sensor S
Comparing means D for determining whether the output signals of 1 to SN exceed the reference value
1 to DN, and if it exceeds the reference value, load 1
The trip signals for driving 0 'are compared with the comparing means D1 to DN.
Is output from each. The calculating means 52 is provided with each comparing means D
It takes in the output signals of 1 to DN, executes an operation such as a logical sum, and outputs a signal of logic "0" for driving the load 10 '. This signal is input to the reference frequency signal output means 65 via the NOT circuit 66. Reference frequency signal output means 65
Is composed of a reference frequency generation means 53 and an AND gate 54. When the output signal of the calculation means 52 is logic "1", a signal of logic "0" is output from the reference frequency signal output means 65, When the output signal of the means 52 is logic “0”, the reference frequency signal from the reference frequency generation means 53 is output. This reference frequency signal is output to the fail-safe circuit 12 via a transmission system including 55, 57, and 56. The switch 9 is controlled by the output signal of the fail-safe circuit 12, and the load 1
0 'works.

In general, the load 10 ′ is installed at a site such as a plant, and the arithmetic unit 52 is often installed at a plant control room or the like. Therefore, both are connected by an optical transmission system to improve noise resistance. Can be considered. Therefore, it is effective to set 55 as an optical transmitter, 57 as an optical cable, and 56 as an optical receiver. Although the fail-safe circuit 12 shown in FIG. 17 uses the fail-safe circuit shown in FIG. 9, the fail-safe circuit shown in FIG. 1, FIG. 3 or FIG.

It is effective that the arithmetic means 52 is a means having a computer processing function such as a microcomputer from the viewpoint of processing performance. In the case where the fail-safe circuit of FIG. 6 is used, the reference frequency generating means 53 outputs signals from the reference signal generating means 531 and 532 having different output frequencies, for example, like a signal synthesizing means 53 'shown in FIG. Need to be output as a means for outputting a reference frequency signal created by combining with the AND gate 533.

The diagnostic result obtained by the diagnostic circuit of the fail-safe circuit 12 is input to the OR gate 48,
The information is displayed on a display means 51 installed in a central control room or the like via a transmission system including 8, 50. Here, it is effective in terms of noise resistance that the transmission system is an optical transmission system including the optical transmitter 49, the optical cable 58, and the optical receiver 50. When the safety protection device is configured as described above, the output of the arithmetic means 52 becomes high impedance due to the loss of the drive power supply of the arithmetic means 52, so that a logical "1" signal is output from the arithmetic means 52. Or a failure in which a signal of logic "1" is equivalently output from the arithmetic means 52 or a reference frequency signal from the reference frequency signal output means 65 Even if any failures such as a failure to be lost or a failure in the transmission system or the fail-safe circuit occur, the function of the fail-safe circuit path 12 causes the load 10 ′ to fail.
Can be operated on the fail-safe side. In addition, since the fail-safe circuit 12 can obtain a high-speed response by previously defining the frequency of the reference frequency signal to a relatively high frequency as described above, a fail-safe circuit is used. High-speed response of the safety protection device can be realized.

If the arithmetic means 52 fails to logic "0", fail-safeness cannot be ensured, so a safety protection device is configured as shown in FIG. In the safety protection device according to the seventh embodiment shown in FIG.
A logic circuit provided between the arithmetic means 52 and the reference frequency signal output means 65 copes with the above failure. The operation means 52 outputs two output signals 59 and 60. When the load 10 'is operated, the two signals have different logics. If one is logic "1", the other is logic "1". 0 ". These two signals are input to an exclusive OR circuit (EOR circuit) 63 via NOT circuits 68 and 69 and AND 61 and 62. Test circuit 64
Is normally logic "1", the EOR circuit
Both signals of logic "1" and "0" are input to 63, and the output is always "1". As a result, a reference frequency signal for operating the load 10 'is output from the reference frequency signal output means 65. Moreover, the calculating means 52 outputs the output signal
By alternately outputting the logical values of 59 and 60, the reference frequency signal output means 65 can always output the reference frequency signal even if the output of the operation means 52 is stuck at logic "0". Absent.

That is, also in this case, the fail-safe property is ensured. When not operating the load 10 '
The operation means 52 outputs the same logic "1" as the output signals 59 and 60.
Alternatively, “0” is output. As a result, since both inputs of the EOR circuit 63 are signals of the same logic, the output thereof is logic "0".
And the output of the reference frequency signal output means 65 is also logic "0".
Becomes

In the case of the above configuration, the EOR circuit
It is conceivable that 63 itself fails to output a signal of logic "1". In response to this, a test signal of logic "0" shorter than the pulse width of the reference frequency signal is output to the AND61.
And 62 to detect a logic "1" failure of the EOR circuit 63. When the test signal is applied, the outputs of the AND gates 61 and 62 become logic "0", and the output of the EOR circuit 63 also becomes logic "0". Failure can be detected.

The operation means 52 receives the output signals of the NOT circuits 68 and 69 and the output signal of the EOR circuit 63,
Each time the calculating means 52 alternately outputs two signals having different logical values, these signals are fetched and the NOT circuits 68, 6
9. A diagnosis is made as to whether a failure has occurred in the AND circuits 61, 62 and the EOR circuit 63, and if there is a failure, the fact is displayed on the display means 70. In addition, the display means 67 uses the EOR
This is a means for displaying the test result of the circuit 63.

Here, the control means 71 determines whether the arithmetic means 52, NO
T circuits 68 and 69, AND gates 61 and 62, EOR circuit 63 and test circuit 64 are integrated and integrated, but this eliminates unnecessary wiring and power supply, further improving reliability. Can be done. This control means 71
The reliability will be further improved.

In the examples shown in FIGS. 17 and 18, the circuits from the calculating means 52, which is described as a safety protection device, to the fail-safe circuit 12 and the switch 9 at the subsequent stage are general-purpose, and a fail-safe function is required in each field. It can be applied to the use.

As described above, the configuration shown in FIGS. 17 and 18 is suitable for a safety protection device, which is one application requiring safety and high-speed response, and can diagnose each circuit. When the safe function operates, it is possible to identify an early abnormal part, repair it, and start up the system again early, and provide a safety protection device with a high operation rate.

[0065]

According to the safety protection device of the present invention, it is detected whether or not the frequency of the input signal is within the reference range, and when the frequency deviates from the reference range, the fail-safe circuit is operated. In addition, by setting the reference frequency at a relatively high frequency, it is possible to detect the deviation from the reference range at an early stage. The responsiveness of the system can be improved. Also,
By adding a diagnostic circuit that detects on-line which part of the safety device has an abnormality, it is possible to identify the abnormal part during the fail-safe operation and the abnormal part before the operation, and complete the repair early. Becomes possible.

Further, since it is possible to diagnose online the operation means for outputting a command for operating the safety protection device and the circuit for driving the load, the fail-safety and reliability of the safety protection device can be further improved. Since it can be further improved and the response of the fail-safe function is fast, a safety protection device excellent in reliability, safety and high-speed response can be provided, and its industrial value is extremely high.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a security device according to a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram of each part of the first embodiment.

FIG. 3 is a configuration diagram of a security device according to a second embodiment of the present invention.

FIG. 4 is an operation waveform diagram of each part of the second embodiment.

FIG. 5 is a configuration diagram of an example of a signal combining unit.

FIG. 6 is a configuration diagram of a security device according to a third embodiment of the present invention.

FIG. 7 is an operation waveform diagram of each part of the third embodiment.

FIG. 8 is a configuration diagram of a safety protection device with a diagnostic circuit according to a fourth embodiment of the present invention.

FIG. 9 is a configuration diagram of a safety protection device with a diagnostic circuit according to a fifth embodiment of the present invention.

FIG. 10 is an operation waveform diagram of each unit when the frequency tuning circuit is normal in the fifth embodiment.

FIG. 11 is an operation waveform diagram of each unit when the output of the frequency tuning circuit has a stuck-at fault of logic “1” in the fifth embodiment.

FIG. 12 is an operation waveform diagram of each unit when the output of the frequency tuning circuit has a stuck-at fault of logic “0” in the fifth embodiment.

FIG. 13 is an operation waveform diagram of each unit when a circuit upstream of the rectifier circuit is normal in the fifth embodiment.

FIG. 14 is an operation waveform diagram of each unit when a circuit upstream of the rectifier circuit is abnormal in the fifth embodiment.

FIG. 15 is an operation waveform diagram of each section when a circuit upstream of a switch is normal in the fifth embodiment.

FIG. 16 is an operation waveform diagram of each unit when a switch fails in the fifth embodiment.

FIG. 17 is a configuration diagram of a security device according to a sixth embodiment of the present invention.

FIG. 18 is a configuration diagram of a security device according to a seventh embodiment of the present invention.

[Explanation of symbols]

2 frequency tuning circuit, 14 frequency monitoring means, 5 transformer, 11 rectifier circuit, 9 switch, 10 load, 12 fail-safe circuit (safety protection device), 15 reference signal output means, 16 voltage Detecting means, 31 ... test signal output means, 35 ...
Current change detection means, 52 arithmetic means, 63 exclusive OR circuit, 65 reference wave number signal output means, 53 reference frequency generation means, 53 'signal synthesis means, 531 and 532 reference signal generation means.

Claims (7)

(57) [Claims] 1. A security device for generating a DC driving voltage of the switch for controlling the load of the plant safety protection system, and the frequency monitoring means for monitoring whether the frequency of the input signal is within the reference range, the Gate means for outputting the input signal only when the frequency monitoring means detects a frequency within the reference range; and means for generating the DC drive voltage from the output signal of the gate means and outputting the DC drive voltage to the switch. security device characteristics and to pulp plant safety protection system that. 2. A method switches the DC driving voltage for controlling the load of the plant safety protection system, the security device for generating and rectifies the input signal composed of a rectangular wave signal or the AC signal by the rectifier means, the frequency of the input signal Frequency monitoring means for monitoring whether or not the input signal is within a reference range, and outputting the input signal to the rectifying means when the frequency monitoring means detects that the frequency of the input signal deviates from the reference range. security device characteristics and to pulp La <br/> cement safety protection system that comprises a gate means for blocking. 3. A security device for outputting a DC driving voltage of the switch to a rectangular wave signal or AC signal as an input signal by rectifying the input signal for controlling the load of the plant safety protection system, the frequency of the input signal Frequency monitoring means for monitoring the DC drive voltage generated from the input signal when the frequency monitored by the frequency monitoring means is within a reference range, and outputting the DC drive voltage when the frequency deviates from the reference range. security device characteristics and to pulp plant safety protection system that comprises a means for controlling the safe side the load by blocking the commutation signal. 4. A frequency monitoring means for receiving a rectangular wave signal or an AC signal as an input signal and monitoring the frequency of the input signal;
Gate means for outputting the input signal when the frequency monitoring means detects a frequency within the reference range and cutting off the output when the frequency deviates from the reference range; a transformer passes only AC components, features and to pulp plant safety protection system further comprising a rectifying means for outputting a DC driving voltage of the switch for controlling the load of the plant safety protection system rectifies the output signal of the transformer Safety protection device. 5. A frequency monitoring means for receiving a rectangular wave signal or an AC signal as an input signal and monitoring the frequency of the input signal.
Gate means for outputting the input signal when the frequency monitoring means detects a frequency within the reference range and cutting off the output when the frequency deviates from the reference range; characterized in that it comprises a transformer and outputting the cut a DC component, and a rectifying means for outputting a DC driving voltage of the switch for controlling the load of the rectification plan <br/> preparative safety protection system the output signal of the transformer and to pulp <br/> Holland safety protection system security device. 6. A rectangular wave signal or an AC signal is input to an input signal.
Frequency monitoring means for monitoring the frequency of the input signal,
The frequency monitoring means detects a frequency within the reference range
When the input signal is output and the frequency is in the reference range
Gate means for shutting off the output when deviating from
Of the output signal from the
Lance and rectify the output signal of the transformer to ensure plant safety
As the DC drive voltage of the switch that controls the load of the protection system
Rectifying means for outputting, and an output signal of the frequency monitoring means
When the input signal indicates a deviation from the reference range.
A first diagnostic means for outputting a fault occurrence;
Monitor the applied DC voltage, and when the DC voltage reaches a predetermined voltage,
Second diagnostic means for outputting a fault occurrence when not
Safety protection system for plant safety protection system
Place. 7. The security device comprising a fail safe circuit for controlling the load of the plant safety protection system, the outgoing when trip signal transmits a square wave signal or the AC signal is generated when driving the load Frequency generating means for cutting off, an optical transmission system for converting a signal transmitted from the frequency generating means to an optical signal, propagating the optical cable, and converting the optical signal to an electric signal on the receiving side, and receiving the signal through the optical transmission system. security device and security device characteristics and to pulp plant safety protection system that comprises of any one of claims 1 to 6 as an input signal a signal converted into an electrical signal.