JP2594987B2 - Interline flicker removal circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to signal processing of an interlaced scanning television signal, and more particularly to an interline flicker removing circuit for removing interline flicker interference and a vertical edge enhancer.

[Summary of the Invention] The present invention provides an interline flicker elimination circuit that processes an interlaced scanning television signal by extracting a vertical high-frequency component and increasing the high-frequency component.
In addition, when the image is a still image, the high frequency component is subtracted from the original signal, thereby removing interline flicker interference generated in an interlaced scanning television signal.

It should be noted that this summary is provided only for quick access to the technical contents of the present invention, and has no influence on the technical scope and interpretation of rights of the present invention.

[Prior Art] Conventionally, there is no effective means other than reducing the vertical resolution of a camera to remove interline flicker, which is one of the causes of image quality degradation caused by an interlaced scanning television signal.

[Problems to be Solved by the Invention] When a television signal of interlaced scanning is displayed on a display of a receiver, an interlaced portion of a high frequency component of a vertical spatial frequency such as a vertical edge of an original image is included. A phenomenon of causing line flicker interference and deteriorating image quality occurs. Therefore, if the vertical resolution of the imaging camera is reduced (made sweet) as in the prior art, the interline flicker disappears, but there is a disadvantage that the entire image is blurred more than necessary.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an interline flicker elimination circuit capable of eliminating the above-mentioned disadvantages and eliminating interline flicker without lowering the vertical resolution of the camera.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a high frequency component extraction circuit for extracting a high frequency component of a vertical spatial frequency from an interlaced scanning television signal as an original signal, and a high frequency component extracting circuit. A first detection circuit for detecting the amount of the high frequency component extracted by the component extraction circuit, a second detection circuit for detecting the movement of the original signal,
A signal indicating the movement detected by the second detection circuit and the first signal;
A control signal generation circuit for generating a control signal based on a signal indicating the amount of the high frequency component detected by the detection circuit, and subtracting the high frequency component from the original signal according to the control signal output from the control signal generation circuit And a control circuit for controlling the amount.

[Operation] According to the present invention, the vertical high frequency component is subtracted from the original signal in accordance with the amount of the vertical high frequency component of the still image. Can be removed.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit configuration of an interline flicker removal circuit according to one embodiment of the present invention. Input signals of the code I _S is a television signal of interlace scanning, it is guided to the vertical an HPF (high-pass filter) 1 for extracting a high frequency component of the vertical spatial frequency from the signal.

Reference numerals 2 to 7 in the drawing show specific examples of the configuration of the vertical HPF 1. That is, the input signal _IS is input to the f-1 / 2H (one field minus 1/2 line) delay circuit 2, and the output of the f-1 / 2H delay circuit 2 and the output thereof are further changed to 1H. (1 line) The signal delayed by one horizontal period by the delay circuit 3 is added by the adder 4, and the addition result is multiplied by a coefficient unit 5 by a coefficient of -1/4. Further, when the value obtained by multiplying the input signal I _S by a coefficient of 1/2 by the coefficient unit 6 and the output of the above-described coefficient unit 5 are added by the adder 7, the output y of the adder 7 becomes the input signal I _S Is the high frequency component of the vertical spatial frequency.

The output of the vertical HPF 1, that is, the output y of the adder 7 is guided to an absolute value circuit 8 and a MIX (mixing) circuit 9. Absolute value circuit 8
Outputs the absolute value y of the signal y as a signal indicating the amount of the high frequency component.

Reference numerals 10 and 11 in the figure are input signals according to the control signal z.
MIX circuit 9 for controlling the amount subtracting the high frequency component y from I _S
Is shown. Here, 10 is a variable attenuator,
The output signal y of the vertical HPF1 is attenuated according to a control signal z described later. The output of the variable attenuator 10 is subtracted from the input signal I _S by the subtracter 11, the output signal O _S of the interline flicker reduction circuit.

On the other hand, the output of the f-1 / 2 H delay circuit 2 is also guided to the f + 1/2 H (one field plus 1/2 line) delay circuit 12, and the subtractor 13 outputs the output of the delay circuit 12 and the input signal I _S Is required. The output signal x of the subtracter 13 is inter-frame difference signal of the input signal I _S. Then, it obtained as a signal indicating the amount of motion component of the absolute value x 'is the input signal I _S of the output signal x by an absolute value circuit 14. This signal x 'is input to the control signal generator 15 together with the output y' of the absolute value circuit 8 described above.

Reference numerals 16 to 18 in the figure show configuration examples of the control signal generator. The levels of the signal x 'and the signal y' are converted by the corresponding nonlinear level converters 17 and 16, respectively. The outputs of the non-linear level converters 16 and 17 are multiplied by a multiplier 18 and the result of the multiplication is output to the MIX circuit 9 as a control signal z.

The characteristics of the nonlinear level converters 16 and 17 are set, for example, as shown in FIGS. 2 (A) and 2 (B). That is, for the signal y 'indicating the amount of the high frequency component of the image, as shown in FIG. 2A, the higher the input level of the signal y', the higher the output level of the nonlinear level converter 16 becomes. Set to be.

In FIG. 2 (A), the reason why the dead zone is provided for the input level is to suppress noise. Also,
As shown in FIG. 2B, for the signal x 'indicating the amount of the motion component of the image, as the input level of the signal x' is lower, the output level of the nonlinear level converter 17 is higher, and The output level of the nonlinear level converter 17 is set to be zero when the input level of 'is larger than a predetermined value.

Using the characteristics of the non-linear level converters 16 and 17, the output level of the control signal z in FIG. 1 increases as the motion component x in the image decreases and the high frequency component y increases. The characteristics of the variable attenuator 10 in this case, the control signal z to the output at z = 0 = 0, also is set so that no attenuation at z = maximum high-frequency component y in the input signal I _S is many, and when less motion component x, the high frequency component y from the input signal I _S
Is to be subtracted.

Next, FIG. 3 shows the operation of the circuit of FIG. 1 in the time-vertical spatiotemporal frequency domain. In FIG. 3, the horizontal axis is the time frequency f _(HZ) , and the vertical axis is the vertical spatial frequency ν.
It is. The input signal I _S 2 of 1125 scanning lines, field frequency 60H _Z: a 1 interlace signal. First,
The vertical high frequency component of the still image is represented by a hatched area a in FIG. This area a is folded by an interlaced carrier to form an area a 'indicated by the same hatching. A and a 'are components that cause interline flicker. On the other hand, since the pass band of the vertical HPF1 in FIG. 1 is represented by the dashed curves c and c ', the a and a' components are extracted from the output of the vertical HPF1.

Therefore, if the interline flicker is conspicuous, that a, a 'when components is large, if subtracting the output y of the vertical HPF1 from the input signal I _S a, a' are removed, interline flicker is removed.

However, when the image moves, a and a 'have a shape that spreads in the time direction as indicated by solid curves b and b'. In contrast, the vertical HPF1
Has an attenuation characteristic in the time direction like c and c '. Therefore, if the above-described operation (subtraction) is performed, another image quality deterioration such as a double image occurs in the image. Furthermore, in the case of moving images, in general, due to accumulated blur or afterimages of the camera,
Since the vertical high frequency component is also reduced, interline flicker is not so noticeable. Therefore, in the present embodiment, when the image has many motion components, the above-described calculation is not performed. In FIG. 1, the inter-frame difference signal is used to detect the amount of motion of the image.
In the drawing, the signal is a signal indicating a component of a region d surrounded by a broken line.

FIG. 4 shows an example of the characteristics of the circuit of FIG. 1 with respect to the vertical spatial frequency ν described above. As shown in FIG. 4, when the input signal I _S has a flat component up to the high frequency range of the vertical spatial frequency ν, the hatched component in this figure generally causes interline flicker. Therefore, the vertical HP in this figure
Subtracting the output characteristics of F1 from the characteristics of the input signal I _S, characteristic of the output signal O _S which does not cause interline flicker as indicated by the broken line in the figure is obtained.

FIGS. 5A and 5B show another embodiment of the present invention.
That is, in the present embodiment, the MIX circuit 9 of FIG. 1 is replaced by a circuit having the configuration of FIG. 5 (A), and the output characteristic of the nonlinear level converter 16 of FIG. Instead, the characteristic shown in FIG. 5 (B) is used.

First, in FIG. 5 (A), the output signal y of the vertical HPF1
Is multiplied by a coefficient of −1 by a coefficient unit 20 to obtain a value of −y. The signal -y and the signal y are input to the variable attenuator 21 with a midpoint.
The middle point of the variable attenuator 21 with the middle point is grounded, and the output point of the variable attenuator 21 is the y signal side when the control signal z is negative, the −y signal side when the control signal z is positive, and When the control signal z is zero, it slides to the middle point. The output of the middle point with the variable attenuator 21 adds the input signal I _S in an adder 22.

The characteristic curve of FIG. 5B shows that the output level of the converter 16 is zero when the y 'signal input to the non-linear level converter 16 is a reference value, and that the output level of the converter 16 when the y' signal is higher than the reference value.
If the output level of the converter 16 is positive and the y 'signal is lower than the reference value, the output level of the converter 16 is negative. If the characteristics of the nonlinear level converter 17 in FIG. 1 are kept as shown in FIG.
Since the output of the non-linear level converter 17 can have only a positive value, the control signal z supplied to the variable attenuator 21 with a middle point has a small motion component in the input signal I _S and y ′, that is, the vertical height of the input signal. When the frequency component exceeds the reference value, it becomes positive, and when it is less than the reference value, it becomes negative. As a result,
When vertical high-frequency component of the input signal I _S is large, this embodiment circuit serves as interline flicker reduction circuit similar to the circuit of FIG. 1, when the high frequency component is small operates as enhancer of vertical high I do.

FIG. 6 shows a boost frequency characteristic when operating as the above-mentioned enhancer in the embodiment of the present invention using the circuit of FIG. 5 (A). Normal vertical enhancer is 3rd
In order to avoid image quality degradation in moving images as described with reference to the figure and to simplify the apparatus, the vertical mid-range is boosted by in-field processing as shown by the broken line curve in FIG. According to the embodiment of the present invention, it is possible to enhance the original vertical high frequency as shown by the solid line in FIG.

It should be noted that the present invention is not limited to the above-described embodiment,
Of course, it can be used for all interlace signals such as NTSC and PAL.

[Effects of the Invention] As described above, according to the present invention, the vertical high frequency component is subtracted from the original signal in accordance with the amount of the vertical high frequency component of the still image. The effect of eliminating interline flicker occurring in scanning television can be obtained.

Further, according to the present invention, even when the vertical resolution of the original signal is unnecessarily low, it is possible to enhance the vertical high frequency, which is difficult with the conventional enhancer.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention, and FIGS. 2A and 2B show an example of characteristics of nonlinear level converters 16 and 17 used in the circuit of FIG. FIG. 3 is an explanatory diagram showing an example of processing in the spatiotemporal frequency domain in the embodiment of the present invention shown in FIG. 1, and FIG. 4 is an example of a vertical frequency characteristic of the embodiment of the present invention shown in FIG. FIG. 5A is a block diagram showing a main part circuit configuration of another embodiment of the present invention, and FIG. 5B is a characteristic diagram showing another characteristic example of the nonlinear level converter 16. FIG. 6 is a characteristic diagram showing an example of the vertical frequency characteristic in the embodiment of the present invention shown in FIGS. 5 (A) and (B). 1 ... vertical HPF, 2 ... f-1 / 2H delay circuit, 3 ... 1H delay circuit, 4 ... adder, 5 ... coefficient unit, 6 ... coefficient unit, 7 ... adder, 8 , 14 ... absolute value circuit, 9 ... MIX circuit, 10 ... variable attenuator, 11 ... subtractor, 12 ... f + 1/2 H delay circuit, 13 ... subtractor, 15 ... control signal generator , 16, 17… Non-linear level converter, 18… Multiplier, 20… Coefficient unit, 21… Variable attenuator with middle point, 22… Adder.

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-62-171282 (JP, A) JP-A-62-76887 (JP, A) JP-A-63-316977 (JP, A)

Claims (2)

(57) [Claims] A high-frequency component extraction circuit for extracting a high-frequency component of a vertical spatial frequency from an interlaced scanning television signal as an original signal; and an amount of the high-frequency component extracted by the high-frequency component extraction circuit. A first detection circuit for detecting, a second detection circuit for detecting the movement of the original signal, a signal indicating the movement detected by the second detection circuit, and the signal detected by the first detection circuit. A control signal generation circuit for generating a control signal based on a signal indicating the amount of the high frequency component, and controlling an amount of subtracting the high frequency component from the original signal in accordance with the control signal output from the control signal generation circuit And an interline flicker removal circuit. 2. The circuit according to claim 1, wherein the control circuit is capable of performing not only subtraction of the high frequency component from the original signal but also addition according to a value of the control signal. An interline flicker elimination circuit characterized in that: