JP2592066B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing apparatus for converting a digital image signal expressed in multiple gradations into a digital pixel signal having several gradations.

(Prior Art) In a copying machine, a facsimile, a printer, and the like using digital image data, a dither method is often used as a method of performing gradation processing of an image signal expressed in multiple gradations to several gradations. Since a dither matrix pattern is used in the method, moire occurs when a halftone dot image is input, and the resolution decreases as the matrix size increases. Further, there is a drawback such that a buffer memory of several lines is required for realizing with hardware.

In addition, there is a conventional method in which a conversion error generated by the dither method is fed back to an image signal before dither processing of the next block. There is also an image binarization processing method for performing error correction using a weight matrix.

However, as described above, when the dither method is used, the resolution is deteriorated due to the size of the dither matrix, and the reproducibility of gradation is deteriorated in the binarization processing.

(Purpose) An object of the present invention is to solve the above-mentioned drawbacks of the prior art, and it is possible to suppress the occurrence of moire from an original image including a halftone original and perform gradation processing without lowering the resolution. An image processing device is provided.

(Structure) In order to achieve the above object, the present invention provides an image processing apparatus for obtaining a reproduced image from an image signal represented by multiple gradations.
Means for separating and adding the image signal into even-numbered pixels and odd-numbered pixels; and means for holding the result of gradation processing of the added signal and the conversion error caused by the gradation processing for one block. By feeding back the conversion error to the pixel signal of the next block, the conversion error is corrected without the occurrence of moire or reduction in resolution without using a matrix in the dither method or the like. I do.

Hereinafter, embodiments of the image processing apparatus according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is an image distribution unit, 2, 3, and 5 are adders, 4 and 6 are gradation processing units, and 7 is an image combining unit.

In FIG. 1, an input multi-tone image signal is supplied to a pixel distribution unit 1.
Is distributed to even-numbered pixel signals and odd-numbered pixel signals. The even-numbered pixel signal is added to the odd-numbered pixel signal by an adder 3 via an adder 2 described later. The gradation processing units 4 and 6 convert the respective input gradation image signals into n gradations suitable for the image reproducing device to reproduce an image.
Note that n is an integer equal to or larger than 2 and equal to or smaller than the number of input gradations.

At this time, the n-gradation image signal causes a conversion error with respect to the input gradation image signal, and this error is again added to the gradation image signal by the adders 5 and 2 and used for gradation processing. The n-gradation image signal subjected to the gradation processing in this manner is output at the pixel combining section by combining the even-numbered pixel signal and the odd-numbered pixel signal.

The feature of the present embodiment is that the grayscale image signal is divided into even-numbered pixels and odd-numbered pixels by the pixel distribution unit 1, and error correction is sequentially performed on each of the two pixels using adders 2 and 5. The point is that the gradation processing is performed.

FIG. 2 is a circuit diagram of another embodiment of the present invention.
8, 17, 18, 19 are latches, 9, 10, 14 are adders, 11 is subtractors, 1
2 is an overflow corrector, 13 is an underflow corrector, 15 and 16 are dividers, 20 is a data selector, and 21 is a frequency dividing counter.

In the figure, a multi-tone image signal which is an input signal is input to a latch 8. The latch 8 has an asynchronous clear function like the other latches 17, 18, and 19 and is cleared by a horizontal synchronizing signal. In other words, all the latches in FIG. 2 are initialized by the horizontal synchronizing signal, and then the first gradation image of one line is latched. Latch timing is Latch
Each of 8, 17, 18, and 19 is determined by the pixel clock obtained by dividing the pixel clock by 1/2 by the frequency dividing counter 21, which is one pixel interval.

The output of the latch 8 enters the adder 9 where it is added to the output of the latch 19. The output of the latch 19 is a quantization error of the gradation processing corresponding to the output of the gradation processing unit 6 in FIG. The adder 10 adds the output of the adder 9 and the output of the latch 8, which corresponds to the adder 3 in FIG. 1 and has the meaning of adding even-numbered pixel signals and odd-numbered pixel signals. The output of the adder 10 is divided into two and enters an overflow corrector 12 and a subtractor 11, which are processed as even-numbered pixel signals and odd-numbered pixel signals by the subsequent circuits. The even-numbered pixel signals input to the overflow corrector 12 are output as the maximum value -1 and corrected only for pixel signals that are equal to or more than the maximum value that the input gradation pixel signal can take.

The subtractor 11 subtracts the maximum value of the input gradation pixel signal from the output signal of the adder 10, and the underflow corrector 13 corrects the negative signal in the output of the subtractor 11 to θ. As a result, the output of the underflow corrector 13 outputs a signal corresponding to the value corrected by the overflow corrector 12 described above.

The divider 15 divides the output signal of the overflow corrector 12 by a predetermined quantization gradation Step. This corresponds to the gradation processing unit 4 in FIG. 1. The quotient becomes the n-th gradation pixel signal of the even-numbered pixel, and is input to the latch 17 and the remainder is input to the adder 14 for quantization error correction. The quantization gradation Step is set to a value obtained by dividing the number of input gradations by the number n of output gradations.

The divider 15 defines a case where the gradation is a linear step. If the gradation is non-linear, that is, the divider 15 may perform processing such as, for example, a log curve according to the characteristics of a printer or the like.

The signal obtained by adding the quantization error and the output of the underflow corrector 13 in the adder 14 becomes an odd-numbered pixel signal and a divider 16 (corresponding to the gradation processing unit 6 in FIG. 1) like the even-numbered signal. , And becomes an n-gradation pixel signal, which is input to the latch 18. The quantization error (the remainder of the divider 16) generated here is latched by the latch 19, and then input to the adder 9 described above, and then input.

The quantization error is added to the gradation signal of the even-numbered pixel to correct the quantization error at the time of quantization of n gradations.

The image signals latched on the latches 17 and 18 after the n gradation processing are alternately output by the data selector 20 as even-numbered and odd-numbered pixel signals, respectively. The output of the frequency dividing counter 21 is used as a select timing signal of the data selector 20. This corresponds to the pixel coupling section 7 in FIG. 1 and returns the pixels separated by the pixel distribution section 1 to the original shape again. In this manner, the pixel signal quantized to n gradations is output to the data selector 20.

FIG. 3 is an operation waveform diagram for explaining the operation of FIG.
FIG. 4 is an explanatory diagram showing the value of each signal in FIG.

In FIG. 2, the highest gradation value, that is, the highest density value is 10
0, the number of quantized gradation steps is 20, the number of output gradations is n = 5, the data held in the latch 19 is 10, the even-numbered pixel signal is 55, and the odd-numbered image signal is 62. ,
With respect to the pixel lock, each device in FIG. 2 is as shown in FIG.

FIG. 4 shows that, for the input multi-gradation signals 55 and 62, the output 5-gradation signals 4, 2 were obtained.

When pixels are continuous in the main scanning direction, the multi-tone image signal which is an input in the present embodiment performs the main scanning method, and adds even-numbered pixels and odd-numbered pixels which have been used in the main scanning method.

FIG. 5 is a block diagram showing another embodiment of the image processing apparatus according to the present invention corresponding to the sub-scanning direction, wherein 22 is a buffer memory for one line in the main scanning direction, 23 is a data selector, and 24 is FIG. 25 is a conversion error buffer memory having the same configuration and operation as the above.

In the configuration shown in FIG. 3, a buffer memory 22 for a multi-tone image signal for one line in the main scanning direction is provided in order to add pixels adjacent to each other in the sub-scanning direction with respect to an input continuous in the main scanning direction. This is supported by adding a buffer memory 25 for holding a conversion error.

(Effects) As described above, according to the present invention, since a matrix in the dither method or the like is not used, the resolution of a reproduced image is good and moire does not occur. Further, since the conversion error is subjected to the feedback correction, the reproducibility of the gradation in the entire image is good.

Then, by adding even pixels and odd pixels,
The uniformity in the solid image portion and the effect of edge enhancement in the halftone portion can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of another embodiment of the present invention, FIG. 3 is an operation waveform diagram of FIG. 2, and FIG. Explanatory diagram showing the value of each signal of
FIG. 5 is a block diagram showing another embodiment of the present invention corresponding to the sub-scanning direction. 1 ... Pixel distribution unit, 2,3,5 ... Adder, 4,6 ... Grayscale processing unit, 7 ... Pixel combining unit.

Claims (2)

(57) [Claims] 1. An image processing apparatus for obtaining a reproduced image by processing two successive pixels of an image signal from a multi-gradation-expressed image signal as one block, wherein the image signal is divided into even-numbered pixels and odd-numbered pixels. A separating unit that separates the pixels into pixels, an adding unit that adds the even-numbered pixels and the odd-numbered pixels that have been separated, and a conversion result generated by performing the gradation processing on the added signal and the conversion error caused by the gradation processing. An image processing apparatus comprising: holding means for holding one block; and means for feeding back the conversion error to a pixel signal of the next block. 2. The apparatus according to claim 1, wherein said feedback means is an addition of a conversion error held by said holding means and an image signal before gradation processing of a next block. Image processing device.