JP2590931B2 - Signal correction circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal correction circuit for a video signal of an image display device driven by a picture element such as a liquid crystal television and a flat panel display.

2. Description of the Related Art Conventionally, a cathode ray tube is mainly used as a display element for displaying a color television image. However, a conventional cathode ray tube has a very long depth compared to a screen size, and is a thin television receiver. It was impossible to create. Therefore, in recent years, as a flat display element, an EL display element, a plasma display apparatus, a liquid crystal display element, and a new image display apparatus disclosed by the present applicant in JP-A-57-135590 have been disclosed and put into practical use. It is getting.

Unlike the CRT, the image display device driven by these picture elements has a linear luminance characteristic with respect to a drive voltage, and has a problem that a bright image (strong signal) is destroyed when a video signal is used as a drive voltage as it is.

Hereinafter, the difference in luminance characteristics as described above will be described with reference to the drawings.

FIG. 10 is a graph showing a comparison between a luminance characteristic and a gradation (appearance brightness) of an image display device driven by a cathode ray tube and a picture element unit. In FIG. B, luminance characteristics with respect to the driving voltage of the image display device driven in units of picture elements, c, gradations with respect to luminance, d, gradations with respect to driving voltage of the cathode ray tube, e, driving of the image display device driven in units of picture elements The gray scale with respect to the voltage, f indicates the drive voltage with respect to the video signal.

As a feature of the human eye, a dark object can be clearly identified even with a small difference in brightness, but a bright object cannot be identified. This is shown in the graph in Fig. 10c.
As a result, the drive voltage and the gradation become almost linear as shown in d as well as the luminance characteristic a of the CRT. On the other hand, in the case of an image display device driven in pixel units,
Since it has a linear luminance characteristic like b, the gradation with respect to the drive voltage becomes a logarithmic curve like e. Therefore,
If the drive voltage is corrected in advance so that the input video signal has an exponential characteristic like f, the gradation becomes linear as d.

FIG. 9 is an example of a conventional signal correction circuit for performing the above correction. In FIG. 9, R11 to R18 are resistors, C1
1 is a capacitor, TR1 to TR3 are transistors, D1 to D3 are diodes, and 31, 32, and 33 are waveforms of an input video signal, a collector output of the transistor TR1, and a final output video signal, respectively.

Now, input video signal (RGB signal) 3
When 1 is input, a large amount of current flows through the transistor TR1 due to the action of the diodes D1 to D3 in the high voltage portion.As a result, the collector output of the transistor TR1 has a corrected waveform like 32, and is inverted by the transistor TR3. As a result, a corrected video signal like 33 is obtained at the output terminal OUT.

By subjecting the corrected video signal to analog-digital conversion (A / D conversion), a drive signal for a display device driven in picture element units is obtained.

However, the above-described conventional signal correction circuit can perform only a simple exponential curve correction, and as a circuit capable of performing correction showing more complicated characteristics, the present applicant has disclosed in Japanese Patent Application No.
No. 31631 proposed a signal correction circuit including a memory for replacing a video signal digitized into several bits with desired unique correction data and a flip-flop for adjusting the timing of the correction data output from the memory.

This means that the digital video signal applied to the A / D converter is used as a memory address, the data uniquely corresponding to the address is output as a corrected digital video signal, and then the output data is input to a flip-flop. By adjusting the timings, desired correction is applied to the video signal.

Problems to be Solved by the Invention However, in the above configuration, the correction data is fixed regardless of whether the average luminance level (APL) is high or low, so that the gradation is generally changed to a bright scene (a scene with a high APL). If you try to give it a glow, the screen will darken and darken if the scene is entirely dark. Conversely, if an attempt is made to clearly display a dark scene as a whole, a bright scene as a whole will appear bright and bright. This is particularly noticeable when an image display element having low gradation is used.

The present invention has been made in view of the above problems, and provides a signal correction circuit capable of switching correction data depending on the magnitude of an APL signal.

Means for Solving the ProblemsTo solve the above problems, the signal correction circuit of the present invention comprises a memory having data for logarithmically converting a video signal digitized into several bits, and the logarithmically converted signal. A digital multiplier for multiplying the digitized APL signal, and a memory having data for exponentially converting the signal output from the digital multiplier, and a flip-flop for adjusting the timing of each signal is provided between the respective circuits. It is provided.

Operation According to the present invention, the manner in which data is corrected can be changed depending on the value of APL. The reason will be briefly described below.

The three solid lines in FIG. 7 indicate the coordinates of the intersection of the three lines (1,
If 1), it is represented by the following equation as a general equation.

y = ^xγ (x> 0, y> 0, γ> 0) (1) The above three solid lines are 6 is a graph of y = x ^γ at the time of FIG.

 This equation (1) can be converted as follows.

log y = log x ^γ log y = γ · log x ∴ y = e ^{γ · log x} (2) The equation (2) shows that the logarithm of x is multiplied by γ and exponentially converted to y. Therefore, when this is represented in a block diagram, it is as shown in FIG.

Conversely, if the block diagram of FIG. 8 is actually implemented, the way of correction can be changed as shown in FIG. 7 by the value of γ, that is, APL. In the present invention,
A memory containing logarithmic and exponential conversion data is used as a logarithmic converter and an exponential converter, respectively.

Embodiment Hereinafter, a signal correction circuit according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a signal correction circuit according to a first embodiment of the present invention. In the figure, 1 is a video signal input terminal, 2 is a clock input terminal, 3 is a corrected digital signal output terminal, 4 is an APL (average luminance level) signal, and the video signal is integrated by a resistor R ₀ and a capacitor C ₀ . I have gained by doing so.

Now, consider the case where equation (1) is handled with a signal digitized into several bits. Now, assuming that the input signal has n bits, the maximum value _Xmax is _Xmax = ^2n- 1 (0). Therefore, equation (1) can be rewritten as follows.

However, Y _max is the maximum value of the output signal, usually Y _max = X
_max .

 When this equation (3) is converted, the following is obtained.

FIG. 1 is a circuit diagram of Equation (4). The video signal input from the video signal input terminal 1 is A / D-converted by the A / D converter 5 to become a digital video signal a. The digital video signal "a" is corrected by the exponential conversion data stored in the memory 6 as shown in FIG. In FIG. 5, each input / output data is normalized by 4 bits and is indicated by a black circle. The signal b subjected to exponential conversion in the memory 6 is a signal c obtained by A / D converting an APL signal 4 obtained by integrating a video signal with a resistor R ₀ and a capacitor C ₀ by an A / D converter 7 and a flip-flop. After the timing is adjusted in steps 8 and 9, the signals are multiplied by the digital multiplier 10. Further, this signal is corrected by the logarithmic conversion data stored in the memory 11 as shown in FIG. In FIG. 6, the input data is 23 or more and the output data is crushed because the input is 23 or less in an actual signal correction circuit (FIG. 3) to be described later.

By this point, up to e ^{γlog X in the} equation (4) has been obtained. Finally, A / D converted signal c of APL signal 4
(Γ) is converted into a value of X _max ^(1-γ) (15 ^{1−γ in} this example) by the memory 12, and further multiplied by the logarithmically converted signal d by the digital multiplier 15, and finally A corrected digital signal f is obtained.

As described above, according to the present embodiment, the three memories 6, 11, 1
As long as the fixed data of exponential conversion, logarithmic conversion, and function X _max ^(1-γ) conversion are stored in 2, the fine resolution that depends to a maximum on the resolution of the A / D converter and the resolution of the digital multiplier Correction can be realized with a minimum memory capacity.

Note that 13, 14, and 16 in the figure are also flip-flops for adjusting timing.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing a signal correction circuit according to a second embodiment of the present invention. In this figure, the difference from FIG. 1 is that the memory 12 and the digital multiplier 15 are replaced by
The point is that the bit shift circuit 18 is included. FIG. 1 and FIG. 2 are the same until e ^{γlog X} in equation (4) is obtained. After that, in the first embodiment, the logarithmically converted signal d
And X _max ^(1−γ) to obtain a finally corrected digital signal f. In the second embodiment, the same effect is obtained by the bit shift circuit 18. Now, from equation (0), X _max = 2 ⁿ -1.
_max ≒ 2 ⁿ . Therefore, X _max ^(1−γ) = 2 ^{n (1−γ)} (5) Here, if n (1−γ) is an integer, X _max ^(1−γ) = 2 ^m (m = n (1−γ), m is an integer), and multiplying it by the signal d logarithmically converted by the digital multiplier 2 is the same as shifting left by m bits.

Therefore, the bit shift circuit 18 can be used instead of the digital multiplier 15.

Now, in equation (5), n = 4, If, since the ^{_{X max (1-γ) =}} 2 2, 2 4, 2 6, the value of gamma, it can be seen that it is sufficient two bits bit shift to the left and right.

FIG. 3 is a specific circuit diagram of a signal correction circuit according to a second embodiment of the present invention. Since the configuration of the above circuit diagram is the same as that of the block diagram of FIG. 2, the details will be skipped.
For the video signal of bit, by its APL, Correction is applied. FIG. 4 shows the relationship between the input and output of the entire system when the 4-bit video signal is corrected with the same configuration as that of the circuit diagram, and shows the logarithmic conversion, exponent of memory 6 (IC3) and memory 11 (IC7). The input and output relationships of the converted data are shown in FIGS. 5 and 6, respectively.

Because of the 4-bit operation, the data has considerably discrete values, but the operation can be confirmed.

As described above, by using the data selector as the bit shift circuit 18 instead of the digital multiplier 15, the value of the γ constant is restricted, but the digital multiplier 15 and the memory 12 can be removed. The configuration can be simpler than the embodiment.

In the first embodiment, the digital multiplier 10 is used to multiply the exponentially converted video signal b and the digitally converted APL signal c, but this may be replaced by an adder. Good.

Effect of the Invention As described above, the present invention multiplies a memory provided with data for logarithmically converting a video signal digitized into several bits by the logarithmically converted signal and a digitized APL (average luminance level) signal. A digital multiplier and a memory having data for performing exponential conversion of the signal output from the digital multiplier, and a flip-flop that adjusts the timing of each signal is provided between the respective circuits, thereby achieving an APL.
Can be applied to the video signal as desired, and the image quality of an image display device driven in picture element units can be maximized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a signal correction circuit according to a first embodiment of the present invention, FIG. 2 is a block diagram of a signal correction circuit according to a second embodiment of the present invention, and FIG. FIG. 4 is a characteristic diagram showing an input / output relationship of the signal correction circuit in the second embodiment, and FIG. 5 is a data input / output relationship of the memory 1 (logarithmic conversion) in the embodiment. 6, FIG. 6 is a characteristic diagram showing an input / output relationship of data of the memory 2 (exponential conversion), FIG. 7 is a characteristic diagram showing a characteristic of y = ^xγ , and FIG. FIG. 9 is a block diagram showing the basic principle of the signal correction circuit, FIG. 9 is a circuit diagram of a conventional signal correction circuit, and FIG. 10 compares the luminance characteristics and gradation of an image display device driven by a cathode ray tube and a picture element unit. FIG. 5,7 …… A / D converter, 6,12,13 …… Memory, 10,15 …… Digital multiplier, 8,9,13,14,16 …… Flip-flop, 18…
... bit shift circuit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-56-107674 (JP, A) JP-A-49-126214 (JP, A) JP-A-56-64570 (JP, A) JP-A 61-76 258567 (JP, A)

Claims (1)

(57) [Claims] 1. A video signal and an average luminance level signal obtained by integrating the video signal are digitized.
An A / D converter, a first memory having data for logarithmically converting the digitized video signal, and a digital multiplier for multiplying the logarithmically converted signal and the digitized average luminance level signal A second memory having data for exponentially converting the signal output from the digital multiplier, and a multiplier for multiplying the exponentially converted signal by a function of the average luminance level signal, A signal correction circuit comprising a flip-flop between each circuit for adjusting the timing of each signal.