JP2590743B2 - Wireless selective call receiver with data communication function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio selective call receiver for performing data communication, and more particularly to a radio selective call receiver configured to be able to communicate received data with an external device.

[0002]

2. Description of the Related Art In recent years, radio selective call receivers have been used not only for calling specific persons but also for receiving information such as stock prices and receiving e-mails, and have been used for data terminal applications. Is also increasing. For this reason, there has been proposed a wireless selective call receiver which can be connected to an external device such as a personal computer and has a function of transferring received data by communication from a request from the external device. For example,
In the radio selective calling receiver described in Japanese Patent Application Laid-Open No. Sho 62-268219, an external device is connected to the receiver by optical means, and the received data is transferred to the external device by an optical signal. Machine has been proposed.

In such a radio selective calling receiver, when performing data communication with an external device, the data is processed by a low-speed clock output from an oscillator built in the receiver. May be missed, and the data communication efficiency may be low. Therefore, it has been considered to perform processing using a high-speed clock generated on the external device side or using a high-speed clock output from a second oscillator built in the receiver.

[0004]

However, the radio selective calling receiver operates on a low-speed clock with little noise by the built-in oscillator when the receiving unit is performing the message receiving operation when it is on. If a high-speed clock is used in the data communication process at the time of this ON, clock noise may occur, the reception quality may be degraded, or the reception operation may not be possible. For this reason, data communication must be performed with a low-speed clock, which causes the above-mentioned data to be missed and a decrease in transfer efficiency. Alternatively, data communication must be performed by a high-speed clock when no message is received,
If a call occurs at that time, a new problem arises in that the message cannot be received.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a communication system that performs data communication while receiving a message without deteriorating reception quality.
An object of the present invention is to provide a radio selective calling receiver with improved efficiency and reliability of data communication with an external device.

[0006]

SUMMARY OF THE INVENTION A radio selective calling receiver according to the present invention includes a means for generating a low-speed first clock signal, a means for generating a high-speed second clock signal, and an operation for receiving these clock signals. And a selection means for selecting a clock in accordance with the ON / OFF state of the clock signal to use the clock for data communication.

[0007] For example, the radio selective calling receiver of the present invention comprises:
A receiving unit that receives a call signal, a receiving unit control circuit that intermittently operates the receiving unit, a data communication control circuit that controls data communication between data in the received signal and an external device, and a data communication control unit that controls the data communication. A data communication buffer interposed between the circuit and an external device, a first oscillator for generating a low-speed first clock signal, a second oscillator for generating a high-speed second clock signal, and the first clock signal. A clock switch for selecting a second clock signal, wherein the reception unit control circuit outputs a reception unit operation ON / OFF signal to intermittently operate the reception unit, and the data communication control circuit performs data communication operation. Controlling the clock switch based on the on / off signal, selecting the second clock signal when the operation of the receiving unit is on, and selecting the first clock signal when the operation of the receiving unit is off. And performs data communication by-option clock signal.

Further, according to the present invention, a data communication control circuit comprises:
The data communication buffer is controlled simultaneously with the control of the clock switcher. When the operation of the receiver is on, the buffer capacity used for data communication is small, and when the operation of the receiver is off, the buffer capacity used for data transfer is large. It is preferable to configure so that

[0009]

According to the present invention, when performing data communication processing between a receiver and an external device, the reliability of data communication is improved by performing processing based on a high-speed clock signal when the operation of the receiver is off. And improve the data communication processing speed. In addition, when the operation of the receiving unit is on, processing is performed based on a low-speed clock signal, thereby reducing noise at the time of reception and improving reception quality.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a radio selective call receiver with a data communication function according to the present invention. In FIG. 1, a receiver includes a receiving unit 1 that performs intermittent reception with a selection signal transmitted from a base station, a receiving unit control circuit 2 that controls the receiving unit 1, a memory 3 that stores received message data, A data communication control circuit 4 for controlling data communication;
A data communication buffer 5 for temporarily storing data when transferring data to and from an external device is provided.
The receiving unit control circuit 2 and the data communication control circuit 4
And a first oscillating unit 6 for generating a low-speed first clock c1 used for driving the data communication control circuit 4 and a speed higher than the speed of the first clock signal c1 used for driving the data communication control circuit 4. A second clock signal generating a second clock signal c2;
An oscillator 7 is provided.
A clock switch 8 for switching between a low-speed clock c1 and a high-speed clock c2 based on a switching signal d from the data communication circuit 4 and supplying the same to the data communication circuit 4.
And

FIG. 2 shows the configuration of the data communication buffer 5. The data communication buffer 5 has a serial / parallel (S
/ P) conversion circuit 51, a parallel / serial (P / S) conversion circuit 52, an input / output buffer 53, a selector 54, a selector 55, and a buffer controller 56. The selector 54 is connected to the data communication control circuit 4.
And SIN and SOUT are connected to external devices.
S / P conversion circuit 51 and P / P
It is connected via the S conversion circuit 52.

The input / output buffer 53 is composed of n (n is a plurality) buffers, and is configured to function as an input buffer or an output buffer depending on which of the selectors 54 and 55 is connected. You. Also,
The S / P conversion circuit 51 converts a signal transmitted from an external device from serial data to parallel data, and transmits the signal to the input / output buffer 53. The S / P conversion circuit 52 converts the parallel data sent from the input / output buffer 53 into serial data, and sends the serial data to an external device.

The selectors 54 and 55 are controlled by a buffer controller 56, and it is set which of the n buffers constituting the input / output buffer 53 performs transmission and reception. Further, the buffer controller 56 turns on the receiving unit 1 output from the receiving unit control circuit 2,
The selectors 54 and 55 are controlled based on the off signal b. By controlling these selectors 54 and 55, the n buffers of the input / output buffer 53 are set to either the input buffer or the output buffer, and the usage ratio of the input / output is adjusted. FIG. 3 shows an example of the usage ratio of the input / output buffer when the receiving unit is on and off.

The operation of the receiver having the above configuration will be described with reference to the timing chart of FIG. In the figure, a is a timing chart of a transmission signal transmitted from the base station, b is an on / off timing chart of a message receiving operation in the receiver 1 of the receiver, and d is a clock switching signal output from the data communication circuit. FIG. 4C is a timing chart of a clock signal selected by the clock switch 70 and supplied to the data communication control circuit 4. Now, own receiver is group 1
After the completion of the synchronization pull-in, the receiving unit control circuit 2 intermittently turns the receiving operation on and off with the on / off signal b in accordance with the timing of the transmission signal of group 1. , Perform a battery saving operation.

When receiving section 1 receives the transmission signal of group 1, receiving section control circuit 2 analyzes whether or not the signal is a paging signal addressed to its own receiver. A predetermined notification operation is performed, and a message included in the call signal is stored in the message memory 3. Then, the data included in this message is sent to the data communication buffer 5 via the data communication control circuit 4, and is transferred from this to an external device connected to the receiver.

Here, the low-speed clock signal c1 from the first oscillator 6 is always input to the receiver control circuit 2,
The receiving unit 1 performs a receiving operation based on the low-speed clock signal. On the other hand, the clock signal c selected by the clock switch 8 is input to the data communication control circuit 4, and the data communication buffer 5 is operated based on the clock signal c to execute data communication.

At this time, the data communication control circuit 4 switches the clock switch 8 at the timing of ON / OFF of the receiving operation in the receiving unit 1 and at the same time, the selectors 54 and 55 of the data communication buffer 5 and the input / output buffer 53 , That is, the capacity of the data communication buffer is switched. Here, during data communication and when the operation of the receiving section is off, the high-speed clock signal c1 is selected by the clock switch 8 by the control signal d, and at the same time, the data communication buffer 5 is set in the small capacity state so that the input buffer is reduced. Switch to.
Conversely, when the operation of the receiving section is ON even during data communication, the clock switch 8 selects the low-speed clock signal c2 by the control signal d, and simultaneously sets the data communication buffer 5 to a large capacity state so that the number of input buffers increases. Switch.

Here, an example of the operation of data communication between the receiver and the external device will be described. FIG. 5 shows a communication protocol for data communication. There is a transfer request ENQ from the external device (101), and when the receiver receives this, the receiver sends an ACK to the external device (102). External device is A
When the CK is received, a command is sent (103). After receiving the command, the receiver transmits the data requested by the command from the receiver to the external device (10).
4). Here, the data length transmitted from the receiver is shown in FIG.
Is transmitted with a fixed block length as shown by. for that reason,
If the transmission data is large, it is transmitted in several blocks. The external device sends an ACK after the block reception is completed (105). After receiving this ACK, the receiver performs block transmission again if there is a next block transmission (10
6). Thereafter, transmission and reception of this ACK (107) and block transmission are repeated, and if there is no next block transmission in the receiver, an END signal is transmitted (108) and the communication is terminated.

FIG. 7 is a flowchart showing a data communication operation in the receiver in the above-mentioned protocol. When there is an ENQ from an external device (201), an ACK is transmitted (202), and a command request waits (203). When a command is transmitted, it is determined whether the operation of the receiving unit 1 is on or off (204), and clock switching and buffer switching are performed. That is, when the receiving unit 1 is on, the clock is set to the low-speed clock c1, and the input / output buffer 53 of the data communication buffer 5 is switched to a large-capacity buffer having more input buffers (205). When the receiving unit 1 is off, the clock is set to the high-speed clock c2, and the input / output buffer 53 of the data communication buffer 5 is switched to a small capacity with a reduced number of input buffers (206).

Thereafter, the data requested by the command from the receiver side is transmitted as a block to the external device (207). After the block transmission, the clock is set to the low-speed clock, and the data communication buffer 40 is switched to the large-capacity buffer (20).
8). After that, it waits for ACK and waits for AC from the external device.
K is waited for (209), and the presence or absence of the next block is determined (210). If there is a next block transmission, the process returns to (204). If there is no next block transmission, an END signal is sent to end the communication. .

As described above, in the receiver of this embodiment, when performing data communication processing with an external device, the data is processed based on a high-speed clock signal when the operation of the receiving unit 1 is off. The reliability of communication can be improved, and the data communication processing speed can be improved. Also, the receiving unit 1
By performing processing based on a low-speed clock signal during reception operation, noise at the time of reception can be reduced and reception quality can be improved.

By switching the capacity of the data communication buffer simultaneously with the switching of the clock signal, the capacity of the buffer can be set to a capacity corresponding to the speed of the clock signal. Data communication can be suitably performed.

Here, in the above-described embodiment, the clock signal is switched and the capacity of the data communication buffer is switched according to the ON / OFF of the receiving operation of the receiving unit.
When the data communication buffer has room, even if only the clock signal is switched, the same effect as in the above embodiment can be obtained.

[0024]

As described above, according to the present invention, a low-speed first clock signal is supplied to a radio selective calling receiver for intermittently receiving a calling signal and performing data communication of the received data with an external device. Since there are provided a means for generating, a means for generating a high-speed second clock signal, and a selecting means for selecting these clock signals in accordance with the ON / OFF state of the receiving operation and using the clock signals as a clock for data communication. By performing data communication processing based on a high-speed clock signal when the operation of the receiving unit is off, the reliability of data communication can be improved and the data communication processing speed can be improved. Further, when the operation of the receiving unit is on, by performing data communication processing based on a low-speed clock signal, noise at the time of reception by the receiving unit can be reduced and reception quality can be improved.

Further, according to the present invention, a data communication control circuit comprises:
The data communication buffer is controlled simultaneously with the control of the clock switcher. When the operation of the receiver is on, the buffer capacity used for data communication is small, and when the operation of the receiver is off, the buffer capacity used for data transfer is large. With this configuration, the buffer capacity required for data communication can be secured without affecting the receiving operation in the receiving unit, and suitable data communication can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a radio selective calling receiver according to the present invention.

FIG. 2 is a block diagram illustrating an example of a data communication buffer.

FIG. 3 is a diagram illustrating an input / output distribution ratio of an input / output buffer in a data communication buffer.

FIG. 4 is a timing chart showing the operation of the radio selective calling receiver of the present invention.

FIG. 5 is a flowchart showing an operation of data communication in the radio selective calling receiver of the present invention.

FIG. 6 is a format diagram of data to be transmitted in blocks.

FIG. 7 is a diagram showing a protocol of data communication in the radio selective calling receiver of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Receiving part 2 Receiving part control circuit 3 Message memory 4 Data communication control circuit 5 Data communication buffer 6 First oscillator 7 Second oscillator 8 Clock switch

Claims (4)

(57) [Claims] A means for generating a low-speed first clock signal in a radio selective call receiver having a function of receiving a call signal and communicating data included in the received signal with an external device; Means for generating a high-speed second clock signal;
Selecting means for selecting a clock for data communication in accordance with the off state, and a radio selective call receiver with a data communication function. 2. A receiving section for receiving a call signal, a receiving section control circuit for intermittently operating the receiving section, a data communication control circuit for controlling data communication between data in the received signal and an external device, and A data communication buffer interposed between the data communication control circuit and an external device;
A first oscillator for generating a clock signal, a second oscillator for generating a high-speed second clock signal, and a clock switch for selecting the first clock signal and the second clock signal; Outputs a receiver operation ON / OFF signal to intermittently operate the receiver, the data communication control circuit controls a clock switch based on the ON / OFF signal during the data communication operation, and operates the receiver. A radio selective call receiver with a data communication function, wherein the second clock signal is selected when the receiver is turned on, the first clock signal is selected when the operation of the receiver is turned off, and data communication is performed using the selected clock signal. 3. The data communication control circuit controls the data communication buffer simultaneously with the control of the clock switcher, reduces the buffer capacity used for data communication when the operation of the receiver is on, and reduces the buffer capacity used for data communication when the receiver is off. 3. The radio selective call receiver with a data communication function according to claim 2, wherein a buffer capacity used for data transfer is large. 4. The receiving section is operated intermittently so as to perform a receiving operation in synchronization with a transmission signal of a group to which the calling signal of the own receiver belongs, and at the time of the receiving operation, the receiving operation is performed based on a first clock signal. The wireless selective call receiver with a data communication function according to claim 2 or 3.