JP2590378B2 - Logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. INDUSTRIAL APPLICATIONS The present invention relates to logic circuit networks, more specifically,
Apparatus and method for compensating for significant fluctuations in power supply voltage fluctuations, circuit parameters and environmental parameters. More particularly, the present invention relates to a current switch comprising a dynamically and dynamically controllable resistor and current source and having an associated control circuit.
Emmitta Follower (Current Switch Emitter Followe
r-CSEF) circuit. These controllable resistors and current sources are each controlled by two independent variable control signals to independently adjust the output logic signal level of the CSEF circuit. The network of the present invention consumes very little power and uses a low voltage power supply to generate logic circuit output even if the power supply voltage, circuit temperature, and device parameters vary significantly. Are controlled so that the logical high level and low level are maintained substantially constant above and below the reference voltage. According to the present invention, by keeping the high level and the low level stable, extremely small logic signal levels can be used, so that the switching speed of the circuit, that is, the operation speed of the circuit, can be increased. Moreover, the power consumption of the circuit can be reduced.

B. Prior Art Power Switch / Emitter / Follower Logic Circuit, ie CS
EF circuits are known. A typical conventional CSEF circuit is shown in FIG. 1 of U.S. Pat. No. 4,575,647 and U.S. Pat.
Column) and FIGS. 1 and 2 of U.S. Pat. No. 3,501,647.

The operation of a typical CSEF logic circuit is necessary to understand the present invention and will be described below. First, reference is made to FIG. 3 which shows a simplified logic circuit 1 having a logic signal input terminal and an output terminal, a power supply voltage input terminal of a power supply device and an auxiliary control signal input terminal. The logic circuit 1 includes one such as OR (OR), NOR (Noah), NAND (Nand), and the like.
Or a standard CSEF circuit that performs more logical functions (emitter coupled logic-
Also called). This circuit typically has one or more logic signal inputs and one or two logic signal outputs. In the case of two outputs, one output is typically the logical complement of the other output. Also,
A standard CSEF circuit, which is an active device, has one
Or more voltage sources, which are supplied by positive and negative voltages from a power supply, commonly shown in FIG. 3 as V _CC and V _EE . ing. Also, other voltages _VT and V called the reference voltage
_REF is supplied from the same power supply. V _REF may be a ground potential.

Details of the input, output and voltage application terminals of the conventional logic circuit 1 shown in FIG. 3 are shown in FIG. In the circuit of FIG. 4 showing an n-input OR / NOR gate, input transistors 12, 14, and 16 are provided in a parallel configuration to receive one or more logic signal inputs. Although three input transistors are shown,
Fewer or more input transistors can be used. Transistor 12,
The bases of 14 and 16 are connected to the input terminal I to receive an input logic signal represented by a high level or a low level.
N ₁ , IN ₂ ... IN _n are connected.

The collectors of the transistors 12, 14 and 16 are connected in common and are connected to a resistor 26 which is supplied with a voltage from the voltage V _CC of the positive voltage power supply. Transistor 1
2, 14, and 16 are connected together with the fourth transistor 18 to form a differential amplifier circuit configuration, and the collector of the fourth transistor 18 is connected to the terminal of the voltage V _CC via the resistor 28. I have. The base of transistor 18 is connected to a first logic level reference voltage V _REF . Although the reference voltage V _REF of the first logic level is set to the ground potential here, another potential may be used. The emitters of these four transistors 12, 14, 16 and 18 are commonly connected to the collector of a fifth transistor 22 and this fifth transistor
Transistor 22 operates as a constant current source for the differential amplifier circuit. The emitter of the transistor 22 is connected via a resistor 32 to a second terminal of the power supply to which the negative voltage _VEE is applied. A second logic level reference voltage, control signal _VCS, is applied to the base of transistor 22. In conventional circuits, signal _VCS is used to provide some control over the low level of the output signal.

In the prior art circuit of FIG. 4, two output transistors 10 and 20 are provided which are connected in an emitter-follower configuration, the emitters of these transistors being:
It is connected to one end of respective resistors 24 and 30, the other end of these resistors 24 and 30 are connected to the second voltage terminal V _T of the power supply. The input voltage to the base of transistor 10 is provided from the commonly connected collectors of transistors 12, 14 and 16, while the input voltage at the base of transistor 20 is provided from the collector of transistor 18. Emitter of the transistor 10 and 20 are respectively connected to the output terminal OUT ₁ and OUT _2.

The operation of the circuit of FIG. 4 is known. Terminals IN ₁ , IN ₂
.. the corresponding transistors 12, 14 when at least one of the input signals applied to IN _n is at a high (positive) level
Or 16 turns on, thereby forcing most of the current flowing through the fixed source transistor 22 to flow through the associated transistor 12, 14 or 16 and the resistor 26. Accordance connexion, the transistor 18 is turned off, the transistor 20 is turned on, thereby the output signal of the terminal OUT ₂ to a higher level. Base voltage of the transistor 10 is lower than the base voltage of the transistor 20, the terminal OUT ₁ is at the low level. In this way, the input terminals IN ₁ , IN ₂ ...
A logical OR of the signals on IN _n is generated at terminal OUT ₂ , and
Logical NOR of these signals is generated on the terminal OUT _1.

In the conventional typical CSEF logic network, the fourth
Many circuits as shown are included in a single integrated circuit chip. Power to the chip is provided by an external power supply that is not on the chip. The power supply voltages V _CC , V _EE , V _T and V _{REF, which} are usually drawn from the same power supply, are intended to be kept constant, but in practice the voltages of these power supplies are many logical Since a large variable current is supplied to the circuit, some fluctuation occurs. Nominally +1.4
A typical voltage fluctuation of the voltage value V _{CC in} volts is ± 85 millivolts. Variations in V _CC or V _EE cause variations (noise) in the output level of the logic circuit, which adversely affects the performance of the circuit.

Because of this variation, the transistors 10 and
Twenty relative high and low output levels are combined with the signal noise to compensate for good communion between the circuits on the chip, so that ± 350 It must be kept a little higher than millivolts. As a result, this higher voltage will limit the switching speed of the circuit, as it requires larger signal voltage swings and longer turn-on and turn-off times for the circuit elements. . Fluctuations due to environmental factors, such as temperature, and fluctuations in circuit element parameters, such as resistance and transistor gain, can increase signal swings to overcome noise due to this type of fluctuation. Must have a negative effect on the performance of the circuit.

Stabilizes the fluctuation of the voltage V _CC or V _EE of the main power supply,
Several other methods have heretofore been proposed to compensate for or to stabilize or compensate for temperature variations and device parameter variations. These methods use either a current source controller or a voltage divider or a clamping circuit of a Schottky barrier diode. However, these conventional circuits either do not accurately track changes in the V _CC voltage, or other voltage, or only track the center of the reference level, or have one of two logic output levels. The level of the temperature can be adjusted only, or the compensation of changes in temperature and device parameters cannot be accurately achieved, or a relatively high voltage power supply must be used. Either
They provide only some compensation or introduce other drawbacks.

In U.S. Patent No. 4575647, control signal V _CS is generated as an input to the base of (a transistor as a transistor 22 in the conventional circuit shown in FIG. 4) the current source transistor. This signal, in cooperation with the respective oppositely connected Schottky barrier diodes, maintains the high and low output levels symmetrically above and below the center of the reference voltage. The disadvantage of this solution, however, is that only one control point is provided. Even if only the _VCS is changed, independent tracking and control of each output level cannot be performed. Also, symmetric outputs are not always profitable, and the use of a single control signal provides complete compensation for variations in V _CC , temperature, or device parameters. is not. In addition, the output signal cannot be reduced below the forward voltage drop of diode 44 shown in this patent.

U.S. Pat. No. 4,709,169 discloses a different circuit and method for controlling the output level of a CSEF circuit. The required additional current is drawn through resistors 26 or 30 of FIG. 3 of this patent (similar to resistors 26 and 28 of FIG. 2). In this circuit, a shot barrier diode is used. The disadvantage of this circuit is that the extra output capacitance at the critical output nodes 10 and 12 of FIG. 3 (similar to the base terminals of transistors 10 and 20 of FIG. 4 of the present specification) is increased. is there. The need for extra power to drive this circuit is also a disadvantage of this circuit.

Other power level control devices are disclosed in U.S. Pat.
It is described in a document entitled "Emitter-Coupled Logic Circuit" on December 2, 975, IBM Technical Disclosure Bulletin, Vol. 15, No. 7, pages 2178 to 2179. However, these devices suffer from weaknesses such as not providing sufficient compensation for variations in the V _CC supply voltage, or the inability to independently control both the high and low levels. I have.

Therefore, conventional methods of adjusting the power supply voltage do not adequately compensate for power supply voltage fluctuations, temperature, or fluctuations in device parameters, so the higher and lower voltage levels generated by the circuit are not compensated. Must be maintained relatively high with respect to the reference voltage level of the logic signal (ground potential in the case of the circuit of FIG. 4). This is, of course, undesirable because it does not have a positive effect on the nominal noise margin, ie the allowable noise width, and has a negative effect on the operating speed of the circuit.

C. Problems to be Solved by the Invention The present invention provides a novel current switch logic circuit that solves the above-mentioned problems, and the circuit of the present invention minimizes the output signal swing. The high and localized voltage levels can be reduced and are largely independent of power supply voltage variations, junction temperature variations, and absolute device parameter variations, and at the same time, The operation speed of the circuit can be maximized, and the power consumption of the circuit can be minimized.

An object of the present invention is to perform precise control on the level of a logic signal in order to reduce swing of an output signal.

D. Means for Solving the Problems The apparatus of the present invention generates an adjustable first logic level and another adjustable second logic level in response to at least one input signal. Circuit element having at least one input terminal, an output terminal, a complement output terminal, at least one power supply terminal for receiving power, device parameters and a first control terminal. A control circuit connected to the logic circuit and having a second control terminal; a voltage of a power supply, a temperature of a circuit element, and components of the logic circuit.
Means for independently generating a first control signal and a second control signal in response to a parameter change; and a power supply voltage change, element temperature change, and device parameter change of a logic circuit element. Regardless, means for applying control signals to the first and second control terminals, respectively, so as to maintain the first and second control terminals at predetermined different reference levels.

In an embodiment of the present invention, the control circuit includes a load resistor,
One or more controllable dynamic resistors, including one or more types of transistors, connected across the resistors, and one or more, the other, controllable to control the dynamic resistance. A controllable current amplifier including a transistor of the type and a means for applying a signal to the current amplifier that changes the dynamic resistance in order to keep the logic signal level constant with respect to a reference voltage.

In another embodiment of the present invention, the logic circuit includes a compensating current switch emitter-follower circuit having a controllable current source connected to a differential amplifier configuration driving the emitter-follower output transistor. First and second
The control signal and the inputs of the logic circuit and the control circuit are generated by a control signal generator including a circuit using a logic level reference voltage generator and a sample generator in the feedback circuit.

Further, the invention includes a method for generating an adjustable first logic level and another adjustable second logic level in response to at least one input signal;
The method includes the steps of generating a first control signal and a second control signal, each step being a function of at least one power supply voltage value of a power supply, a temperature of a circuit device, and device parameters. , Respectively, so as to maintain the first and second logic levels at different predetermined reference levels, respectively.
And separately controlling the first and second logic levels by the second logic level.

By using a signal generator controlled by a feedback circuit and a dynamic resistor, the high output logic level and low output logic level of the power supply are maintained independently of the power supply and changes in environmental conditions. Is compensated over a large range. This reduces the nominal output signal swing without reducing the worst case signal swing. In addition, the output levels need not be symmetrical with respect to any reference level, and relatively low voltage power supplies can be used. According to the simulation results of the embodiment of the present invention, the reduced signal swing has a higher performance (speed) than the conventional standard CSEF circuit.
It has been found that circuits with a 20% increase are easily achievable.

E. Embodiment Referring to FIG. 1, a block diagram of one embodiment of the present invention is shown. However, the invention is not limited to this particular embodiment.

In FIG. 1, a logic circuit 1 provides one or more output signals in response to one or more logic signal inputs, similar to the circuit shown in FIG. Power of the logic circuit, the voltage V _CC of the main power supply, V _EE, is by connexion supplied to V _T and V _REF. In this embodiment, V _REF is the ground potential. The difference between the voltages V _CC and V _EE is for example, about 3 volts, the difference between V _CC and V _T are, for example, about 2 volts.

A feature of the present invention resides in using the control circuit 42 of the power supply device. Since the power supply control circuit 42 is powered by the same voltage as V _CC and V _T used to power the logic circuit 1,
Or does not require a separate power supply. The control circuit 42 provides an input voltage V _CR of the fifth to the logic circuit 1. In the particular embodiment shown in FIG. 2, this fifth voltage input V
_CR is provided from node 60 to resistors 26 and 28 of logic circuit 1. As can be seen by comparing FIGS. 2 and 4, this circuit arrangement is such that only resistors 26 and 28 receive the mains supply stabilization voltage V _CR and the same voltage V _CC It differs from conventional circuit arrangements in that it is supplied to the collectors of transistors 10 and 20.

Input voltage V _CR of the power supply control circuit 42 nodes is maintained by the connexion constant 60 is a voltage which is stabilized against V _CC and V _EE varies. In the embodiment of FIG. 1, the control circuit has three inputs: a main power supply voltage V _CC , a power supply second voltage V _T, and a second control signal V _CCC . Thus, the voltage V _CR is a function of the inputs V _CC , V _T and V _CCC .

The second control signal V _CCC , which is a variable voltage, is generated by a control signal generator 40 (see FIG. 1) which is another feature of the present invention. Further, the signal generator 40 on the input to the logic circuit 1, for generating a first control signal V _CS is variable voltage. The input to the signal generator 40 is a voltage of a standard power supply V _CC, V _EE, V _T and V _REF. Signals V _CCC and V _CS
Are fed back to the signal generator 40 to form a closed feedback loop.

Control signal V _CCC and V _CS, the voltage V _CC, V _EE, V _T and V _REF
In response to temperature fluctuations of elements constituting the logic circuit 1 and fluctuations occurring in device parameters.
The primary purpose of V _CCC is to control the high level of the logic output of logic circuit 1 with respect to V _REF , and the primary purpose of V _CS is to control the low level of the logic output with respect to V _REF . It is in. Accordingly, differences between signal levels are also controlled. Each control signal affects both levels due to the nature of the feedback circuit of signal generator 40. Thus, the control signals V _CCC and V _CS and the control circuit 42 and its output V _CR maintain the output level of the logic circuit 1 in close proximity to these preselected ideal reference levels. As such, it achieves the function of the present invention to stabilize voltage variations, temperature variations, and device parameter variations. Normal,
These "ideal" levels are chosen to be as small as possible to speed up circuit operation.

A specific embodiment of the circuit arrangement of the control circuit 42 is shown in FIG. In FIG. 2, the circuit portion enclosed by a dashed line is the conventional typical CS shown in FIG. 4 except that the voltage V _{CR at} node 60 has been replaced by a connection at V _CC .
The same circuit as EF is shown. As already mentioned, in the present invention, the terminal of the voltage V _CC of the power supply device is not connected to the resistors 26 and 28 unlike the conventional circuit. Instead, the load resistor 50 and the first control transistor 52
_Provided during the parallel configuration between the V _CC terminal and node 60, node 60 is connected to resistors 26 and 28. In the preferred embodiment, transistor 52 is a bipolar transistor and the transistors used in the logic circuit (i.e., transistors 10, 12, 14, 16, 18, 20, and 2).
It is desirable that the transistor is of the opposite type to the type of 2). In this embodiment, transistor 52 is PN
P type, transistors 10, 12, 14, 16, 18, 20
And 22 are of the NPN type. The emitter of transistor 52 is connected to the V _CC terminal and its collector is connected to node 60; in addition, transistor 52 is configured to operate as a dynamic resistor responsive to a signal applied to its pace. Have been.

The collector of the second control transistor 54 is connected to the base of the transistor 52. Emitter of the transistor 54 is connected to the resistor 56, the other end of the resistor 56 is connected to one of the second voltage terminal V _T of the power supply. The pace of transistor 54 receives a first variable control signal V _CCC from control signal generator 40.

Transistor 54 operates as a current amplifier and provides additional amplification for the V _CCC signal, but if the beta value (gain) of transistor 52 is high (ie, greater than 60), the circuit will operate. It is not always necessary. In practice, such a high beta value is difficult to achieve for an integrated PNP transistor, but if it were, the control signal V _CCC would be inverted and connected in series with the base of transistor 52. Can be directly input to the resistor.

A resistor 50 having the same value as the maximum resistance required of transistor 52 for the range of the voltage V _CC of the power supply operates to reduce the burden of current to be supplied by transistor 52. This increases the effective beta value of transistor 52, and additionally reduces the required base current. As a result, the overall power required for control circuit 42 will be reduced.

In another embodiment of the present invention, transistors 52 and 54
And the resistor 56 can be replaced by a field effect transistor (PFET or NFET) whose source-drain current path is between the V _CC terminal and the node V _CR. Connected and its gate electrode receives V _CCC . In such a case, the phase of the V _CCC and the amplitude of the signal, of course, need to be adjusted appropriately.

First variable control signal V from control signal generator 40
_CS is input to the base of the transistor 22 in the logic circuit 1 of the embodiment shown in FIG. The control signal V _CS passes through the transistors 12, 14, 16 and 18 and indirectly
The current changes through 10 and 20 and through the current path of the collector-emitter of transistor 22. Control signal V _CS
Controls transistor 22 and the voltage at node 60 is V _CCC
As a result, the voltage and current at the output of the CSEF circuit are kept substantially constant at a predetermined level, and thus the noise is minimized, so that the amplitude of the output signal is minimized. It is possible to limit the swing.

FIG. 5 shows the control signal generator 40 of the present invention shown in FIG.
The control signal generator controls the control signals V _CCC and V _CS
Used to generate and. In FIG. 5, a high level sample generator 70 and a high level reference voltage generator 72 are provided, the outputs of which are supplied to a first differential amplifier 74. A low-level sample generator 76 and a low-level reference voltage generator 78 are provided, and the respective outputs are supplied to a second differential amplifier 80.

The high-level sample generator 70 provides a logical high-level output of the actual level of the high-level output signal generated by a typical CSEF circuit in a typical operating environment (eg, in a semiconductor chip in a central processing unit). It is intended to generate the voltage value of the signal. The high level sample generator 70 includes, for example, logic circuitry associated with the control circuit 42 of FIG. 2 having one or more input transistors that are always "off", i.e., fixed at a low level. It is one. These inputs are connected to the low level reference voltage generator 78.
Can be taken from In one embodiment, the high level output of high level sample generator 70 is in the range of +350 millivolts to -50 millivolts when the feedback loop is open. When the feedback loop is closed, the output voltage is the same as the output of the reference voltage generator.

The high level reference voltage generator 72 of FIG. 5 provides a standard reference high level logic signal (ie, the "ideal" high level logic output required for the particular configuration and environment intended for the CSEF circuit). Level (a higher level voltage value). A typical voltage at the output of reference voltage generator 72 is on the order of +150 millivolts. A specific example of a reference voltage generator 72 is described in, for example, IBM
Technical Disclosure Bulletin Vol. 30 No. 10
Issue 27, “Reference Generator Insensitive to Power S”
upply Variations),
7 is the circuit shown in FIG. 6 of the drawings attached to this specification.

A differential amplifier that receives as inputs the outputs of the high level sample generator 70 and the high level reference voltage generator 72.
The output of 74 is the second control signal V _CCC . Differential amplifier 74
May be a circuit described in the above-mentioned document or a bipolar differential amplifier such as the circuit shown in FIG. The required gain of the differential amplifier 74 is determined by the amount of change chosen to allow for the DC output logic level of the CSEF circuit 1. In embodiments of the present invention, a gain of 100 has been found to be sufficient. Output V of amplifier 74
_CCC is the input to the control circuit 42 (FIG. 1) of the power supply, and more specifically, the input to the base of the transistor 54 (FIG. 2). This V _CCC signal controls the high level absolute value of the CSEF logic, and is also fed back to both sample generators 70 and 76 to control the control signal V CC.
The control of both the _CCC and V _CS, in order to more closely, to form a closed loop, so that separate both the high level and the low level of the logic circuit, to more effectively control.

In an embodiment of the present invention, a low level sample generator 76, a low level reference voltage generator 78 and a differential amplifier
For 80, a similar circuit arrangement is provided. For example, the low level sample generator 76 is always "on", ie, fixed to a high level, with the standard CSEF logic circuit 1 of FIG. 2 (with control circuit 42).
Or more input transistors of circuit 1. These inputs can be taken from the high level reference voltage generator 72. In this way, the lower level
Sample generator 76 generates the voltage value of the low level output signal of the actual low level output signal generated by the typical CSEF logic circuit in a particular operating environment. In an embodiment of the present invention, this low level output is -200
Millivolts to -300 millivolts.

For example, a low-level reference voltage generator 78 such as the circuit shown in the above-mentioned document or the circuit shown in FIG.
Generates the "ideal" low level standard reference logic low level voltage value for the particular configuration and environment of the CSEF logic circuit. In certain embodiments of the invention, the low level signal is a voltage on the order of -230 millivolts.

The outputs of the low level sample generator 76 and the reference voltage generator 78 are applied to the input of a differential amplifier 80, which is, for example, a differential bipolar amplifier with a gain of 100 as shown in FIG. . The differential amplifier 80 is a CSEF logic circuit 1.
(Fig. 1), more specifically transistors
22 (FIG. 2) has an output which is a second control signal (V _CS ) for the input to the base. This V _CS signal is
Control the difference between the high and low levels of the circuit,
It is also fed back to both the sample generators 70 and 76 to form a closed loop for tighter control of the V _CS and V _CCC signals, thereby providing higher and lower output levels of the logic circuit. Control the levels separately and more effectively.

Accordance connexion, the control signal fed back circuit arrangement of generator 40 (FIG. 5), the voltage V _CC of the main power supply, V _EE and control in such a manner to compensate for variations in V _T voltage V _CCC and V
_Provides a means to change _CS . The control circuitry arrangement also helps to compensate for temperature variations and device parameter variations of various devices in the CSEF circuit by using the sample generator. Thus, the nominal output signal swing can be reduced without reducing the worst case signal swing. Reference voltage generator of high level and low level, and the variation of the voltage V _CC, V _EE and V _T, but is independent of variations in temperature and device parameters, high level and low proportional directly to the V _REF Give level criteria.

FIG. 6 is a specific example of a circuit described in the above-mentioned document that can be used for the reference voltage generators 72 and 78 of FIG. FIG. 7 shows a specific example circuit shown in the above-mentioned document that can be used as the differential amplifiers 74 and 80 of FIG.

In FIG. 6, the voltages V _CC and V _EE of the power supply are input to terminals 88 and 91, respectively. As one example, these two
Some circuits between the two terminals have the following elements connected in series. That is, the first path is connected to the resistor 84
A path between the collector and the emitter of the transistor 82;
Including a resistor 83. The second path includes a resistor 84 and a resistor
85, a path between the collector and emitter of transistor 86, and a resistor 87. The third path includes the path between the collector and the emitter of transistor 89 and a resistor 90. The fourth path includes a resistor 92, a collector-emitter path of transistor 93, and a resistor 94.
The fifth path includes a path between the collector and the emitter of the transistor 95 and a resistor 96. The base of transistor 82 receives power supply voltage V _REF which is a ground potential. The bases of transistors 86 and 93 are both transistors 89
Connected to the emitter. The bases of transistors 89 and 95 are connected to the collectors of transistors 86 and 93, respectively.

For optimal operation, the V _BE of transistor 82 is made the same as the V _{BE of} transistor 89 and
V _BE of transistor 95 is the same as V _{BE of} transistor 95. In addition, the resistance of the resistor 83 is made the same as the resistance of the resistor 84,
The ratio between the value of the resistor 92 and the value of the resistor 94 is made the same as the ratio of the sum of the resistance values of the resistors 84, 85, and 87 and the resistance value of the resistor 87.

The output terminal of FIG. 6, taken from the emitter of transistor 95, provides a high level reference signal for input to amplifier 74 of FIG. 5 or a low level reference signal for input to amplifier 80 of FIG. Supply. These logical level reference signal, V _CC, and V _EE and V _T, is independent of temperature and device parameters, follows the V _REF.

FIG. 7 shows the differential amplifier 74 shown in FIG.
2 shows a differential amplifier used in any of the differential amplifiers 80. The appearance of the circuit of FIG. 7 is similar to the circuit of FIG. 6, but the circuit of FIG. 7 has a completely different function from the circuit of FIG. Power supply voltages V _CC and V _EE are applied to terminals 106 and 108, respectively. In the embodiment of FIG. 7, some current paths connected between these two terminals are as follows. That is, the first passage is the resistance 110
And the path of the collector-emitter of the transistor 111;
And a resistor 112. The second path includes a resistor 110, a resistor 113, a collector-emitter path of transistor 114, and a resistor 115. The third path includes the collector-emitter path of transistor 116 and resistor 117. The fourth path includes resistor 98, the collector-emitter path of transistor 99, the collector-emitter path of transistor 118, and resistor 119. The fifth path includes the resistor 100 and the collector of the transistor 101.
It includes an emitter path, a collector-emitter path of transistor 118, and a resistor 119. The sixth path includes a collector-emitter path of the transistor 102;
And a resistor 103. The base of the transistor 111 is
In this embodiment, the voltage _VREF of the installed power supply is applied. The bases of transistors 114 and 118 are both connected to the emitter of transistor 116. The bases of transistors 116 and 102 are transistors
It is connected to the collectors of 114 and 101, respectively. The transistor 118 operates as a constant current source.

For auxiliary operation, the resistances of resistors 98 and 100 are the same, and the resistances of resistors 110, 112 and 113 are also equal. In addition, the ratio between the resistor 98 (or the resistor 100) and the resistor 119 is determined by adding the resistance of the resistor 110 to the value of the resistor 113 and the resistance of the resistor 115.
Is the same as the ratio of the total value obtained by adding twice the value of the resistor 115 to the value of the resistor 115.

When the circuit of FIG. 7 operates as the differential amplifier 74 of FIG. 5, the input "A" from the high level sample generator 70
Is applied to the base of transistor 101, and input "B" from high level reference voltage generator 74 is applied to the base of transistor 99. Output, that is, control signal V
_CCC is derived from the emitter of transistor 102.

When the circuit of FIG. 7 is used as the differential amplifier 80 of FIG. 5, a similar circuit will operate. in this case,
The input "C" from the low level sample generator 76 is
The input “D” applied to the base of transistor 99 and from low level reference voltage generator 78 is applied to the base of transistor 101. The output of this circuit is a transistor
A control signal V _CS taken from 102 of the emitter. Seventh
The elements on the left side of the circuit shown (ie, transistors 111, 114,
116 and 118, and resistors 110, 112, 113, 115, 117 and 11
Element 9) operates to maintain an output which is not affected by external fluctuations by a stable constant current source configuration. The voltage at the output of the circuit of FIG. 7 varies in proportion to only the difference between the voltages at the two inputs, the circuit comprising V _CC ,
And voltage V _EE, V _T, is independent of variations in the temperature and device parameters of the circuit.

The operation of the embodiment of the present invention will be described below. First, consider the voltage V _{CC of the} power supply. If a transient voltage drop occurs at this voltage, this voltage drop causes the output of sample generator 70 and sample generator 76 (FIG. 5) to momentarily fluctuate to a lower order, , Differential amplifier 74
And 80. Since the outputs of the reference voltage generators 72, 78 are independent of the fluctuations in the voltage of V _CC and V _EE , the outputs of the reference voltage generators 72, 78 are not affected by the aforementioned fluctuations. As a result, the control signal V _CCC at the output of the amplifier 74 is
Increased by the magnitude as a function of the variation of the voltage of V _CC and V _EE, and the control signal V _CS at the output of amplifier 80, V _CC and V
It is reduced by a magnitude as a function of the _EE voltage variation.

V _CCC applied to the base of transistor 54 (FIG. 2)
The signal causes almost simultaneous fluctuations in the current gated through transistor 54, and in turn, the current through the base of transistor 52. In turn, this variation is due to transistor 52
In the resistance of the emitter-collector current path at the same time. In an embodiment of the present invention, the dynamic resistance of transistor 52 is
_CC is above the "median" nominal V _CC of +1.4 volts
When changing from a rise of 200 millivolts to a drop of 200 millivolts down, it varies from 0 ohms to almost infinity. This change is large enough to maintain the ideal reference very high level in the output OUT ₁ and OUT ₂ are close to the level of the circuit. When V _CC is at its nominal value (ie, when the current is centered at the nominal value), the emitter-collector resistance of transistor 52 is approximately equal to the resistance of resistor 50. If the voltage V _CC rises, the transistor 52 will be turned off more (allowing a smaller current to flow), and the emitter-collector resistance of the transistor 52 will increase, which means that V _CC and V _CR The voltage across is lowered.

Transistors 52 and 54 have a response time that is fast enough to reflect almost simultaneous changes in control signal V _CCC , which in turn changes almost simultaneously with changes in power supply voltages V _CC and V _EE. . Resistor 56 controls the base of transistor 52 and operates in conjunction with transistor 54 to provide current amplification and helps increase the gain of the feedback loop. As a result, the output level of the logic circuit becomes the voltage V _T
Is almost irrelevant to changes in

In addition, V _CS changes almost simultaneously with the change in V _EE . For example, if V _EE increases more positively, V _CS will increase.

Another feature of the present invention is that the voltage regulating circuit (signal generator 40
And the overall power consumption required by the control circuit 42) is small. In this embodiment, when a PNP type transistor is used, the power consumed by the control circuit 42 can be extremely reduced.
52 (FIG. 2) uses a PNP transistor.
The power required by one CSEF logic circuit can be calculated by the following equation.

In the above equation, i _SW is the switch current flowing through transistor 52, β is the base current of transistor 52 for collector current gain, and α is the collector current of transistor 54, the emitter current and Is the ratio of Since the resistor 50 provides half of the current of the current switch, i _SW is divided by two. Because of this circuit arrangement, the control signal generator 40 consumes only a small amount of power even if the power supply distributes current to many logic circuits.
Also, the same sample generator, reference voltage generator and differential amplifier can be used for the same power supply used for other logic circuits.

By using the present invention, the nominal high and low levels of +150 mV and -220 mV at the output of CSEF logic 1 (FIG. 2) can be V _CC , V _EE , or
Even if the _VT voltage changes to 20%, it can be changed at 1% or less. Similarly, when the ambient temperature is between 45 ° C and 85 ° C
, These output levels vary by less than 1%, and the device parameters of the logic circuit (eg, resistors 26, 28 and 32, or transistor 1)
When the V _{BE of} 0, 12, 14, 16, 18, 20, and 22 varies in the range of 20%, the corresponding elements of the sample generators 70 and 76 (FIG. 5) respond accordingly. It changes at the rate mentioned above.
In other words, the present invention compensates for all variations in typical semiconductor manufacturing in device parameters. The magnitude of control described above can reduce the output level to a magnitude that gives a standard CSEF logic circuit at least a 20% speed increase.

The signal generator 40 (FIG. 5) is provided on the same chip as the CSEF circuit so as to more accurately track device parameter variations of the circuit. This distributes two control signals V _CCC and V _CS to a plurality of CSEF logic circuits. It is anticipated that the number of logic circuits capable of receiving these signals from the same generator will be over 400.

The control provided by the present invention can be performed at low voltage operation, so that if the logic circuits operate at the same current, the power consumption is low. this is,
In addition to improved performance, CSEF logic using the same type of device can be provided with devices that operate at higher speeds.

Another advantage of the present invention is that the control circuit 42, the sample generator
If 70 and differential amplifier 74 (FIG. 2) are designed to operate at sufficiently high speed, high frequency switching noise from the power supply (noise generated by the driver,
That is, Δi noise) can be filtered. If a capacitor is connected to node 60 of control circuit 42, an additional filtering action is obtained.

As described above, the high and low levels indicate the power supply voltage fluctuation, the PN junction temperature fluctuation,
The present invention can reduce the swing of the output signal of the ordinary current switch logic circuit to a minimum width, since it hardly changes due to the parameter variation. Thus, maximum speed and minimum power consumption can be achieved simultaneously.

Thus, the present invention solves a significant problem faced by designers of high performance logic circuits, that is, it can effectively compensate for voltage fluctuations caused by the above-described environment. This can provide better noise margin for small signals.

F. Effects of the Invention As described above, the present invention can reduce the swing of the output signal of the power switch logic circuit to a minimum level, and the high and low levels can reduce the voltage fluctuation of the power supply device. And a current switch logic circuit that is largely independent of variations in the temperature of the PN junction and absolute parameters of the device.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
FIG. 3 is a block diagram of a conventional CSEF logic circuit, FIG. 4 is a schematic circuit diagram of the logic circuit of FIG. 3, and FIG. 5 is a schematic circuit diagram of the embodiment of FIG. block diagram of an embodiment of a fed back circuit of the present invention that can be used to generate a control signal V _CCC and V _CS is used as the input of the circuit of FIG. 2, FIG. 6 is a reference voltage generator of Figure 5 72 And 78
FIG. 7 is a schematic circuit diagram showing one example of the differential amplifier of FIG.
It is a schematic circuit diagram of an example of 74 and 80. 1 ... Logic circuit, 40 ... Control signal generator, 42 ... Power supply control circuit, 70 ... Higher level sample generator, 72 ... Higher level reference voltage generator, 74, 80 ... Differential Amplifier, 76 …… Low level sample generator, 78…
… Low-level reference voltage generator, V _CC , V _EE , V _T , V _REF …
… Main power supply voltage, V _CR … Fifth voltage, V _CS … First
Control signal, V _CCC ...... the second control signal.

Continuation of the front page (72) Inventor Jyogi Eel-Smith, Third, 24 Minor Drive, Wappingards Guards, New York, USA (56) References JP-A-54-62766 (JP, A) JP-A-53 65051 (JP, A) JP-A-47-30261 (JP, A)

Claims (1)

(57) [Claims] 1. A logic circuit connected between a first power supply node and a second power supply node for generating a logic output that changes between a first logic level and a second logic level in response to an input signal. A power switch / emitter follower logic circuit including a current source transistor having a first control terminal; a first power supply connected to the first power supply node; a second power supply; A power supply control circuit connected between a power supply and the second power supply node, the power supply control circuit having a second control terminal; and a first sampler representing the first logic level actually generated from the logic circuit. A first sample generation circuit for generating a level, a first reference voltage generation circuit for generating a first reference voltage for the first logic level of the logic circuit, and the first sample level and the first sample level. Based on the difference from the first reference voltage A first control signal generation circuit including a circuit for supplying a first control signal to the first control terminal; and a second sample signal representing the second logic level actually generated from the logic circuit. A second sample generation circuit for generating a level, a second reference voltage generation circuit for generating a second reference voltage for the second logic level of the logic circuit, and the second sample level and the second sample level. A second control signal generating circuit including a circuit for supplying a second control signal to the second control terminal based on a difference from a second reference voltage.