JP2589855B2 - Thin film for InAs Hall element - Google Patents
Thin film for InAs Hall elementInfo
- Publication number
- JP2589855B2 JP2589855B2 JP2157743A JP15774390A JP2589855B2 JP 2589855 B2 JP2589855 B2 JP 2589855B2 JP 2157743 A JP2157743 A JP 2157743A JP 15774390 A JP15774390 A JP 15774390A JP 2589855 B2 JP2589855 B2 JP 2589855B2
- Authority
- JP
- Japan
- Prior art keywords
- inas
- thin film
- hall element
- electron mobility
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910000673 Indium arsenide Inorganic materials 0.000 title claims description 109
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 title claims description 109
- 239000010409 thin film Substances 0.000 title claims description 84
- 239000000758 substrate Substances 0.000 claims description 60
- 239000000463 material Substances 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 11
- 230000037230 mobility Effects 0.000 description 63
- 239000010410 layer Substances 0.000 description 40
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 17
- 239000013078 crystal Substances 0.000 description 9
- 230000007423 decrease Effects 0.000 description 9
- 238000001451 molecular beam epitaxy Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 230000005355 Hall effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000010445 mica Substances 0.000 description 1
- 229910052618 mica group Inorganic materials 0.000 description 1
- 239000012044 organic layer Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910000859 α-Fe Inorganic materials 0.000 description 1
Landscapes
- Hall/Mr Elements (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、抵抗値の温度変化の極めて小さい新規な二
層構造をもつInAsホール素子用薄膜からなるInAsホール
素子用素材に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a material for an InAs Hall element comprising a novel thin film for an InAs Hall element having a novel two-layer structure having a very small change in resistance value with temperature.
従来、InAsホール素子を作る方法としては、単結晶の
InAsをつくりこれをスライスし、ついで研磨により薄く
した材料を用いる方法、マイカ基板上に蒸着したInAs多
結晶薄膜をはがしてフェライト等の基板上に接着したも
のを用いる方法、GaAs基板上に成長させたInAs薄膜を用
いる方法等がある。Conventionally, as a method of making an InAs Hall element, a single crystal
A method of making InAs, slicing it, and then using a material thinned by polishing, a method of peeling the InAs polycrystalline thin film deposited on a mica substrate and using a material that is adhered to a substrate such as ferrite, and growing on a GaAs substrate There is a method using an InAs thin film.
しかし、上に述べた第一の方法では工業的に一定の厚
さでInAs薄膜を製作することや、それを１μｍまたはそ
れ以下の厚さにすることが非常に難しく量産的でない。
第二の方法では、InAs薄膜の厚さは一定にそろえられる
が、薄膜と基板の間に接着剤として有機物の絶縁層が形
成されるため、100℃をこえる高温で動作させるInAsホ
ール素子を製作する材料としては好ましいものとはいい
がたい。第三の方法は、InAs薄膜と基板との界面には有
機層のようなものはなく高温までの使用に耐えうる。し
かし、InAsと基板とは異種材料であるため、基板との界
面付近のInAs単結晶は基板との格子不整合のために多く
の格子欠陥を有し、かつ結晶格子も乱れていることは知
られていた。このため、このInAs薄膜をホール素子とし
て利用すると抵抗値の温度変化が大きく、すなわち60℃
付近から抵抗値が温度の上昇とともに低下してゆく特性
をもっている。このため、この材料を用いたホール素子
は、100℃をこえて一定電圧の入力で使用すると、上述
の抵抗値の低下により発熱量が増大し素子温度が上昇し
更に抵抗値を下げるという自己暴走的なモードが有り、
ホール素子駆動上の大きな欠点をもっている。したがっ
て、この薄膜をホール素子として利用するには、100℃
以上で負である抵抗値の温度係数をほとんど零もしくは
正にする改善が必要である。However, in the first method described above, it is extremely difficult to manufacture an InAs thin film with a constant thickness industrially and to reduce the thickness to 1 μm or less, and it is not mass-produced.
In the second method, the thickness of the InAs thin film is kept constant, but an organic insulating layer is formed as an adhesive between the thin film and the substrate. It is difficult to say that the material to be used is preferable. In the third method, there is no such thing as an organic layer at the interface between the InAs thin film and the substrate, and it can be used up to a high temperature. However, since InAs and the substrate are different materials, it is known that the InAs single crystal near the interface with the substrate has many lattice defects due to lattice mismatch with the substrate, and the crystal lattice is also disordered. Had been. For this reason, when this InAs thin film is used as a Hall element, the resistance value changes greatly with temperature, that is, 60 ° C.
It has the characteristic that the resistance value decreases with increasing temperature from around. For this reason, when a Hall element using this material is used with a constant voltage input exceeding 100 ° C, the self-runaway that the heating value increases, the element temperature rises, and the resistance value further decreases due to the above-mentioned decrease in resistance value There is a typical mode,
It has a major drawback in driving the Hall element. Therefore, to use this thin film as a Hall element,
It is necessary to improve the temperature coefficient of the negative resistance value to almost zero or positive.
GaAs上に成長させたInAs薄膜の抵抗値の温度変化をキ
ャリアー濃度を増やして少なくすることが可能である
が、実用素子としてキャリアー濃度ｎには上限があり、
キャリアー濃度を大きくすることによってだけでは、室
温から100℃付近までしか抵抗値の温度変化を少なくす
ることは期待できない。なぜならホール素子の駆動条件
から決まるInAs薄膜のシート抵抗値に下限があるためで
ある。しかも電子濃度の温度変化の他に電子移動度の温
度変化が100℃以上ではかなり大きく、抵抗値の温度変
化を後者が支配するようになる。このため、従来の技術
では厚さ1.4μｍ以下のInAs薄膜の抵抗値の温度変化を1
00℃以上においても小さくする技術は見出いだされてい
なかった。すなわち、実用的なホール素子を製作するの
に好都合の厚さ1.4μｍ以下のInAs薄膜において、100℃
以上での抵抗値の温度変化を小さくすることや温度の上
昇にともなう抵抗値の低下をなくすことは、従来未踏の
技術であった。その理由の一つは、このように薄いInAs
薄膜を単純に基板上に形成した場合は、電子移動度の温
度変化はバルクの状態とは異なっており、その温度変化
の様子も十分理解されていないことによる。It is possible to reduce the temperature change of the resistance value of the InAs thin film grown on GaAs by increasing the carrier concentration, but there is an upper limit to the carrier concentration n as a practical device.
The increase in carrier concentration alone cannot be expected to reduce the temperature change in resistance only from room temperature to around 100 ° C. This is because there is a lower limit to the sheet resistance of the InAs thin film determined by the driving conditions of the Hall element. In addition to the temperature change of the electron concentration, the temperature change of the electron mobility is considerably large when the temperature is 100 ° C. or more, and the temperature change of the resistance value is dominated by the latter. Therefore, in the conventional technology, the temperature change of the resistance value of the InAs thin film having a thickness of 1.4 μm or less
No technique has been found to reduce the temperature even at 00 ° C. or higher. That is, at a temperature of 100 ° C. for an InAs thin film having a thickness of 1.4 μm or less which is convenient for manufacturing a practical Hall element.
It has been an unexplored technique to reduce the above-mentioned temperature change of the resistance value and to prevent the resistance value from decreasing due to the temperature rise. One of the reasons is that such thin InAs
When a thin film is simply formed on a substrate, the change in electron mobility with temperature is different from the bulk state, and the state of the temperature change is not fully understood.
また実用ホール素子の製作において、利用上の利便さ
やコストの要求から微少な（0.4mm角以下の）ホール素
子チップを作る必要があるが、この場合入力電流を流し
たときの消費電力による発熱が微少な部位に集中する。
このため、抵抗値の温度変化をできるだけおさえ、理想
的には温度上昇とともに抵抗値が下がらなくする必要が
あるが、現在まで実現されていない。In the production of a practical Hall element, it is necessary to make a small (0.4 mm square or less) Hall element chip due to the demand for convenience and cost in use. In this case, heat generated by power consumption when input current flows is generated. Focus on small areas.
For this reason, it is necessary to suppress the temperature change of the resistance value as much as possible, and ideally, the resistance value does not decrease as the temperature rises, but this has not been realized until now.
本発明の目的は以上に説明した問題点を解消し、100
℃以上で150℃付近の温度まで使用できるInAsホール素
子用素材を提供することにある。特にこの素材は、抵抗
値が温度とともに低下しない特性をもつホール素子を提
供し、厚さ1.4μｍ以下で、かつ電子移動度が二層構造
を有するInAs薄膜からなるInAsホール素子用素材であ
る。An object of the present invention is to solve the problems described above,
It is an object of the present invention to provide a material for an InAs Hall element which can be used at a temperature of 150 ° C. or higher to a temperature of about 150 ° C. In particular, this material is a material for an InAs Hall element which provides a Hall element having a property that the resistance value does not decrease with temperature and is made of an InAs thin film having a thickness of 1.4 μm or less and having a two-layered electron mobility.
このような問題点を解決するために本発明者は、基板
上にエピタキシャル成長させたInAs薄膜に対して、電子
輸送現象の解析と不純物原子のドーピングによる特性改
善を試みた。すなわち、基板とInAs層との界面の格子不
整合によって界面に近い部分のInAsの格子が乱れるが、
この部分の電気伝導に関する寄与が少なくなるような薄
膜構造を検討した。In order to solve such problems, the present inventors have attempted to analyze the electron transport phenomenon and improve the characteristics of an InAs thin film epitaxially grown on a substrate by doping impurity atoms. That is, the lattice mismatch of the interface between the substrate and the InAs layer disturbs the InAs lattice near the interface,
A thin film structure was studied in which the contribution of this portion to electrical conduction was reduced.
実際には本発明者はGaAs上に成長させた厚さ1.4μｍ
以下のInAs薄膜に、InAsのドナー不純物として使用する
Siのドープを試みた。その結果、まずSiのドープ量の増
大とともにInAs薄膜中の電子濃度が大きくなったがさら
に、電子移動度の値 が同一の結晶成長条件にも関わらず電子濃度とともに大
きくなるという現象（第１表）と電子移動度の温度変化
が大きくかわるという現象を見いだした。Actually, the inventor has grown a thickness of 1.4 μm on GaAs.
Used as InAs donor impurity in the following InAs thin films
I tried to dope Si. As a result, first, the electron concentration in the InAs thin film increased with the increase in the Si doping amount. Was found to increase with electron concentration despite the same crystal growth conditions (Table 1), and a phenomenon that the temperature change of electron mobility changed significantly.
次に、InAs薄膜中で電子の動きやすい部分と動きにく
い部分の存在の可能性について調べた。第２表には、In
As中のSiがドープされた位置と電子移動度の関係を示
す。第２表によれば、表面近くにSiをドープしたInAs薄
膜（No.4）は高い電子移動度を示しており、Siのドーピ
ングによりInAs薄膜の電子移動度が大きく向上している
ことがわかる。一方、Siを基板との界面付近にドープし
た場合（No.2）は、電子移動度の向上はみられていな
い。さらに、全体に均一にSiをドープした場合（No.3）
は電子移動度の大きな向上がみられる。このことから、
InAs薄膜では、厚さ方向で電子移動度の値が大きく変化
することが明らかである。すなわち、電流の流れやすい
層と流れにくい層があることが明かとなった。つまり、
このInAs薄膜は基板との界面近くにSiをドーピングして
も低い電子移動度 を示すが、基板との界面からある程度以上離れた部分に
Siをドープすると大きな電子移動度を示すことから、Si
のドーピングによりInAs薄膜が、低い電子移動度をもつ
部分（Ａ層と呼ぶ。）と高い電子移動度をもつ部分（Ｂ
層と呼ぶ。）の二層の構造をもつことは明らかである。Next, the possibility of existence of a part where electrons easily move and a part where electrons do not easily move in the InAs thin film was examined. Table 2 shows In
4 shows the relationship between the Si-doped position in As and the electron mobility. According to Table 2, the InAs thin film (No. 4) doped with Si near the surface shows high electron mobility, and it can be seen that the electron mobility of the InAs thin film is greatly improved by doping with Si. . On the other hand, when Si was doped near the interface with the substrate (No. 2), no improvement in electron mobility was observed. Furthermore, when Si is doped uniformly throughout (No.3)
Shows a significant improvement in electron mobility. From this,
It is clear that the value of the electron mobility changes greatly in the thickness direction in the InAs thin film. That is, it became clear that there were a layer in which current easily flowed and a layer in which current hardly flowed. That is,
This InAs thin film has low electron mobility even if Si is doped near the interface with the substrate Is shown in the area at least a certain distance from the interface with the substrate.
Since doping with Si shows large electron mobility,
Doping makes the InAs thin film a portion having a low electron mobility (referred to as layer A) and a portion having a high electron mobility (B layer).
Called layer. It is clear that the two-layer structure has a two-layer structure.
第３表にはSiをドープしたInAs薄膜の膜厚と電子移動
度の関係を示す。第３表よりSiをドープしたInAs薄膜の
膜厚が厚くなるにしたがい電子移動度が大きくなること
がわかるが、その値は0.1μｍ と0.2μｍの間で急激にかわっており、変化高はこのと
き最大である。さらにこの事実を確かめるためにGaAs基
板上に成長させた0.6μｍ厚さのSiが一様にドープされ
たInAs薄膜を順次エッチングしながら測定した電子移動
度を第４表に示す。この表から0.1μｍ以下の部分は電
子移動度が非常に小さく、低い電子移動度の層であるＡ
層が存在することが実証された。Table 3 shows the relationship between the thickness of the Si-doped InAs thin film and the electron mobility. From Table 3, it can be seen that the electron mobility increases as the thickness of the Si-doped InAs thin film increases, and the value is 0.1 μm. And 0.2 μm, and the height of change is maximum at this time. In order to confirm this fact, Table 4 shows electron mobilities measured while sequentially etching a 0.6 μm-thick Si-doped InAs thin film grown on a GaAs substrate. From this table, the portion having a thickness of 0.1 μm or less has a very small electron mobility, and the low electron mobility layer A
The layer was demonstrated to be present.
この事実を前提に、第５表にはSiをドープしたInAs薄
膜の膜厚と電子移動度の関係及び基板の界面に近い低い
電子移動度部の電子移動度が膜厚に関係なく3,000cm2/V
sとしたときのＢ層の電子移動度を示す。第５表より基
板の界面近くは電子移度が小さく、界面よりはなれた部
分（表面も含む。）は電子移動度が極めて大きい構造と
なっている。すなわち、界面より0.1μｍまでは電子移
動度の 低い層（Ａ層）があり、0.1μｍを境界として表面まで
は電子移動度の極めて大きい層（Ｂ層）がある二層の電
子移動度部が形成されている。 Assuming this fact, 3,000 cm 2 regardless electron mobility of the fifth low-electron mobility portion near the interface between the relationship and the substrate thickness and the electron mobility of InAs thin film doped with Si to table in thickness / V
The electron mobility of the B layer when s is indicated. According to Table 5, the electron mobility is small near the interface of the substrate, and the portion (including the surface) separated from the interface has a structure in which the electron mobility is extremely large. In other words, the electron mobility is less than 0.1 μm from the interface. There is a low layer (layer A), and a two-layer electron mobility portion having a layer (B layer) with extremely high electron mobility is formed up to the surface with a boundary of 0.1 μm.
本発明者はこのように二層の電子移動度部をもつ構造
のInAs薄膜とその作製に関する技術を完成した。すなわ
ち、ドナー不純物のドーピングにより、高い電子移動度
をもち、かつ電子移動度の大きいＢ層部と低い電子移動
部のＡ層をもつInAs薄膜を作製する技術を完成した。The present inventor has thus completed a technique relating to an InAs thin film having a structure having two layers of electron mobility portions and a technique for producing the same. That is, a technique for producing an InAs thin film having a high electron mobility and a B layer having a high electron mobility and an A layer having a low electron mobility by doping with a donor impurity was completed.
更に、本発明者はこのような高い電子移動度部に大量
のドナー不純物をドープした層を有するInAs薄膜の抵抗
値の温度特性の測定を行ない、100℃以上でノンドープ
のInAs薄膜に比べて温度変化が大幅に小さくなる事実を
見いだした。Furthermore, the present inventor has measured the temperature characteristics of the resistance value of the InAs thin film having a layer in which a large amount of donor impurities are doped in such a high electron mobility region, and has a temperature higher than 100 ° C. as compared with the non-doped InAs thin film. We have found that the change is much smaller.
本発明者が作製した二層構造のInAs薄膜のＢ層部はホ
ール効果に寄与する割合が大きく、ドナー不純物のドー
ピングにより電子移動度が向上しており、かつこの部分
を走る電子数も従来のInAs薄膜に比べて増大しており、
薄膜の電気伝導はこの部分が主となる。この結果、InAs
薄膜の特性を大幅に改善することとなった。すなわち、
このInAs薄膜では、電子移動度の温度変化が低温から15
0℃まで極めて小さくなった。したがってドナー不純物
をドープすることにより電子移動度を大きくし、InAs薄
膜の電子濃度の温度変化に依存する抵抗率の温度係数β
ρを室温付近で小さくするとともに、100℃〜150℃にお
ける移動度の温度変化も大幅に小さくなり、この温度に
おける抵抗率の温度係数βρも大幅に小さくなった。第
３図には本発明のInAs薄膜の電子移動度の温度変化をグ
ラフにより示し、従来例と比較した。また、第４図に
は、本発明のInAs薄膜の抵抗率の温度特性をグラフによ
り示し、従来例と比較した。従来技術のInAs薄膜に比
べ、高温部において電子移動度、抵抗率とも大幅に温度
変化が小さくなっている。しかも150℃という高温まで
抵抗率がほぼ一定であるという従来にない特性を示して
いる。この結果、本発明のInAs薄膜は、低温部から高温
部まで抵抗率の温度係数が大幅に小さくなり、すなわち
厚さ1.4μｍ以下のInAs薄膜の抵抗値（正しくは抵抗
率）の温度係数をほとんど零もしくは非負の値にならし
めることを達成した。The B layer portion of the InAs thin film of the two-layer structure produced by the present inventors has a large contribution to the Hall effect, the electron mobility is improved by doping of the donor impurity, and the number of electrons running in this portion is the same as the conventional one. Increased compared to InAs thin film,
This portion is mainly used for electric conduction of the thin film. As a result, InAs
The characteristics of the thin film were greatly improved. That is,
In this InAs thin film, the temperature change of electron mobility changes from low temperature to 15
It became extremely small up to 0 ° C. Therefore, the electron mobility is increased by doping with the donor impurity, and the temperature coefficient β of the resistivity, which depends on the temperature change of the electron concentration of the InAs thin film,
As ρ was reduced near room temperature, the temperature change in mobility at 100 ° C. to 150 ° C. was also significantly reduced, and the temperature coefficient βρ of resistivity at this temperature was also significantly reduced. FIG. 3 is a graph showing a temperature change of the electron mobility of the InAs thin film of the present invention, and compared with a conventional example. FIG. 4 is a graph showing the temperature characteristics of the resistivity of the InAs thin film of the present invention in a graph and compared with the conventional example. As compared with the conventional InAs thin film, the temperature change in both the electron mobility and the resistivity is significantly smaller in the high temperature part. Moreover, it shows an unprecedented characteristic that the resistivity is almost constant up to a high temperature of 150 ° C. As a result, the temperature coefficient of the resistivity of the InAs thin film of the present invention is significantly reduced from the low temperature portion to the high temperature portion, that is, the temperature coefficient of the resistance value (correctly, the resistivity) of the InAs thin film having a thickness of 1.4 μm or less is almost reduced. Achieved zero or non-negative values.
これらのことにより、GaAs半絶縁性基板上に成長させ
た厚さ1.4μｍ以下で、二層構造の電子移動度部を有す
るInAsエピタキシャル薄膜を用いて、温度領域−40℃か
ら＋150℃まで抵抗値の温度による低下がほとんどないI
nAsホール素子用素材を作製する技術を実現した。As a result, using an InAs epitaxial thin film grown on a GaAs semi-insulating substrate with a thickness of 1.4 μm or less and having a two-layered electron mobility region, the resistance value from -40 ° C to + 150 ° C in the temperature range Almost no temperature drop I
The technology for fabricating materials for nAs Hall elements has been realized.
この結果、本発明のInAsホール素子用薄膜は、従来の
ように60℃を越えると抵抗値が温度の上昇とともに低下
するという現象がなくなり、この薄膜をホール素子に利
用したときにはInAsホール素子の定電圧駆動上での大き
な問題が解決する。さらに、微小素子を作っても温度の
上昇にともなって抵抗値が下がらないため電流が増大せ
ず、消費する電力が増大しないため余分な発熱もなく、
安定に高温まで動作することが明かとなった。このた
め、汎用性の高い高感度InAsホール素子の信頼性が大き
くアップするとともに駆動電圧も大きくでき、大きな出
力を得ることも可能となった。その結果InAsホール素子
の実用上の特性を大幅に向上することができた。As a result, the thin film for an InAs Hall element of the present invention does not have the phenomenon that the resistance value decreases as the temperature rises when the temperature exceeds 60 ° C. as in the prior art. A major problem in voltage driving is solved. Furthermore, even if a small element is made, the resistance value does not decrease as the temperature rises, so the current does not increase, and the consumed power does not increase, so there is no extra heat generation,
It became clear that it could operate stably up to high temperature. Therefore, the reliability of the highly versatile high-sensitivity InAs Hall element has been greatly improved, the driving voltage can be increased, and a large output can be obtained. As a result, the practical characteristics of the InAs Hall element were significantly improved.
第１図は、本発明のInAsホール素子用素材の断面図の
例を示す。この素材は、基板の界面近くの低い電子移動
度部と界面よりはなれた高い電子移動度部の二層構造の
薄膜を有している。１は基板を示し、２はInAs薄膜で二
層の構造をしており、21は低い電子移動度のＡ層、22は
高い電子移動度のＢ層を示す。また３はドープされたド
ナー不純物を示している。第２図には本発明の基板上に
成長させた二層の電子移動度を有するInAs薄膜を感磁部
としたホール素子の構造を示した。（ａ）は上面図で
（ｂ）は断面図である。４はホール素子の電極を示し、
５はホール素子の感磁部を示している。FIG. 1 shows an example of a sectional view of a material for an InAs Hall element of the present invention. This material has a two-layered thin film having a low electron mobility portion near the interface of the substrate and a high electron mobility portion separated from the interface. Reference numeral 1 denotes a substrate, 2 denotes an InAs thin film having a two-layer structure, 21 denotes an A layer having a low electron mobility, and 22 denotes a B layer having a high electron mobility. Reference numeral 3 denotes a doped donor impurity. FIG. 2 shows the structure of a Hall element in which an InAs thin film having two electron mobilities grown on a substrate according to the present invention is used as a magnetic sensing part. (A) is a top view and (b) is a cross-sectional view. Reference numeral 4 denotes a Hall element electrode,
Reference numeral 5 denotes a magnetic sensing part of the Hall element.
このような本発明に用いられる基板は一般に、InAs薄
膜を成長できる基板であればGaAs、InP、サファイア、
表面に絶縁層を形成したSi基板等いずれでもよい。Such a substrate used in the present invention is generally GaAs, InP, sapphire, or a substrate on which an InAs thin film can be grown.
Any Si substrate or the like having an insulating layer formed on the surface may be used.
また、本発明で重要な役割を果たす不純物原子として
は一般にInAsドナー不純物として作用するものがよく、
Si,S,Ge等がある。そのドーピング量は少なくともキャ
リア濃度として４×1016個/cm3以上が必要であるが、不
純物原子のドーピング量の限界からキャリア濃度の上限
は８×1017個/cm3である。ホール素子としては好ましく
用いられる1.4μｍ以下の薄膜ではドーパントしてSi,S,
Geが特に好ましい原子である。Further, as the impurity atoms that play an important role in the present invention, those that generally act as InAs donor impurities are better,
There are Si, S, Ge and the like. The doping amount must be at least 4 × 10 16 / cm 3 as the carrier concentration, but the upper limit of the carrier concentration is 8 × 10 17 / cm 3 due to the limitation of the doping amount of the impurity atoms. In a thin film of 1.4 μm or less, which is preferably used as a Hall element, Si, S,
Ge is a particularly preferred atom.
本発明のInAs薄膜のシート抵抗は、ホール素子を実使
用範囲から下限は50Ωである。また、InAsホール素子の
抵抗値は1kΩ以下がよく用いられるためInAs薄膜のシー
ト抵抗値としては400Ω以下が好ましい。The lower limit of the sheet resistance of the InAs thin film of the present invention is 50Ω from the actual use range of the Hall element. Further, since the resistance value of the InAs Hall element is often 1 kΩ or less, the sheet resistance value of the InAs thin film is preferably 400 Ω or less.
InAs薄膜の抵抗率をρ、電子の電荷をｅ、電子濃度を
ｎ、電子のホール移動度をμＨとすると1/ρ＝lelnμＨ
の式より抵抗率ρの温度係数βρは βρ＝（1/ρ）（ｄρ/dT） ＝−（1/n）（dn/dT）＋（−1/μＨ）（ｄμH/dT） と表現できる。電子濃度ｎを十分大きくなるようにする
と、（dn/dT）の大きくないので、第１項の寄与は極め
て少なくなる。つまりｎが十分大きければこの項は抵抗
率の温度変化に寄与しなくなる。このような状況は高温
でｎが大きくなった場合またはドナー不純物のドーピン
グ等により電子濃度ｎを大きくした場合に実現される。
このときは、 βρ＝（1/ρ）（ｄρ/dT） ≒−（1/μＨ）（ｄμH/dT） という関係が成立し、βρ≒−βμＨが成り立つ。すな
わち、βρの温度変化はβμＨによって支配される。し
たがって、抵抗率の温度変化を小さくするには電子移動
度の温度変化を小さくすること、また、高温部でβρ≧
０とするにはβμＨ≦０とすることが必要であり、それ
を実現するのが二層構造の電子移動部を有するInAs薄膜
である。したがって、本発明のInAs薄膜を用いたInAsホ
ール素子は抵抗値の温度変化がなく、高温で抵抗値が低
下することがない。The resistivity of the InAs thin film [rho, the electron charge e, when the electron concentration n, and the hole mobility of the electron and μ H 1 / ρ = lelnμ H
= Temperature coefficient Betaro resistivity [rho than formula βρ (1 / ρ) (dρ / dT) = - (1 / n) (dn / dT) + (- 1 / μ H) and (dμ H / dT) Can be expressed. If the electron concentration n is made sufficiently high, (dn / dT) is not large, and the contribution of the first term is extremely small. That is, if n is sufficiently large, this term does not contribute to the temperature change of the resistivity. Such a situation is realized when n increases at a high temperature or when the electron concentration n is increased by doping of a donor impurity or the like.
In this case, βρ = (1 / ρ) (dρ / dT) ≒ - (1 / μ H) relation (dμ H / dT) is satisfied, βρ ≒ -βμ H holds. That is, the temperature change of βρ is dominated by βμ H. Therefore, in order to reduce the temperature change of the resistivity, the temperature change of the electron mobility must be reduced, and βρ ≧
To achieve 0, it is necessary to satisfy β μ H ≦ 0, and this is achieved by an InAs thin film having an electron transfer portion having a two-layer structure. Therefore, the resistance of the InAs Hall element using the InAs thin film of the present invention does not change with temperature, and the resistance does not decrease at high temperatures.
第５図には、本発明のInAsホール素子用薄膜を用いた
InAsホール素子の入力抵抗値の温度変化の様子を示し
た。第５図は、第４図の薄膜での特性を反映しており、
大幅に温度変化が小さくなっていることを示している。
ここで、（イ）の線は本発明のInAs薄膜を用いたInAsホ
ール素子の抵抗値の温度特性を示し、（ロ）は従来技術
のそれを示している。100℃以上において大幅にβρが
小さくなっている。これは、第１図および第３図に示し
た二層構造の電子移動度部を有するInAs薄膜のμＨの温
度変化を反映したものである。FIG. 5 shows the case where the thin film for an InAs Hall element of the present invention was used.
The state of the temperature change of the input resistance value of the InAs Hall element is shown. FIG. 5 reflects the properties of the thin film of FIG.
This indicates that the temperature change is significantly reduced.
Here, the line (a) shows the temperature characteristic of the resistance value of the InAs Hall element using the InAs thin film of the present invention, and (b) shows that of the prior art. Above 100 ° C., βρ is significantly reduced. This is a reflection of the change in temperature of the InAs thin film mu H having an electron mobility of the two-layer structure shown in Figure 1 and Figure 3.
試作例１ 半絶縁性で厚さ0.3mm、片面を鏡面研磨した直径２イ
ンチのGaAs基板を12枚セットしたホルダーを基板導入室
より準備室を通して大型の分子線エピタキシー装置の超
高真空である成長室へセットした。この基板ホルダーを
水平回転させるとともにGaAs基板を基板加熱ヒーターに
より輻射加熱する。また、基板の鏡面側にはIn,Asおよ
びSiの蒸発源、すなわちクヌーセンセル（Ｋセル）が対
向して装着されている。ＫセルよりIn,Asを５分間蒸発
させ、その後、結晶表面平坦化のため、２分間Asのみ蒸
発させ結晶成長を中断した。２分間の成長中断後、In,A
s,Siの３元素を15分間蒸発させ、SiをドープしたInAs単
結晶で、0.4μｍ厚さの薄膜をGaAsの基板の鏡面側に成
長させた。基板の冷却後、この基板を分子線エピタキシ
ー装置より取り出した。このようにして、第１図（ａ）
に示したInAs薄膜を試作した。基板の界面近くは低電子
移動度であり、表面近くは高電子移動度であってSiがド
ナー不純物としてドープされている。製作したInAsホー
ル素子用薄膜の特性はシート抵抗130Ω、電子移動度15,
000cm2/Vsであった。Prototype Example 1 A semi-insulating, 0.3 mm thick, mirror-polished single-sided GaAs substrate with a diameter of 2 inches and a set of 12 GaAs substrates was passed through the preparation chamber from the substrate introduction chamber to grow a large molecular beam epitaxy apparatus under ultra-high vacuum. Set in the room. The substrate holder is horizontally rotated, and the GaAs substrate is radiantly heated by the substrate heater. On the mirror side of the substrate, evaporation sources for In, As, and Si, that is, Knudsen cells (K cells) are mounted facing each other. In and As were evaporated from the K cell for 5 minutes, and then only As was evaporated for 2 minutes to flatten the crystal surface, and the crystal growth was interrupted. After 2 minutes of growth interruption, In, A
Three elements, s and Si, were evaporated for 15 minutes, and a 0.4 μm thick thin film of Si-doped InAs single crystal was grown on the mirror side of the GaAs substrate. After cooling the substrate, the substrate was taken out of the molecular beam epitaxy apparatus. Thus, FIG. 1 (a)
The InAs thin film shown in Fig. 1 was experimentally manufactured. Near the interface of the substrate has low electron mobility, and near the surface has high electron mobility, and Si is doped as a donor impurity. The characteristics of the fabricated thin film for InAs Hall element are sheet resistance 130Ω, electron mobility 15,
000 cm 2 / Vs.
また、その温度特性を示したのが第３図および第４図
である。第３図は、本発明のInAsホール素子用薄膜の電
子移動度の温度変化を示し、第４図は、本発明のInAsホ
ール素子用薄膜の抵抗率の温度変化を示している。第４
図から、本発明のInAsホール素子用薄膜の抵抗率は150
℃まで低下することがないことが明らかになった。FIGS. 3 and 4 show the temperature characteristics. FIG. 3 shows the temperature change of the electron mobility of the thin film for InAs Hall element of the present invention, and FIG. 4 shows the temperature change of the resistivity of the thin film for InAs Hall element of the present invention. 4th
The figure shows that the resistivity of the thin film for an InAs Hall element of the present invention is 150
It was found that the temperature did not drop to ° C.
この発明のInAsホール素子用薄膜を用いてInAsホール
素子を試作した。試作したホール素子の特性を第６図表
に示す。またその温度特性を示したのが、第５図、第６
図および第７図である。第５図から、本発明のInAs薄膜
を用いたホール素子の入力抵抗値は150℃まで低下する
ことなく、第６図および第７図からホール出力電圧の温
度変化も150℃まで定電圧駆動で−0.12、定電流駆動で 定電圧駆動では入力電圧3V、磁束密度500G 定電流駆動では入力電流1mA,、磁束密度1kG −0.11％であり、極めて小さな値を示すことが明かとな
った。第７表はこうして作製したホール素子の信頼性テ
ストの結果を示す。室温の最大入力電圧は、従来素子に
比べ、約50％向上しており、熱的に大幅に強化されたこ
とを示しており、自己暴走的な高温でのトラブルモード
もなくなった。さらに温度による抵抗値の変化が小さ
く、ほぼ一定値のままであるため、不平衡電圧の温度変
化も 従来のホール素子に比べ、極めて小さくなった。An InAs Hall element was prototyped using the thin film for an InAs Hall element of the present invention. Table 6 shows the characteristics of the prototype Hall element. 5 and 6 show the temperature characteristics.
FIG. 7 and FIG. From FIG. 5, the input resistance value of the Hall element using the InAs thin film of the present invention does not decrease to 150 ° C., and the temperature change of the Hall output voltage can be reduced to 150 ° C. by the constant voltage drive from FIGS. 6 and 7. −0.12, with constant current drive The constant voltage drive has an input voltage of 3V and the magnetic flux density of 500G. The constant current drive has an input current of 1mA and a magnetic flux density of 1kG -0.11%. Table 7 shows the results of the reliability test of the Hall element thus manufactured. The maximum input voltage at room temperature is about 50% higher than that of the conventional device, which indicates that the device has been greatly enhanced thermally. Furthermore, the change in resistance due to temperature is small and remains almost constant, so the temperature change of unbalanced voltage also The size was extremely small as compared with the conventional Hall element.
試作例２ 半絶縁性で厚さ0.3mm、片面を鏡面研磨した直径２イ
ンチのGaAs基板を12枚セットしたホルダーを基板導入室
より準備室を通して大型の分子線エピタキシー装置の超
高真空である成長室へセットした。この基板ホルダーを
水平回転させるとともにGaAs基板を基板加熱ヒーターに
より輻射加熱する。また、基板の鏡面側にはIn,Asおよ
びSiの蒸発源、すなわちＫセルが対向して装着されてい
る。ＫセルよりIn,Asを５分間蒸発させ、その後In,As,S
iを15分間蒸発させ、SiをドープしたInAs単結晶で、0.4
μｍ厚さの薄膜をGaAsの基板の鏡面側に成長させた。基
板の冷却後この基板を分子線エピタキシー装置より取り
出して特性を測定したところ、シート抵抗130Ω、電子
移動度14,000cm2/Vsであった。Prototype Example 2 A semi-insulating, 0.3 mm thick, mirror-polished single-sided GaAs substrate with a diameter of 2 inches and a set of 12 GaAs substrates was passed through the preparation chamber from the substrate introduction chamber to grow a large molecular beam epitaxy apparatus under ultra-high vacuum. Set in the room. The substrate holder is horizontally rotated, and the GaAs substrate is radiantly heated by the substrate heater. On the mirror side of the substrate, evaporation sources for In, As and Si, that is, K cells are mounted to face each other. Evaporate In, As from K cell for 5 minutes, then In, As, S
Evaporate i for 15 minutes and use Si-doped InAs single crystal, 0.4
A μm thin film was grown on the mirror side of the GaAs substrate. After the substrate was cooled, the substrate was taken out of the molecular beam epitaxy apparatus and its characteristics were measured. As a result, the sheet resistance was 130Ω and the electron mobility was 14,000 cm 2 / Vs.
このようにして、第１図（ａ）に示したInAs薄膜から
なるInAsホール素子用素材を試作した。基板の界面近く
は低電子移動度であり、表面近くは高電子移動度であっ
てSiがドナー不純物としてドープされている。In this way, an InAs Hall element material composed of the InAs thin film shown in FIG. Near the interface of the substrate has low electron mobility, and near the surface has high electron mobility, and Si is doped as a donor impurity.
この場合のInAsホール素子用薄膜の温度特性は試作例
１と同等の結果であった。さらに、この本発明のInAsホ
ール素子用素材を用いて試作例１と同様の方法でInAsホ
ール素子を試作した。この場合も、ホール素子の特性は
前記試作例１と同等であり、また、信頼性も同等の結果
を示した。The temperature characteristics of the thin film for the InAs Hall element in this case were the same as those of the prototype example 1. Further, an InAs Hall element was trial-produced in the same manner as in Prototype Example 1 using the InAs Hall element material of the present invention. Also in this case, the characteristics of the Hall element were the same as those of the prototype example 1, and the reliability was the same.
試作例３ 試作例２において、SiのかわりにＳをドーパントして
同様にInAsホール素子用素材を試作した。この場合もSi
のドーパントを用いた試作例１と同等の結果を示した。
さらに、Geをドーパントとした場合も同等であった。Prototype Example 3 In Prototype Example 2, a material for an InAs Hall element was similarly produced by using S as a dopant instead of Si. Again, Si
And the results equivalent to those of Prototype Example 1 using the above dopant were shown.
Furthermore, it was the same when Ge was used as the dopant.
このように、本発明のInAs薄膜を用いたホール素子は
入力抵抗値の温度変化が極めて小さく、さらに、ホール
出力電圧の温度変化も小さく、InAs薄膜に特有の高電子
移動度を利用できるためホール出力電圧を大きくでき
る。As described above, the Hall element using the InAs thin film of the present invention has a very small temperature change in the input resistance value, a small temperature change in the Hall output voltage, and can utilize the high electron mobility specific to the InAs thin film. Output voltage can be increased.
試作例４ 半絶縁性で厚さ0.3mm、片面を鏡面研磨した直径２イ
ンチのGaAs基板を12枚セットしたホルダーを基板導入室
より準備室を通して大型の分子線エピタキシー装置の超
高真空である成長室へセットした。この基板ホルダーを
水平回転させるとともにGaAs基板を基板加熱ヒーターに
より輻射加熱し、基板の鏡面側に対向して装着されてい
るIn,AsおよびSiの蒸発源、すなわちＫセルにより前記
３元素を超高真空中で20分間蒸発させ、Siをドープした
InAs単結晶で、0.4μｍ厚さの薄膜をGaAsの基板の表面
に成長させた。基板の冷却後、この基板を分子線エピタ
キシー装置より取り出して特性を測定したところ、シー
ト抵抗120Ω、電子移動度14,000cm2/Vsであった。Prototype Example 4 Growth of a large molecular beam epitaxy apparatus under ultra-high vacuum through a preparation chamber from a substrate introduction chamber through a holder in which 12 GaAs substrates each having a thickness of 0.3 mm and a mirror-polished one side and having a diameter of 2 inches and having a diameter of 2 inches are set. Set in the room. The substrate holder is rotated horizontally, and the GaAs substrate is radiated and heated by the substrate heater, and the three elements are super-highly heated by the evaporation source of In, As and Si, which is mounted opposite to the mirror surface of the substrate, that is, the K cell. Evaporated in vacuum for 20 minutes, doped with Si
A 0.4 μm thick thin film of InAs single crystal was grown on the surface of a GaAs substrate. After cooling the substrate, the substrate was taken out of the molecular beam epitaxy apparatus and its characteristics were measured. As a result, the sheet resistance was 120Ω and the electron mobility was 14,000 cm 2 / Vs.
このようにして、第１図（ｂ）に示したInAsホール素
子用薄膜からなるInAsホール素子用素材を試作した。基
板の界面近くは低電子移動度であり、表面近くは高電子
移動度であって、Siがドナー不純物としてドープされて
いる。In this way, an InAs Hall element material composed of the InAs Hall element thin film shown in FIG. 1B was prototyped. Near the interface of the substrate has low electron mobility, near the surface has high electron mobility, and Si is doped as a donor impurity.
この場合のInAsホール素子用薄膜の温度特性は試作例
１と同等の結果であった。さらに、このInAsホール素子
用素材を用いて試作例１と同様の方法でInAsホール素子
を試作した。この場合も、ホール素子の特性は前記試作
例１と同等であり、また、信頼性も同等の結果を示し
た。The temperature characteristics of the thin film for the InAs Hall element in this case were the same as those of the prototype example 1. Further, using this InAs Hall element material, an InAs Hall element was prototyped in the same manner as in Prototype Example 1. Also in this case, the characteristics of the Hall element were the same as those of the prototype example 1, and the reliability was the same.
〔発明の効果〕 以上説明したように、本発明によれば室温だけでな
く、100℃から150℃という高温まで安定に動作する高感
度InAsホール素子用薄膜からなるInAsホール素子用素材
を提供することができる。[Effects of the Invention] As described above, according to the present invention, there is provided an InAs Hall element material comprising a highly sensitive InAs Hall element thin film that operates stably not only at room temperature but also at a high temperature of 100 ° C to 150 ° C. be able to.
第１図は、基板の界面近くの低い電子移動度部（Ａ層）
と界面より離れた高い電子移動度部（Ｂ層）の二層構造
のInAs薄膜を有する本発明のInAsホール素子用素材を示
す。 （ａ）はＢ層のみ不純物をドープ、 （ｂ）はＡ層、Ｂ層とも不純物をドープ。 第２図は本発明の基板上に成長させた二層の電子移動度
層を有するInAs薄膜を感磁部としたホール素子の構造
図、 （ａ）は上面図、 （ｂ）は断面図、 第３図は、本発明のInAs薄膜の電子移動度の温度変化を
示すグラフ、 第４図は、本発明のInAs薄膜の抵抗率の温度変化を示す
グラフ、 第５図は、本発明のInAsホール素子用素材を用いて試作
したInAsホール素子の抵抗値の温度変化を示すグラフ、 第６図および第７図は、本発明のInAsホール素子用素材
を用いて試作したInAsホール素子のホール出力電圧の温
度変化を定電圧駆動と定電流駆動でそれぞれ示したグラ
フである。 １……基板， ２……InAs薄膜， 21……Ａ層， 22……Ｂ層， ３……ドナー不純物， ４……電極， ５……ホール素子感磁部。FIG. 1 shows a low electron mobility portion (A layer) near the substrate interface.
2 shows a material for an InAs Hall element of the present invention having a two-layer InAs thin film having a high electron mobility portion (layer B) remote from the interface. (A) Doping impurities only in the B layer, (b) Doping impurities in both the A layer and the B layer. FIG. 2 is a structural view of a Hall element using an InAs thin film having a two-layer electron mobility layer grown on a substrate of the present invention as a magnetic sensing part, (a) is a top view, (b) is a cross-sectional view, FIG. 3 is a graph showing the temperature change of the electron mobility of the InAs thin film of the present invention, FIG. 4 is a graph showing the temperature change of the resistivity of the InAs thin film of the present invention, and FIG. FIGS. 6 and 7 are graphs showing the temperature change of the resistance value of the InAs Hall element prototyped using the Hall element material. FIGS. 6 and 7 show the Hall output of the InAs Hall element prototype produced using the InAs Hall element material of the present invention. 5 is a graph showing a temperature change of a voltage in a constant voltage drive and a constant current drive, respectively. 1 ... substrate, 2 ... InAs thin film, 21 ... A layer, 22 ... B layer, 3 ... donor impurity, 4 ... electrode, 5 ... Hall element magnetosensitive part.
Claims (1)
μｍでかつ低い電子移動度部と高い電子移動度部から成
る二層の電子移動度構造を有し、少なくとも高い電子移
動度部はキャリア濃度（電子濃度）４×1016〜８×1017
個/cm3の範囲でドナー不純物がドープされているInAs薄
膜からなるInAsホール素子用素材1. A method according to claim 1, which is formed on an insulating substrate and has a thickness of 0.2 to 1.4.
μm and has a two-layer electron mobility structure composed of a low electron mobility part and a high electron mobility part. At least the high electron mobility part has a carrier concentration (electron concentration) of 4 × 10 16 to 8 × 10 17.
InAs Hall element material consisting of InAs thin film doped with donor impurities in the range of pcs / cm 3
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2157743A JP2589855B2 (en) | 1990-06-18 | 1990-06-18 | Thin film for InAs Hall element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2157743A JP2589855B2 (en) | 1990-06-18 | 1990-06-18 | Thin film for InAs Hall element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0453177A JPH0453177A (en) | 1992-02-20 |
| JP2589855B2 true JP2589855B2 (en) | 1997-03-12 |
Family
ID=15656382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2157743A Expired - Lifetime JP2589855B2 (en) | 1990-06-18 | 1990-06-18 | Thin film for InAs Hall element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2589855B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7185873B2 (en) | 2001-09-27 | 2007-03-06 | Showa Corporation | Bracket mounting structure of propeller shaft |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6034829B2 (en) * | 1978-10-11 | 1985-08-10 | 旭化成株式会社 | Magnetoelectric transducer and its manufacturing method |
| JPS55148479A (en) * | 1979-05-08 | 1980-11-19 | Matsushita Electric Ind Co Ltd | Hall element device |
-
1990
- 1990-06-18 JP JP2157743A patent/JP2589855B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7185873B2 (en) | 2001-09-27 | 2007-03-06 | Showa Corporation | Bracket mounting structure of propeller shaft |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0453177A (en) | 1992-02-20 |
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