JP2586658B2 - Blur processing circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a blur processing circuit suitable for blurring a cache memory pattern, for example.

[Conventional technology]

In the case of inputting image information from an image reading device such as a one-dimensional image sensor and performing character recognition by a pattern matching method, reduce the enormous amount of image information to a certain amount before comparing patterns. Is valid. In such a case, a blur processing circuit may be used as a circuit for reducing the amount of image information. When a mosaic image is created from a normal image, an operation of replacing a plurality of pieces of image information constituting each of the predetermined sections with one piece of image information is performed. In this case, a similar blur processing circuit is also used. Can be used.

Conventionally, when such a blurring process is performed, a mask pattern is set softly on image information, and the blurring process is performed.

This will be described with reference to FIG. FIG. 3 shows a range of image information (20 pixels in the x direction and 8 pixels in the y direction in the figure). For such image information, a 5 × 5 mask 71 of 5 pixels in each of the x direction and the y direction is provided, and a predetermined weighting is applied to the synthesized 25 pixels, and this is subjected to blur processing for one pixel.

FIG. 4 shows each pixel of this mask, and FIG.
The figure shows the weights corresponding to these. 5x
Each of the pixels a _1, a ₂ of 5 masks 71, ...... e _4, the weight x ₁₁ in e ₅ according to their _{position, x 12, ...... x 54,} x 54 is attached.

Therefore, conventionally sequentially reads performs weighting the pixel a ₁ ~a ₅ of the image information shown in FIG. 3 First, determine the additional value A ₁ by the following equation (1).

_{A 1 = a 1 x 11 +} a 2 x 12 + a 3 x 13 + a 4 x 14 + a 5 x 15 ...... (1) pixel b ₁ ~b ₅ additional value A ₂ to A ₅ by weight of such the following (2 )

A ₂ = b ₁ x ₂₁ + b ₂ x ₂₂ + b ₃ x ₂₃ + b ₄ x ₂₄ + b ₅ x ₂₅ A ₃ = c ₁ x ₃₁ + c ₂ x ₃₂ + c ₃ x ₃₃ + c ₄ x ₃₄ + c ₅ x ₃₅ A ₄ = d _{1 x 41 + d 2 x 42} + d 3 x 43 + d 4 x 44 + d 5 x 45 A 5 = e 1 x 51 + e 2 x 52 + e 3 x 53 + e 4 x 54 + e 5 x 55 ...... (2) where (1 ) the added value a ₁ was calculated by the formula and the total sum a (a = a _1), then replaces the value of the total sum a by adding the addition value a ₂ to the content of the total sum a (a = A + A ₂ ).
In the same manner, sequentially replaces the value of the total sum A with the value of the addition value A ₃ to A _5, finally obtains a total sum A, writes this in a predetermined memory as the value for the blurring processing Had gone.

[Problems to be solved by the invention]

As described above, in the conventional blur processing, such calculation processing is repeatedly performed using a CPU (Central Processing Unit), so that calculation of the blur processing takes a considerable amount of time, particularly when the size of the max becomes large. There is a problem that the processing speed becomes slow. In addition, there is a problem that the CPU cannot be used efficiently because the CPU is occupied for the blur processing during the calculation period.

SUMMARY OF THE INVENTION Accordingly, a first object of the present invention is to provide a blur processing circuit capable of performing a blur processing operation without intervention of a CPU.

A second object of the present invention is to provide a blur processing circuit capable of changing various types of calculation for blur processing.

A third object of the present invention is to provide a blur processing circuit that can change the size of a mask for blur processing.

[Means for solving the problem]

According to the first aspect of the present invention, (a) m rows and n columns of data to be subjected to the blur processing are stored, and one column of m shot-out data sequentially output by the shift operation is re-input as shift-in data. And a first shift for outputting horizontal information indicating the position of the shift-out data to be output at that time in the p-th column when the n-th column is divided into n smaller columns. Registers,
(B) Numerical conversion of shift-out data sequentially output in parallel from the first shift register group using horizontal information and parameters given in advance corresponding to each row, and numerical values for obtaining the sum thereof Conversion means;
(C) an adder for accumulating the data sequentially converted by the numerical conversion means by the number of times equal to p; and (d) an output of the adder which is obtained by dividing n by p as data after the blur processing. The second shift register group sequentially stored is provided in the blur processing circuit.

According to the first aspect of the present invention, the data output by the shift operation of the first shift register group is numerically converted by the numerical value conversion means and added by the adder, thereby using the CPU. The blur processing can be performed without any problem.

According to the second aspect of the present invention, (a) m rows and n columns of data to be subjected to the blur processing are stored, and one column of m shotout data sequentially output by the shift operation is re-input as shift-in data. And a first shift register for outputting horizontal information indicating the position of the shift-out data to be output at that time in the p-th column when the n-th column is divided into p columns each smaller than this. Group and (b)
The shift-out data sequentially output in parallel from the first shift register group is numerically converted individually using the horizontal information and the address information corresponding to each row and a predetermined parameter, and the numerical value obtained by calculating the sum is obtained. A read-only memory for outputting data, (c) parameter selection means for selecting parameters for reading by the read-only memory, and (d) a read-only memory.
An adder for accumulating the data sequentially read out from the only memory by the number of times equal to p; and (e) a second means for storing the output of the adder as data after the blurring processing by dividing n by p in order. And a shift register group are provided in the blur processing circuit.

According to the second aspect of the present invention, a read-only memory is prepared for numerical value conversion, and some parameters for numerical value conversion are prepared. To make things possible.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to examples.

FIG. 1 shows a configuration of a blur processing circuit according to an embodiment of the present invention. This blur processing circuit includes a shift register unit 11, a ROM (read only memory) 12 for inputting an output of the shift register unit 11 as address information and performing numerical conversion, and an adding unit for adding data after the numerical conversion. 13 and a register unit 14 for storing the addition data of the addition unit 13.

The shift register unit 11 includes a shift register 16 having m rows and n columns and m = 5 and n = 20, and a shift control unit 17 for shifting the shift register. The shift register 16 stores an image pattern of 5 rows × 20 columns to be processed. The shift control unit 17 supplies the shift register 16 with a shift direction signal 18 and a shift number signal.
19 is supplied, and an instruction as to whether the shift direction is left or right in the figure and the number of shifts are controlled. By forming the shift register 16 into a gate array, a large number of ICs (integrated circuits) conventionally used can be reduced to a small number of components.

On the other hand, the ROM 12 inputs the mode information 20 from the outside,
5-bit shift-out data from shift register section 11
21 and the horizontal direction information 22 of 5 × 5 max are input, and numerical conversion data 23 is output using these as address information. The ROM 12 stores the calculation results obtained by calculating each pixel with the weight corresponding to each position of the 5 × 5 mask. One of them is selected. The adder 13 includes an adder 25 that inputs the numerical conversion data 23 read from the ROM 12 as one of the input data, and a register that registers the added value 26.
Consists of 27. Data 28 output from register 27
Is supplied to the register section 14 and becomes the other input of the adder 25.

The register unit 14 includes four registers 31 arranged in series.
To 34, and constitutes a shift register as a whole. The stored data 36 output from the register unit 14 is data subjected to the blurring processing. The stored data 36 is connected to a data bus of a CPU (Central Processing Unit), not shown, and can be read by firmware.

FIG. 2 is for explaining the operation of the blur processing circuit having such a configuration. Times T ₀ , T ₁ ,..., T ₂₅ ,... Shown in FIG. It represents. This time axis T starts from T _0. In the next time T _1, the reset signal 43, 44 (FIG. 2 k, n) is issued. These reset signals 43, 44
Is output from the shift control unit 17 of the shift register unit 11. The reset signal 43 is supplied to the reset terminal R of the register 27 constituted by a flip-flop circuit,
Initialize this. Also, the reset signal 44 is
14 to initialize the four registers 31 to 34, respectively.

When the shift register 16 of the shift register section 11 shifts to the left or right, the shift-out data 51 to 55 output in parallel one bit at a time are taken in as shift-in data on the side opposite to the output side. It is supposed to be. That is, when the shift register 16 shifts 20 times in the same direction, the stored pattern is restored to the original pattern. However, in this embodiment, it is assumed that the shift direction of the shift register 16 is fixed only in the left direction in the figure by the firmware.

At times T _{2 to} T ₆ shown in FIG. 2A, the shift number signal 19 is generated once each as shown in FIG. 2C. A _{1 to} a ₂₀ , b ₁ to b as shown in the shift register 16.
_20, if c ₁ to c _20, d ₁ to d _20, data of e ₁ to e ₂₀ are to have been stored, first shift-out data in a time T ₂ 51 to 55 (Fig. 2 E to I) is ( a ₁ , b ₁ , c ₁ , d ₁ , e ₁ ). The data (a ₁ , b ₁ , c ₁ , d ₁ , e ₁ ) becomes the address information of the ROM 12 together with the lateral information 22 (FIG. 2d) of the 5 × 5 mask. The ROM 12 outputs, as data corresponding to the address, a value obtained by performing the operation shown in the above equation (1) on the data (a ₁ , b ₁ , c ₁ , d ₁ , e ₁ ). The 5-bit numerical conversion data 23 is output as data a ₁ '(FIG. 2j).

Similarly, at times T _{3 to} T ₆ , the sequential shift-out data 51 to 55 sequentially include data (a ₂ , b ₂ , c ₂ , d ₂ , e ₂ ), (a ₃ , b
_{3, c 3, d 3,} e 3), (a 4, b 4, c 4, d 4, e 4) and _{(a 5, b 5, c} 5, d
₅ , e ₅ ) and supplied to the ROM 12. And R
Numeric conversion data in these time T ₃ through T ₆ from OM12
23, data a ₂ ′,..., A ₅ ′ are sequentially output. These are based on the calculation result of the expression shown in the above expression (2).

Numeric conversion data 23 in the time T ₂ through T ₆ output from ROM12 are input to the adder 25 in the addition section 13, a register
It is added to the data 28 output by 27. Addition value by this
26 is sequentially stored in the register 27 by a storage clock 57 (FIG. 2L) output from the shift control unit 17 and supplied to the clock input terminal of the register 27. Register 27
The data 28 output from the
_11, f _12, f _13, and represent as f _14, f _15. Then, the data f ₁₁ in the time T _2, the data a ₁ '. Data f ₁₂ at the next time T ₃ is obtained by adding the data a ₂ 'to the data f _11. Similarly, the data
f ₁₃ is' is obtained by adding the data f ₁₄ is data a ₄ to the data f ₁₃ 'data a ₃ to data f ₁₂ is obtained by adding the data f ₁₅ is the data a _5' to the data f ₁₄ It is the sum.

In the embodiment, the size of the mask is set to 5 rows × 5 columns. Therefore, the final in the time T ₇ the shift is performed five times from the shift control unit 17 data storage clock 58 (second
When FIG. O) is output, the first register 31 of the four registers 31 to 34 which use this as a clock input stores data 28
The stored first as a mask blurring processing result value g ₁ (second
Figure p).

At the same time, the register 27 is initialized by a reset signal 43 in the time T _7. And more than time T ₂
First mask blurring process similar conducted in through T ₆ is also performed in the time T ₈ through T _12. When the final data storage clock 58 to the time T ₁₃ is output again, the data f ₂₅ is stored in the second register 31 as a mask blurring processing result g _2. At this time, it was stored in the register 31. First mask blurring processing result value g ₁ is Shiuto the next register 32 (FIG. 2 q).

In the same manner, the third mask blurring at the time T ₁₃ through T ₁₈ is performed, the fourth mask blurring process is performed in the time T ₁₉ through T _24. Then, as the data f ₃₅ is the third mask blurring processing result g _3, and as the data f ₄₅ is fourth mask blurring processing result g _4, will be respectively input to the register unit 14. Thus the register 34 first mask blurring processing result value g ₁ (second drawing s) in the register
33 time second mask blurring processing result g ₂ (second FIG r), the third mask blurring processing result value g ₃ in register 32, which further fourth Masukubogashi processing result value g ₄ in register 31 are stored respectively to T _25, to end all processing of the blurring processing circuit.

So the shift control unit 17 issues a termination interrupt signal 61 at this time T ₂₅ (FIG. 2 t), and notifies the completion of the blurring process with respect to a CPU (not shown). When the CPU receives this end interrupt signal 61, the four registers 31 in the register section 14
34 are read, and the result of the blur processing is taken.

Thus, in the blur processing circuit of the embodiment, a _{1 to} a ₂₀ , b
100 data of _{1 to} b ₂₀ , c _{1 to} c ₂₀ , d _{1 to} d ₂₀ , and e _{1 to} e ₂₀ are blurred to four data of g ₁ to g ₄ using a 5 × 5 mask. And the start signal 41 is transmitted to the shift control unit 17.
By setting to, processing can be performed irrespective of the CPU.

In the embodiment described above, the output period of the reset signal 43 is fixed, but by changing this, the size of the mask in the shift direction can be changed. Also, by changing the number of bits constituting the shift-out data 21 and performing the corresponding operation in the ROM 12,
The size of the mask in a direction orthogonal to the shift direction can be changed.

In this embodiment, since the parallel data output from one of the shift registers 16 is input from the other, the same image data can be processed with different masks.

〔The invention's effect〕

As described above, according to the first aspect of the present invention, the data of m rows and n columns having a matrix size smaller than the data to be subjected to the m-row and n-column blur processing set in the first shift register group is stored. , And sequentially add the same to the number equal to p to obtain the sum of m rows and p columns. The sum is sequentially set in each shift register of the second shift register group, and after the blur processing, I decided to store it as data. Therefore, not only is the image processing speeded up without imposing a burden on the CPU, but also the circuit configuration after the numerical value conversion means can be downsized even if the size of the data to be blurred is large.

According to the second aspect of the present invention, data of m rows and p columns having a matrix size smaller than that of m rows and n columns of data to be subjected to the blur processing set in the first shift register group is read. Since the numerical conversion is performed using the only memory, the read only memory can be downsized even if the size of the data to be blurred is large. Further, since a read-only memory is used, individual arithmetic processing is not required, and the speed of the blur processing is increased. Furthermore, since parameters for numerical conversion can be selected, it is possible to perform blur processing suitable for various types of processing.

[Brief description of the drawings]

1 and 2 are diagrams for explaining an embodiment of the present invention. FIG. 1 is a schematic diagram showing the configuration of a blur processing circuit, and FIG. 2 shows the operation of this circuit. FIG. 3 is an explanatory diagram showing the relationship between image information and a mask, FIG. 4 is an explanatory diagram showing the arrangement of each pixel in image information, and FIG. 5 is an explanatory diagram showing weights corresponding to these pixels. FIG. 11 shift register section, 12 ROM, 13 adder section, 14 register section, 16 shift register, 17 shift control section, 20 mode information, 21 shift-out data, 25: Adder, 27: Register, 31 to 34: Register, 71: Mask.

Claims (2)

(57) [Claims] 1. An apparatus for storing m rows and n columns of data to be subjected to blur processing and outputting m data for one column sequentially output by a shift operation.
Number of shout-out data are re-input as shift-in data, and the number of the shift-out data output at that time in the p-th column when the n-th column is divided into p columns each smaller than this A first shift register group that outputs horizontal information indicating the following, and the shift-out data sequentially output in parallel from the first shift register group is given in advance in correspondence with the horizontal information and a row thereof. Numerical conversion means for performing numerical conversion using the obtained parameters to obtain the sum of these, an adder for sequentially adding the data which has been numerically converted by the numerical conversion means by the number of times equal to p, and an output of the adder And a second shift register group for sequentially storing the n as the data after the blur processing by the number obtained by dividing the n by the p. Processing circuit. 2. The m-row data for one column which is stored in m rows and n columns and is sequentially output by a shift operation.
Number of shift-out data are re-input as shift-in data, and the number of the shift-out data output at that time in the p-th column when the n-th column is divided into p columns each smaller than this A first shift register group for outputting horizontal information indicating the following, and the shift-out data sequentially output in parallel from the first shift register group correspond to the horizontal information and respective rows and predetermined parameters. A read-only memory for outputting numerical data obtained by individually converting the numbers into numerical values using the address information, a parameter selecting means for selecting parameters for reading by the read-only memory, An adder for sequentially adding data sequentially read from the read-only memory by the number of times equal to p, A second shift register group for sequentially storing the output of the arithmetic unit as the data after the blur processing by the number obtained by dividing the n by the p.