JP2586388B2 - Exchange system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exchange used for a telephone communication network or the like, and more particularly to a switching system which is suitable for high-speed and wide-band communication and which takes scale expandability into account. The present invention relates to a configuration of a shape exchange system. 2. Description of the Related Art Switching systems are moving toward higher speeds, wider bandwidths, and higher reliability. As a specific measure against this, it is conceivable to decentralize the communication path system, particularly the line concentrator stage. That is, the processing capacity can be improved by the load distribution effect, the capacity of the entire exchange can be increased, and the building block characteristics can be ensured (optimal configuration can be obtained according to the station scale). It is a plan. [0003] The role of the conventional exchange was to exchange low-speed telephone voice in most cases, but it is expected that demand for high-speed data communication including images and so-called multimedia communication will increase in the future. For this reason, the switching equipment is required to dramatically improve the call processing capacity, but the processing capacity of the processor has a certain limit. As a measure for improving the processing capacity, there is a function distribution and a load distribution by using a multiprocessor, but the software is complicated and communication between the processors becomes a bottleneck. [0004] Further, from the viewpoint of expansion and risk distribution, it is desirable that the exchange is modularized for each functional unit, and it is desirable that the switches be physically distributed. In that case, the processors themselves are distributed. Unless an independent distributed configuration is adopted, the load on the central processor does not change, but rather the number of control lines for controlling each module increases. On the other hand, as described above, although demand for high-speed data communication and multimedia communication is increasing, there is a regional and time bias, and an economical exchange system having only a high processing capacity and a large capacity is not enough. Network cannot be configured. Therefore, the architecture can be used for the future, and the scale can be flexibly configured from a small capacity to a large capacity. In other words, the above-described building block property becomes important. FIG. 2 shows a basic configuration of a conventional exchange. Communication path system and control system 20 including a concentrator stage 201 having a subscriber interface and a distribution stage 202 for switching.
3. It is composed of a maintenance operation system 205 and a signal processing system 204 (see "3.1 Basic Configuration of Switch" on page 17 of "Digital Switching System" published by the Institute of Electronics, Information and Communication Engineers). In order to achieve decentralization in this configuration, it is conceivable to make the concentrator 201 a distributed module (distributed concentrators 301 and 302) as shown in FIG. The burden on the system does not change. It is physically dispersed, so it is dangerous dispersion in the event of a disaster.For example, if a certain concentrator module fails, the entire system is centrally managed by the control system. For example, it is necessary to perform disconnection processing of the failed module.
Overhead occurs in the central management unit, which affects the entire system. [0008] As described above, in a distributed switching system of a type in which the communication path system is distributed and the control system is concentrated in one place, the processing capacity of the control system is limited. Therefore, the benefits of load balancing cannot be fully utilized. That is, it is desirable that the future switching system has an independent decentralized configuration including the control system. However, when each module is independent, when trying to communicate from one module to another module, the transmitting-side module determines whether the transmission path to the partner module is free or further exits from the partner module. You have to know if some lines are free. That is, resource management is required. Even in a normal distributed system, resource management is often performed in a concentrated manner. However, if resource management is performed in a single location, all modules will inquire to this centralized management unit. In the case of a system, this is a processing bottleneck. On the other hand, if each module is completely independent, one module will always know the status of all other modules or check the status of the other module each time a call is set up. There must be. In the former, it is necessary to notify all other modules when the status changes in one module, or to check the status periodically, and it is not enough When only one line is left in a certain module, there is a possibility that a plurality of other modules may simultaneously make a communication request there. In the latter case, such a problem does not occur, but anyway, communication between all modules is necessary. For this purpose, for example, it is conceivable to put a communication line between each module in a mesh shape,
This is not economical, both physically and in terms of having to manage communications further. It is an object of the present invention to construct a more economical, high-throughput distributed switching system. More specifically, the present invention is a distributed switching system having a transmission line such as a bus or a device (central switching module) commonly accessed by peripheral switching modules. To avoid becoming a neck,
An object of the present invention is to construct a distributed switching system in which each peripheral switching module can independently process a call. In order to achieve the above-mentioned object, a plurality of peripheral switching modules 402 having an interface circuit for transmitting / receiving a signal to / from a subscriber line or a trunk line as shown in FIG. A distributed switching system comprising 403, 404, and 405 and one or a plurality of central switching modules 401 connected to each of the plurality of peripheral switching modules via a transmission line is configured. The peripheral switching module has a function of determining a destination route of a signal input from a subscriber line or a trunk line, and a block of information (a signal (header including a signal and a destination peripheral switching module number) on a transmission line). Packet, block, cell, etc.) to the transmission line, a state management function for always storing the idle / busy state of the subscriber line or the trunk line, and the subscriber line when requested. Alternatively, it has a function of determining whether the trunk line is occupied or not and a function of transmitting and receiving the determination result between the plurality of peripheral switching modules. The central switching module connects the peripheral switching modules to each other, and may be a simple bus-type transmission line, a loop-type transmission line, or a switch. In the case of a switch, the following measures are required to avoid the above-mentioned packet collision. That is, a plurality of time switches and a space switch that connects the time switches, and the idle / busy management of a link (a management unit that applies to each call when connecting the switches) corresponding to the input highway of the space switch, Performed on a frame-by-frame basis (signals on the transmission path divided for convenience)
Referring to the first state management memory, the second state management memory, and the first and second state management memories, which perform link idle / busy management for each frame corresponding to the egress highway of the space switch. The circuit has a circuit for generating a write or read address for each of the plurality of time switches so that a plurality of time slots having destinations are not switched at the same time. With the above configuration, the following call setting is performed. [0015] When a call request is issued from a subscriber to a certain peripheral exchange module, the peripheral exchange module analyzes the dialed digits and finds a destination route. Next, an arbitrary peripheral exchange module belonging to the destination route is selected, and a call signal is sent. This call signal includes, as a header, the destination of the number of the selected peripheral switching module, and wrote the call number, the selected number, the signal speed, and the used time slot number as a signal.
This is one packet put on a time slot on the transmission path. A time slot is a subdivided frame, and is a basic unit of division and multiplexing in the time division multiplexing technology. This time slot is transmitted to the central exchange module via the transmission line. When the central exchange module is a transmission line, since this transmission line multiplexes packets from each peripheral exchange module and connects each peripheral exchange module, each peripheral exchange module reads the header of each packet and reads its own packet. If there is something addressed to, take it in. On the other hand, if the central exchange module is a switch, the central exchange module reads the header and switches this packet to the transmission line connected to the destination peripheral exchange module. When the peripheral switching module designated as the destination receives the time slot carrying this packet, it determines whether the subscriber line or the trunk line is occupied, and then sends a response signal back to the originating peripheral switching module. This response signal is also a packet having substantially the same configuration as the call signal. The number of time slots for carrying packets will be described later in detail. However, as long as the line is free, the time slot is set so that there is an empty time slot. Therefore, a response signal always returns if the line is free. Conversely, if no response signal is returned after a certain period of time, it is determined that the line could not be captured, and a call signal is sent again to another peripheral switching module belonging to the same route. When the response signal is returned, the call setup is completed at that time. Thereafter, every frame, a signal is transmitted using the same time slot which has been notified to the destination peripheral switching module by a call signal. At this time, the central switching module only reads the destination of the header and performs switching, and does not involve a processor. As described above, the central switching module, which is a common unit, can perform call setting only by the peripheral switching modules without performing any processing other than packet distribution. Also in the subsequent call state, the central switching module performs autonomous switching based on the header of each time slot. An embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows a communication path system of the switching system according to the present invention, and a central switching module (CM: Central Modul).
e) A peripheral switching module (FM: Front-end Module) with a center on 101 and transmission lines 111, 112, etc.
le) 102 to 109 are connected. In the figure, SM
Peripheral switching modules 102 to 105 marked (Subscriber Module) have a subscriber line interface, and peripheral switching modules 106 to 109 marked TM (Trunk Module) have a trunk line interface. For example, a signal arriving from the subscriber line 110 is added with a destination address by the peripheral switching module 102, passes through the inter-module transmission line 111, and passes through the central switching module 10
Sent to 1. The central switching module 101 refers to the address written in the header and, for example, if the destination is the peripheral switching module 108, the inter-module transmission path 1
Switching to 12. In the peripheral switching module 108, the header is removed, and the signal is transmitted to the trunk line 113. The same applies to communication from the trunk line side to the subscriber line side. Since normal communication takes place in both directions, the peripheral switching module (SM) of the subscriber line interface
For example, 102 and 104 and 103 and 105 are distributed and installed in a pair. The peripheral exchange module (TM) of the trunk interface does not need to be installed in a distributed manner, and therefore is placed close to the central exchange module. The number of peripheral switching modules and the ratio between SM and TM can be freely determined according to the local state. Of course T
If only M is installed, it functions as a transit exchange. Next, further details will be described with reference to FIG. The peripheral switching module 102 includes a time switch 501, a link interface 502, a control system 503, and a state management memory 500. From the subscriber line, a time-division multiplexed signal from the subscriber is input via a concentrator (not shown). The time switch 501 rearranges the time-division multiplexed signal for each destination module in accordance with an instruction from the control system 503. The link interface 502 adds a header such as a destination address to this, puts it in a time slot together with a signal going to the same destination, and sends it out to the central switching module 101. The central switching module 101 includes link interfaces 504 and 514, time switches 505 and 51
It comprises a 5-channel match logic 511, a space switch 506, and time switches 507 and 517. The header of the time slot received from the peripheral switching module 102 is read by the link interface 504. The channel match logic 511 determines the read address or write address of each time switch 505, 515 from the header information of each time slot arriving from each peripheral switching module so that a plurality of time slots having the same destination do not exist at the same time. Generate address. This operation can be performed only by wired logic. The time switches 505 and 515 switch the time slots based on the address generated by the channel match logic. In order to change the time slots in one frame so that they do not completely collide, that is, to make the time slots non-block, The outgoing link is operated at twice the speed of the incoming link. The spatial switch 506 switches each time slot according to the destination address written in its header and sends out the time slot to the time switches 507 and 517 connected to the destination peripheral switching module. The time switches 507 and 517 return the operation speed to the original speed and transmit the time slot to the transmission line connected to the peripheral switching module. The peripheral switching module 104 includes a link interface 509, a time switch 510, and a control system 50.
8. It comprises a state management memory 518. The header of the time slot arriving from the central switching module 101 is removed by the link interface 509, the signal is written to the time switch 510 by the address indicated by the control system 508 based on the information in the header, and the signal is time-divided again. It is multiplexed and transmitted to the trunk line. Having described the signal flow with reference to FIG. 5, the operation at the time of call setting will now be described. As shown in FIG.
Upon detecting a call, a subscriber line side peripheral exchange module (hereinafter abbreviated as SM) performs route analysis. Therefore, each SM must have all necessary data by itself. When the destination route is determined, generally, there are a plurality of trunk line side peripheral exchange modules (hereinafter abbreviated as TM) for each route, and any one of them is selected. Although various selection algorithms are conceivable, since the peripheral switching modules on the transmitting side do not communicate with each other, it is desirable to use an algorithm in which each peripheral switching module on the transmitting side preferably selects a different peripheral switching module on the receiving side. For example, if there is a lot of communication from a specific SM to a specific route, the SM always selects a specific TM, and other SMs do not select the TM. After selecting the TM, a call signal is sent to the TM. This may be transmitted using another signal line, but in this embodiment, a time slot of a communication path is used. In the information part of the calling signal, a call number, a selected number, a signal speed, and a used time slot number are written. T
M will then receive. In which time slot (if a plurality of calls are included in one time slot), it is possible to recognize whether or not the information of what bit and in what order is the call. (A method of placing a plurality of calls heading for the same route in one time slot in order to reduce the overhead of the header is common as a type of group switching.) The TM that has received the call signal is shown in FIG. The control system 508 refers to the state management memory 518 to determine the idle / busy state of the line accommodated therein, and if there is a vacancy, captures one of the lines and sends it to the line state management memory 518.
Rewrite and return response signal. The response signal is the reception T
M is sent from the transmission TM paired with M, and the transmission S
It is received by the SM paired with M. The response signal includes
Write the call number and the used time slot number. When the response signal is received by the SM, the call setup is completed.
According to this method, the peripheral switching module manages the state of the line accommodated therein, determines the occupied state of the line, and notifies it only. Time slots to be used can be secured. FIG. 6 shows a frame configuration of an inter-module transmission line. Here, 125 μs is defined as one frame, and the frame is divided into m time slots. Each time slot includes a header 601 and an information section 602. FIG. 7 shows the structure of the time slot in more detail. The header 601 is divided into five areas. The contents are an empty / busy display 701, an exchange information / call control information indicator 702, a destination address 703, a transmission address 704, and a call number 705. Next, the number of time slots and the length of the information section will be described. As a prerequisite, it is assumed that there are n peripheral switching modules accommodating a maximum of c lines, a header in a time slot is h bytes, and an information part is i bytes. The number t of time slots in one frame is set to satisfy the following condition. In other words, only the information for one line of voice (that is, 1 byte) is transmitted to (n-1) destinations other than a certain destination peripheral switching module. ｛C- (n-
1) Even if all the circuit information is sent to one destination peripheral switching module in a concentrated manner, the time slots must not be insufficient. This means that t ≧ (n−1) + {c− (n−1)} / i must be satisfied. On the other hand, the overhead o due to the header can be expressed as follows. ## EQU2 ## o = t） (h + i) / c As the number of time slots t increases, the overhead increases. Therefore, the optimum values of t and i are obtained from the above equations 1 and 2. When the number of time slots is determined in this manner, a time slot for communication with a certain peripheral switching module can be secured as long as a line is free, and resource management in the peripheral switching module can be ensured. This can be done only when the line is idle. Next, the channel match logic in the switching unit described above will be described in more detail. FIG. 9 shows a block diagram of the channel match logic unit. Link interfaces 504 to 514 and time switches 505 to 515
The space switch 506 is the same as that described with reference to FIG. The channel match logic 511 includes an address multiplexer 901, a primary link management memory 902, a secondary link management memory 903, and an address calculation unit 904. Here, the “primary link” is an incoming link of the space switch 506, and the “secondary link” is an outgoing link of the space switch 506. Link interface 504-514
The header is read out by the address multiplexer 901 and multiplexed by the address multiplexer 901. Outgoing address (SA) is 1 in the contents of the header.
The read address of the next link management memory 902 is used, and the destination address (DA) is the read address of the secondary link management memory 903. The primary link management memory 902 has the occupied state of each time slot of the primary link corresponding to the peripheral exchange module, and the secondary link management memory 903 has the occupied state of each time slot of the secondary link corresponding to the peripheral exchange module. Is written. The operation speed of the space switch is doubled in order to form a non-block communication path. Therefore, the number of time slots is twice the number of time slots input in one frame cycle. Looking at a certain point in the frame, it is possible to know which time slots are vacant for each of the primary link and the secondary link in the frame. This will be described more specifically with reference to FIG. The figure shows that a time slot addressed from the i-th peripheral switching module on the incoming side to the j-th peripheral switching module on the outgoing side has arrived. (In the figure, 1 is closed, 0 is empty)
The contents of the primary link management memory and the secondary link management memory are read with the transmission address #i and the destination address #j, respectively. An OR of the two is obtained to find a common empty space, and the empty space near the top of the frame is set as the address where this time slot is to be written in the time switch. The used position is rewritten from "0" to "1", and is fed back to the primary link management memory and the secondary link management memory. The time slot arriving in this way is randomly written in each time switch based on the write address, and the primary link management memory and the secondary link management memory are rewritten, thereby processing one frame. When the space switch 506 is transmitted to the space switch 506 by the sequential read after the
In switching at 06, no time slot collision occurs. In the above description, the time switch has a so-called double buffer configuration, which has a write surface and a read surface and uses them alternately. In addition, although the description has been given of the random write and the sequential read, the same function can be obtained by the sequential write and the random read. The space switch 506 only needs to be capable of autonomously switching according to the destination address of the header of each time slot, and various configurations are possible. FIG.
An example is shown in FIG. Here, the selector 11 corresponds to each destination.
11-1113, the switching address generation circuit 1121
1 to 1123, a switching address is generated based on the header information and switching is performed. Retiming circuits 1101 to 11
21 are provided. As can be seen from the above description, all the central switching modules can be constructed with wired logic and are passive modules that do not require a control processor. FIG. 12 shows an example of the system configuration. This configuration example achieves load distribution and risk distribution by using a plurality of central switching modules. Such decentralization is easy because the central switching module is a passive module. Since it is configured so that it can reach the same peripheral switching module via either central switching module, there is no problem even if one fails, as long as the other does not become overloaded. According to the present invention, each peripheral switching module only needs to manage its own line and does not require centralized resource management. High processing capacity can be obtained as a whole system.
Also, each peripheral exchange module has its own processor,
It is an independent distributed module that can perform all call processing.On the other hand, the central switching module, which is a common part, has no call processing processor, is simply a transmission line, or is composed of all wired logic, so processing of the processor is The capacity does not become a bottleneck, and a high processing capacity can be obtained as a whole switching system. Further, since expansion and expansion can be performed without concern for the processing capacity of the central switching module, which is a common part, by changing the number of peripheral switching modules, a flexible configuration from a small-scale configuration to a large-scale configuration can be realized. Configuration is possible. Furthermore, since the central switching module having the switching function has neither a processor nor a switch holding memory, an intermittent failure does not affect the time later, and one peripheral switching module fails. However, it is possible to construct a highly reliable distributed switching system that hardly affects the central switching module. In summary, according to the present invention, load distribution,
By risk diversification, processing capacity is high and reliable,
The construction of a distributed switching system is possible.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration example of a distributed switching system according to the present invention. FIG. 2 is a block diagram showing a conventional example. FIG. 3 is a block diagram showing a conventional example. FIG. 4 is a block diagram showing a basic configuration of the present invention. FIG. 5 is a block diagram showing an embodiment of the present invention. FIG. 6 is an explanatory diagram of a frame configuration according to the embodiment of the present invention. FIG. 7 is an explanatory diagram of a time slot configuration according to the embodiment of the present invention. FIG. 8 is an explanatory diagram of a call control sequence of the present invention. FIG. 9 is a block diagram of an embodiment detailing part of FIG. 5; FIG. 10 is an operation explanatory diagram of FIG. 9; FIG. 11 is a block diagram of an embodiment showing a part of FIG. 5 in detail. FIG. 12 is a block diagram illustrating an example of a system configuration. [Description of Signs] 101: Central switching module, 102 to 109: Peripheral switching module, 500: State management memory, 501: Time switch, 502, 504: Link interface, 503: Control circuit, 505, 507: Time switch, 506 ... space switch, 511 ... channel match logic, 901 ... address multiplexer, 902 ... primary link management memory, 903 ... secondary link management memory, 904 ... address calculation unit.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Takao Kato               216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa               Hitachi, Ltd. Totsuka Plant (72) Inventor Hiroshi Kuwahara               1-280 Higashi Koigabo, Kokubunji-shi, Tokyo               Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-61-196643 (JP, A)                 JP-A-60-253396 (JP, A)                 U.S. Pat. No. 3,418,462 (US, A)                 Yoshito Sakurai, Shinobu Gobara, Kenichi Otsuki: "Next generation               A Consideration on the Exchange System "               Law SE86-68                 Takao Takeuchi, Hiroyuki Okazaki, Takehiko Yamaguchi: "S               YNCRONOS COMPOSIT               E PACKET SWITCHING               Exchange System Configuration Method by 1984 "               Proceedings of the IEICE General Conference 1939, min               Book 8-PP. 169                 Takehiko Yamaguchi, Takao Takeuchi: "Line / Packet               One method of integrated exchange "               Proceedings of the IEICE General Conference 1938, min               Book 8-PP. 168                 Takao Takeuchi, Takehiko Yamaguchi: "Line / Packet               A method of integrated exchange "               148                 Takao Takeuchi, Takehiko Yamaguchi: "Line / Packet               G. A Method of Integrated Exchange (Part 2)               Law SE84-39                 Hiroshi Suzuki, Shinichiro Hayano, Hiroki Niwa, Takeuchi               Takao "Study on SCPPS Switching System Configuration"               Academic Technique SE85-9                 TAKAO TAKEUCHI, TA               KEHIKO YAMAGUCHI: "               A NEW SWITCHING AR               CHITECHTURE FOR IS               DN ENVIRONMENT ”, PR               OC. ICC, MAY 1984, PP. 38               −41                 HIROKI NIWA, HIROS               HI SUZUKI, SHIN-ICH               IRO HAYANO, TAKAOT               AKEUCHI, TAKEHIKO Y               MAGUCHI: "STNCRONO               US COMPOSITE PACKE               T SWITCHING FOR BR               OADBAND ISDN ”, PRO               C. ICC, JUNE 1986, PP.               1715-1719                 HIROSHI SUZUKI, TA               KAO TAKEUCHI, TAKEH               IKO YAMAGUCHI, "VER               Y HIGH SPEED AND H               I

Claims (1)

(57) [Claims] Each is a call for information from a subscriber line or trunk line
The subscriber accommodated by the self-exchange means in the exchange means performing the processing
Means for judging and managing the idle / busy state of a line or a trunk line;
Information with a header containing information corresponding to the destination.
Conversion means for converting to fixed length packets and transmitting / receiving
A plurality of first switching means connected to the plurality of first switching means via transmission means;
The fixed length packet according to the contents of the header.
Self-exchanged between the first exchange means in units of
A plurality of second exchange means having a routing switch;
The fixed-length packet output by the transmitting-side first switching unit.
Is transmitted to the destination side via at least one second exchange means.
An exchange system, wherein the exchange system arrives at one of the exchange means .