JP2578057Y2 - Module address setting device - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a slot address detection circuit used in a building block type electronic device such as a sequencer, and more particularly to an improvement requiring a small number of buses.

[0002]

2. Description of the Related Art A power supply module, a CPU module, and an input / output module are sequentially mounted on a mother board in a building block type electronic device. It is used. In the nest structure, a control system is constructed by mounting a printed circuit board called a card on the nest, and the nest is housed in a separately provided large casing such as a cubicle. The nest structure is frequently used in a process control device of a chemical industry or the like, and is generally installed in an instrumentation room where dust is relatively small.

FIG. 2 is an explanatory view of a conventional building block type electronic device and a nest structure device. The backboard has slots 1 to 3 for mounting modules, and each slot is connected by a bus. The slot address signals SLOTA3 to SLOT0 are 4-bit terminals forming each slot, and are used by the CP connected to the module connected to each slot.
An address for accessing from the U module is given.

FIG. 3 shows a slot address signal SLOT3.
FIG. SLOTA3 to SLOT0 constitute each bit. In slot 0, all bits are L, and slot 1
Then, only SLOTA0 is H, and in slot 2, SLOTA1
Only H, and in Slot 3, SLOTA0 and SLOTA1 are H. The module mounted in each slot reads the slot address signals SLOTA3 to SLOT0 to know its own address.

[0005]

However, the operation of detecting the slot address of each module by each module is performed only at the time of initialization at the time of power-on, and the module performs a normal operation as a controller after storing the slot address. Yes, there is no need to physically detect the slot address. Also, when reducing the manufacturing cost of the motherboard, reducing the number of signal lines between the module and the motherboard is equivalent to reducing the number of mounting connector pins on the module side and the motherboard side, which contributes to cost reduction. At the same time, the mechanism design is facilitated and the reliability is improved. The present invention solves such a problem, and an object of the present invention is to provide a module address setting device capable of detecting a slot address while having a small number of signal lines between a module and a mother board.

[0006]

According to the present invention, there is provided a motherboard having a bus, and a module mounted in a slot provided in the motherboard.
An apparatus in which a slot address is set corresponding to each module has the following configuration.

That is, a circuit 11 connected to a part of signal lines of the bus and generating a slot address signal corresponding to each slot on the signal line is provided on the mother board side. A signal generation permission circuit 12 for permitting generation of an address signal is connected to a signal generation permission circuit between adjacent slots. In the slot address reading mode, a single signal generation permission circuit is effective among all signal generation permission circuits. And a slot address control line 13 to be set in a state.

Each module has a read permission circuit 21 for recognizing whether a signal generation permission circuit of a slot connected to the own device is in an effective state. A circuit 2 for reading the slot address of the own device from the signal line that also serves as the slot address
2, and a next station notifying circuit 23 for transmitting a slot address read command through a slot address control line connected to an adjacent slot after reading of the slot address of the own device is completed. When the reading mode of the slot address is released, the signal line of the bus which is also used for the slot address is used for communication of the original signal.

[0009]

In the present invention, the slot address control lines connect the slots in a daisy chain system.
A bus right is sequentially given to a signal generation permission circuit provided for each slot. In the signal generation permission circuit to which the bus right has been given, the slot address generation circuit is operated to cause the slot address of the own device to appear on the signal line of the bus which is also used as the slot address signal line. On the module side, the state of the signal generation permission circuit of the connected slot is read by the read permission circuit. If the state is valid, the slot address of the own station is read from the slot address signal line by the slot address read circuit. The notification circuit makes the adjacent slot inherit the bus right.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG.
FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a reset signal line, a fail signal line, a bus right arbitration signal (arbitration),
An interrupt signal, an address bus, a data bus, an access control signal, and the like are used, and constitute a so-called multi-master system. In the figure, the data bus D0 is used as a bus.
Only D7 are shown, and other signal lines are omitted. Here, when no module is a bus master, or when a certain module is a bus master but is not driving an address bus or a data bus, the address bus or the data bus is in a high impedance state, Here, it is held at the logic level H by the action of the pull-up resistor.

A slot address generating circuit 11 is provided for each slot of the mother board 10, and D0 to D3 of the data bus are also used as slot address signal lines. A switching transistor is connected to each slot address signal line according to the slot address. When this transistor is turned on, the slot address signal line D
Since the signal lines corresponding to 0 to D3 become L, the slot address is revealed by observing all the slot address signal lines. The signal generation permitting circuit 12 permits the slot address generating circuit 11 to generate a slot address signal and notifies the module 20 of the own device that the slot address has appeared on the slot address signal line. Here, the signal generation permission circuit 12 is an exclusive OR gate EOR, and the bus right has been granted to the own station by the logical state of the slot address control lines ₁₃₁ , ₂ , ₃ connected before and after the own station. And the slot address generation circuit 11 is operated. The slot address control line 13 is of a daisy chain type in which the signal generation permission circuit 12 is connected between adjacent slots. In the slot address read mode, all the signal generation permission circuits 12 are connected to only a single signal generation permission circuit 12. Give the bus right to make it valid. The reading mode of the slot address is
For example, a command is issued from a master station such as a CPU module (not shown) to each slave station, and is performed only for a limited time such as when power is turned on.

Each module 20 is mounted in a slot, and here corresponds to an I / O module serving as a slave station. The read permission circuit 21 recognizes whether the signal generation permission circuit 12 of the slot connected to the own device is valid, and may input the signal of the slot address control line 13 on the station immediately before the daisy chain. The slot address read circuit 22 reads the slot address from the slot address signal lines D0 to D3 when the read permission circuit 21 recognizes that the read permission circuit 21 is in a valid state. Used to identify own station in communication with. After the processing of the slot address reading circuit 22 is completed, the next station notifying circuit 23 activates the signal generation permission circuit 12 in the next slot, so that the slot address control line 13 communicating between the own slot and the next slot is used. And the signal generation permission circuit 12 in the slot of the own device is invalidated when the signal generation permission circuit 12 is not in the invalid state.

The operation of the apparatus having the above-described configuration will be described. When the system is turned on for the first time,
0 is negated to release the reset state, and the slot address control line 13 of slot 0 (not shown) is asserted (asserted) from the motherboard side.
t) Then, the mode becomes the read mode of the slot address.

In each module 20, when the slot address control line 13 of the immediately preceding station is asserted, the slot address reading circuit 22 waits for permission of the read permission circuit 21.
Reads the slot address from the slot address signal lines D0 to D3. At this time, the signal generation permission circuit 12 sets the slot address control line 13 of the immediately preceding station to “H”.
Then, only when the slot address control line 13 of the station immediately after is "L", the address of the slot appears on the slot address signal line. When the reading is completed, the next station notification circuit 23 asserts the slot address control line 13 connected to the next slot. Then, in the next slot, the same operation is performed to read the slot address of the own slot,
A bus right is inherited to an adjacent slot. When the reading of the slot address of the own device is completed in all the modules, the reading mode of the slot address ends, and the mode can be shifted to the normal control mode.

[0015]

As described above, according to the present invention, since a part of the bus is also used as a slot address signal line by the slot address generating circuit, a dedicated slot address terminal is not required, and the number of connector poles is reduced. And the production cost is reduced. Since the slot address control line 13 and the signal generation permitting circuit 12 are used to substantially adopt a daisy chain system, the addresses of the respective slots appear sequentially on the slot address signal lines, so that the modules can cooperate. Thus, the slot address of the own device can be read from the slot address signal line.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a conventional device.

FIG. 3 is an explanatory diagram of slot address signals SLOTA3 to SLOTA0.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 mother board 11 slot address generation circuit 12 signal generation permission circuit 13 slot address control line 20 module 21 read permission circuit 22 slot address read circuit 23 next station notification circuit

Claims (1)

(57) [Scope of request for utility model registration] 1. An apparatus having a motherboard (10) having a bus and modules (20) mounted in slots provided in the motherboard, wherein a slot address is set corresponding to each module. A circuit connected to a part of signal lines of the bus to generate a slot address signal corresponding to each slot on the signal line; and permitting the slot address generating circuit to generate the slot address signal. A signal generation permission circuit (12) and a signal generation permission circuit connected between adjacent slots, and a slot address for enabling a single signal generation permission circuit among all the signal generation permission circuits in the slot address read mode. A control line (13) and a read for recognizing whether the signal generation permission circuit of the slot connected to the own device provided in each module is in an effective state. A permission circuit (21), and a circuit (22) for reading the slot address of the own device from the signal line of the bus which is also used as the slot address when the read permission circuit recognizes the validity.
And a next station notifying circuit (23) for transmitting a slot address read command through a slot address control line connected to an adjacent slot after the reading of the slot address of the own device is completed. A module address setting device, wherein when released, a signal line of the bus, which also serves as a slot address, is used for initial signal communication.