JP2572244Y2 - Digital direct synthesizer - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital direct synthesizer, and more particularly, to a digital direct synthesizer applied to various devices such as a signal generator, a signal analyzer, and an impedance transfer characteristic measuring device.

[0002]

2. Description of the Related Art A conventional example of the present invention will be described with reference to FIG. The digital direct synthesizer shown in FIG. 1 comprises a phase accumulator 3, a data memory 4, a latch 5, a digital-to-analog converter 6, and a low-pass filter 7. In the phase accumulator 3, the increment data k and the repetition frequency f
s clock signal is added. The output pattern of the phase accumulator 3, which is the result of addition for each clock of the frequency fs, is used as an address of the data memory 4, and a waveform, for example, a sine wave stored in the memory 4 is read out. Digital / Analog /
After conversion into an analog signal in the converter 6, the signal is filtered by the low-pass filter 7 to obtain an output of the frequency fo.

[0003]

[Problem to be solved by the invention] Digital director
The input / output of the synthesizer will be described. Input and output ^{fo = (k / 2 n)} · fs (HZ) Equation _{1 T = m 1 / fs =} m 2 / fo (m 1, m 2 is an integer) is expressed as Equation 2. The derivation of fo and T is as follows
Done. f ₀ is the digital direct of this invention
-The output frequency of the synthesizer. k is the output frequency f
₀ is a numerical value arbitrarily set, and f ₀ is proportional to k.
The unit of k is (1 / hour). n is constructed in binary
The number of bits of the phase accumulator
Is a bit. Here, the phase accumulator
Possible values are integer values ranging from 0 to (2 ⁿ -1).
You. f _s ward to be supplied to the phase-accumulator
It is the lock frequency and the unit is (H _Z ). See FIG.
To Fay, T is, driven by the clock frequency f _s
Complete repetition at the output of the accumulator
Period. m ₁ is the output of the phase-accumulator
Of the clock f _s during the complete repetition cycle
It is a number and the unit is a cycle. m _2, Phase A
During the complete repetition period at the output of the
Digital direct synthesizer output frequency f0
Is the number of cycles. FIG. 7 shows m ₁ = 16 and m ₂ =
Output waveform of phase accumulator when 3
FIG. 3 is a diagram showing output signal waveforms. In this figure, a _{T = 16 / f s = 3} / fo. The complete repetition period T of the accumulator output is
m ₁ = 16 cycles of fs , and the synthesizer output
A complete repetition period T of m ₂ = 3 cycles worth of fo
is there. For reference, the behavior of the phase accumulator
For operation, for example, f _s = 1H _z , n = 3 bits, k
= 3, the output of the phase accumulator is
Time and phase accumulate as starting from 0
The output values of the data are shown below. At time = 3 seconds, the output value becomes 6 + 3 = 9.
Bafuro to a 9-2 ³ = 1. The same applies hereinafter.
You. The total number of possible output codes is 2 ⁿ = 8
In contrast, the number of codes actually output is also eight.
Was. Here, the total number of possible output codes is n bits
0 to the total number of numbers that can be represented in binary
(2 ⁿ -1) 2 ⁿ pieces. With digital code
Is a numerical value expressed in a binary system. For example, digital
The code “001” represents “1” and the digital code
The code “010” represents “2” and the digital code “
011 "represents" 3. "
000, 0 for n = 3 bits
01,010,011,100,101,110,11
1 and the total number of code types is eight.

[0004] Conventional digital direct synthesizers generate spurious noise. The spurious is generated due to the quantization error in the data memory 4 and the nonlinearity of the digital-to-analog converter 6. When
At that time, the digital-to-analog converter is i, 2
i, 4i, 8i ···, with weights in binary as of 2 ⁿ i
Output current according to the input digital code.
I'm working. Each of these binary weights contains an error.
The correct digital code corresponding to the input digital code.
No analog output is obtained. This characteristic is
It is called the non-linearity of the log converter. Then, the non-linearity of the digital-to-analog converter 6 is determined by the code the total number that can take the digital-to-analog converter 6. Here, the code the total number that can be taken, de
Digital input to digital-to-analog converter
This is the total number of code types.
It is repeated in period T. Code the total number at this time is considered to m ₁
I don't mind. The total number of possible codes is fo
From the formulas of T and T: fs · T = m ₁ = m ₂ · fs / fo = (m ₂ / k) · 2 ⁿ Where the output value of the phase accumulator
Is supplied to the address input of the memory. Out of that memory
The force naturally changes according to the input address value. So
The digital-to-analog converter
Output analog voltage or current according to the output value of the memory
Power. Generally, digital-to-analog converters
Non-linear errors are adjusted so that they approach zero as an average.
However, if you look at only some of the digital codes,
Includes large errors. That is, digital / analog
Using all of the digital input codes of the
The average error is reduced.

In the conventional digital direct synthesizer, the output frequency fo is controlled only by changing the size of the increment data k. Therefore, depending on the value of the output frequency fo, fs.T is extremely large. Less. In this case, energy is concentrated on a small number of spurious spectra, and the level of these spurious signals becomes high. This is shown in FIG. That is, non-linear
Repetition of a fixed pattern where the type error is not random like noise
If it's a return, it's
It is because it is observed. Further to explain,
The frequency spectrum that is the area that defines
Digital direct synthesizer output signal
This is the result of Fourier transformation. What is Fourier transform?
Sine waves of any frequency in the time waveform of the signal of interest
Correlation function between the sine wave and the cosine wave.
The results of evaluating the correlation value for each frequency of the cosine wave and
To tell. Large correlation for signals with repeated characteristics
The value of the spectrum peak) is observed. Where
Digital input to digital-to-analog converter
One with short repetition of code and a small total number of codes
Then, for example, harmonic components such as square wave and triangle wave
This results in a lot of inclusion. However, digital code
If the return is long and the total number of codes is large,
For example, a sinusoidal waveform with thermal noise added
No harmonic components are included .

Here, for example, the output frequency fo = 640K
With regard to HZ, k = 64 is obtained by substituting f ₀ = 640 KHz into f ₀ = k × 10 (KHz). Since 2 ¹⁰ = 1024 is divisible by 64, m ₂ = 1. The repetition frequency of the accumulator output matches the output frequency f ₀ . That is, the phase accumulator returns to the original value after 16 clocks with k = 64. This is f ₀ = f _s / 16. m ₂ gives the ratio of the period T of the complete repetition at the output of the phase accumulator to 1 / f ₀ . in this case,
Since T is equal to 1 / f ₀ , m ₂ = 1 is apparently obtained. Tf _S = m ₁ from Equations 1 and 2, _{also, fo = m 2 / T =} (k / 2 n) / f and _{S ^{deformed, Tf S = 2 n · m}} 2 / k The formula and Tf _S = From m ₁ , T · f _S = m ₁ = 2 ^nm · m ₂ / k In the case of the output frequency fo = 1 MHz, k = 100 is obtained, and since n = 10, m ₁ = 1024 · since m _2/100 equation 3 m ₁ and m ₂ is a positive integer, equation 1 in the right side of the equation 3
Minimum m ₂ to 30.24 × m ₂ of an integral is 25. Therefore, at this time, m ₁ = 256. That is, 25
m ₁ = 256 m ₂ holds. m ₁ = fs · T = 256.

[0007] In some cases, the digital direct synthesizer may want to reduce the spurious energy level of the synthesized signal spectrum to a predetermined level or less. The idea is to know the period T of the output pattern of the phase accumulator, and to adjust the energy level of the spurious by selecting fs · T.

[0008]

A phase accumulator 3 to which the increment data k and the clock signal fs are supplied, a data memory 4 storing a waveform, a digital / analog converter 6, and a low-pass filter 7 comprises a signal source 1 'comprising a plurality of clock signal sources 1 having different repetition frequencies generated as signal sources for generating a clock signal fs, and comprising a plurality of clock signal sources.
Switch source 1 to phase accumulator 3 and connect
A period measuring circuit 8 for measuring the output pattern period T of the phase accumulator 3 for each clock signal.
The product of the clock frequency f _s and the output pattern period T
And the spurious level of the composite signal is calculated from the product
Select a value that is less than or equal to the specified level, and
A signal for selecting a lock signal source is supplied to the selection circuit 2.
A digital direct synthesizer including the lock selection control circuit 11 was constructed.

[0009]

An embodiment of the present invention will be described with reference to FIG. The digital direct synthesizer according to the present invention is provided with a plurality of clock signal sources 1 having different repetition frequencies generated from the conventional digital direct synthesizer shown in FIG. Further, this corresponds to a circuit provided with a period measuring circuit 8 and a clock selection control circuit 11 for measuring the output pattern period T of the phase accumulator 3 for each clock fs.

That is, any one of the plurality of clock signal sources 1 ′ selected via the selection circuit 2 sends the clock signal fs to the phase accumulator 3. Exit of phase accumulator 3
Power is supplied by a bit / OR circuit 9 and a D-type flip-flop.
The signal is sent to the period measuring circuit 8 through the line 10. Phase
The output pattern period T of the accumulator 3 is
The clock frequency fs in the period measurement circuit 8
Is required. This will be explained in more detail later.
It is .

Here, referring to the timing chart of FIG. 4, when the reset is released, the clock frequency fs
, The phase accumulator 3 and the cycle measuring circuit 8 start operating. Thus, the output pattern period T of the output of the phase accumulator 3 with respect to the clock frequency fs is measured, and the number of possible codes can be known. As described above, the target output frequency fo is determined by fo = (k / 2 ⁿ ) · fs. When the clock frequency fs is selected by the clock selection control circuit 11, the output frequency fo differs by the number of clock signal sources 1. The total number of codes to be obtained, fs.T, can be selected. Furthermore,
Specifically, the phase accumulator
The clock frequency fs and the output frequency
If the number fo is given as a _{condition, k · f s = f 0} ·
Digital direct synthesizer k to be a 2 ⁿ
If the phase accumulator input is set to f _s
Is varied by other conditions , the output frequency f ₀ is
Can be fixed. Get the same f ₀ to a plurality of f _s
To, switches the f _s, increment data
The value of ta kk is also changed. That is, as described above,
The maximum possible code total number f _s · T is the maximum
Select the click frequency fs, to match the product k · f _s to f ₀
Set as needed.

[0012]

As described above, according to the digital direct synthesizer of the present invention, a certain output frequency
It is possible to select the total code number fs · T that can be different from each other by the number of clock signal sources 1 with respect to the wave number fo ,
The spurious energy of the spectrum of the signal to be synthesized can be dispersed in frequency to adjust the spurious level. If this synthesizer is applied to various measuring instruments, the measuring accuracy of the measuring instruments can be improved.

An application example of the digital direct synthesizer according to the present invention will be described below. FIG. 5 is a diagram illustrating an example of application to a signal analyzer. The memory storing Sin and Cos is read from the output of the phase accumulator, and the result of multiplication with the signal to be analyzed by the multiplying DAC is integrated to perform Fourier analysis.

FIG. 6 is a diagram for explaining an application example to a transfer function measuring device. That is, the output signal synthesized by the phase accumulator of FIG. 3 is applied to the DUT, and only the input and output or only the output of the DUT are synchronized with the clock frequency fs of the phase accumulator. AD conversion.

[Brief description of the drawings]

FIG. 1 is a diagram showing a conventional example of a digital direct synthesizer.

FIG. 2 is a diagram showing a frequency spectrum of an output signal.

FIG. 3 is a diagram showing a digital direct synthesizer of the present invention.

FIG. 4 is a diagram showing a correlation between waveforms.

FIG. 5 is a diagram showing an application example of the present invention to a signal analyzer.

FIG. 6 is a diagram showing an application example of the present invention to a transfer function measuring device.

FIG. 7 is a diagram illustrating a phase accumulator .

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 clock signal source 2 selection circuit 3 phase accumulator 4 data memory 5 latch 6 digital-analog converter 7 low-pass filter 8 cycle measurement circuit 9-bit OR circuit 10 D-type flip-flop 11 clock selection control circuit

Claims (1)

(57) [Scope of request for utility model registration] 1. A digital direct synthesizer comprising a phase accumulator to which increment data and a clock signal are supplied, a data memory storing a waveform, a digital-to-analog converter, and a low-pass filter. A signal source comprising a plurality of clock signal sources having different repetition frequencies generated as signal sources for generating clock signals, wherein the plurality of clock signal sources are connected to a phase accumulator.
And a period measuring circuit for measuring the output pattern period of the phase accumulator for each clock signal. The clock frequency of each clock signal and the period of each output pattern are provided.
And calculate the spurious level of the composite signal from the product.
Select a value at which the level falls below a specified level, and
A signal for selecting a clock signal source to be supplied to the selection circuit
A digital direct synthesizer comprising a clock selection control circuit .