JP2570998B2 - Branch instruction processing device and branch instruction processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a branch instruction processing apparatus and a branch instruction processing method, and more particularly to a branch instruction processing apparatus and a branch instruction processing method for optimizing a branch instruction in an assembler.

[0002]

2. Description of the Related Art In a microprocessor program using an assembler language, the code length of a branch instruction varies depending on the distance between the branch instruction and a label to which the branch instruction refers. In this type of program, when the user codes the above-mentioned branch instruction, the code length is appropriately selected and specified, or the branch instruction having the shortest code length corresponding to the branch destination position of the above-mentioned branch instruction (hereinafter the shortest branch instruction) A translation program such as a compiler or an assembler selects a tentative branch instruction (hereinafter, a tentative branch instruction) written by a user for replacement and performs the above replacement. This is called branch instruction optimization.

Referring to FIG. 7, which shows a block diagram of a conventional branch instruction processing device, this conventional branch instruction processing device includes a source file 1 serving as an input file, an assembler 2 performing assembler processing, and an object file serving as an output file. File 3.

The assembler 2 includes a source file input unit 4 for reading the source file 1, a syntax analysis unit 5 for analyzing the syntax of the read source file 1, generating a symbol table 6 and outputting the intermediate information 7, and a branching unit. An optimization processing unit 8 that performs an instruction optimization process, an intermediate information analysis unit 9 that performs an analysis process of intermediate information to generate an object code, and an object file output unit 10 that outputs the object code to the object file 3 are provided. .

The syntax analyzer 5 includes a branch information generator 51 for supplying branch information to the branch information table 11 when the content of the syntax analysis is a temporary branch instruction.

Next, the operation of the conventional branch instruction processing device will be described with reference to FIG. 7. The source file input unit 4 sequentially reads the source files 1 and supplies them to the syntax analysis unit 5. The syntax analysis section 5 analyzes the syntax of the read content, generates a symbol table 6 described later, and outputs the analysis content as intermediate information 7. If the content of the syntax analysis is a temporary branch instruction, the branch information generation unit 51 supplies the branch information to a branch information table 11 described later. After that, the optimization processing unit 8 receives the provisional branch instruction, the symbol table 6, the intermediate information 7, and the branch information table 11, and corrects the provisional address of the symbol table 6 to a correct address after optimization. Execute branch instruction optimization processing. Next, the intermediate information analysis unit 9 analyzes the intermediate information, generates an object code, and outputs the generated object code as the object file 3 via the object file output unit 10.

Symbol table 6 and branch information table 1
Referring to FIG. 8 showing the relationship between the symbol analysis unit 1 and the input source file 1, when n symbol definitions and k provisional branch instructions are described in the source code of the input source file 1, the syntax analysis unit 5 Table 6 shows symbol entries S1 to Sn
On the other hand, the branch information generation unit 51 generates branch information entries B1 to Bn in the branch information table 11.

Each of the symbol entries S1 to Sn has a branch information field A and an address field B. The branch information field A is a field for storing a pointer corresponding to a recently generated branch information entry, and the address field B is a field for storing the address of the symbol. However, the above address may not be determined if there is a provisional branch instruction before the symbol definition. In this case, the address is assumed to be an address when it is assumed that all provisional branch instructions are replaced by the shortest code instructions.

Each of the branch information entries B1 to Bn includes a branch destination field A for storing a pointer corresponding to the symbol entry of the branch destination, a branch address field B for storing an address in which the temporary branch instruction is described, and a A code increase product field C for storing a byte length at which the address of the temporary branch instruction is larger than that of the temporary branch instruction preceding the branch information, and a byte length that may be larger than the temporary branch instruction preceding the branch information. And a code increase amount field E that stores information on whether or not the code length of the branch information is determined. If the code length is determined, the code increase amount field E stores the code length. It has five fields.

Referring to FIG. 9 showing a flowchart of the optimization processing unit 8, a symbol table 6 and a branch information table 1 are shown.
More specifically, the operation of the optimization process performed by using No. 1 will be described. First, in the initialization process of step P1, initialization of the branch information position in the branch information table 11, initialization of the address increase amount, and the determined branch amount Is initialized. Further, the processing unit for operating the branch information entry operates on the branch information entry at the branch information position. By the initialization of the branch information position, the address increase amount, and the determined branch amount, the branch information position becomes the first entry of the branch information table 11, that is, the branch information entry B1.
, The address increment is 0, and the determined branch amount is 0 bytes.

Here, for convenience of explanation, the branch information position indicates the branch information entry Bk, the temporary branch destination is the j-th symbol entry Sj, and the branch information entry corresponding to the true branch destination is the i-th, that is, the branch information entry. It is assumed that the information entry is Bi.

In the address increasing process in step P2, the address of the address field BkB is increased by the address increasing amount. Next, branch information determination processing (step P
In 3), it is determined whether or not the information of the code increase field BkE is undecided and can be solved. If yes, the process proceeds to Step P4 to perform a branch information solving process. If not, the process proceeds to Step P5 to perform a code increase process. The above determination is performed as follows. Branch destination address field BkA
Thus, the address AD1 of the address field SjB of the symbol entry Sj of the branch destination becomes the above-mentioned branch destination address, but since this is a temporary address, it is further corrected using the branch information entry Bi indicated by the pointer of the branch information field SjA. I do. The address AD2 of the branch target field BkA and the code increase product of the code increase product field BiC of the branch information entry Bi are CD1 and the code increase product of the code increase possible product field BiD is CD2.
Then, the following determination processing is performed. That is, when the difference between AD2 and AD1 + CD1 + CD2 is equal to or less than the branch width (replacement branch width) at which the shortest branch instruction is replaced, the temporary branch instruction is replaced with a branch instruction having a shorter code length (short branch instruction). You. If the difference exceeds the replacement branch width, the provisional branch instruction is replaced with a branch instruction having a longer code length (long branch instruction).

The branch information solving process (step P4) stores 0 in the code increase amount field BkE and adds 1 byte to the determined branch amount if it is replaced with a short branch instruction corresponding to the above determination position in step P3. I do. If it is replaced by a long branch instruction, 1 is stored in the code increment field BkE, and one byte is added to each of the address increment and the determined branch parameter.

In the code increase process (step P5), the address increase amount is added to the increase product of the code increase product field BkC, the number of determined branches is subtracted from the increase amount of the code increase product field BkD, and the branch information in step P6 is obtained. Perform position determination processing. Branch information position determination processing (step P
In 6), it is determined whether or not the branch information position is the last. If not, the branch information position increasing process in step P7 is performed, and if it is the last, the process proceeds to the end determination process in step P8.

In the branch information position increasing process (step P7), the branch information entry Bk indicated by the branch information position is
k + 1, and then the address increase processing (step P
Return to 2). In the end determination process (step P8), if all the branch information entries B1 to Bk have been determined, the symbol table conversion process (step P9) is performed. If not, the process returns to the initialization process (step P1) and the remaining process is performed. P1 to P9 are executed again.

Symbol table conversion processing (step P
In 9), the tentative addresses of all the symbol information entries S1 to Sn are corrected to correct addresses, and the optimization process is completed.

The correction method will be described. The storage address of the address field SiB of the symbol entry Si to be corrected is assumed to be AD1, and the code increase product of the branch information entry Bi specified by the branch information field SiA is calculated. Assuming that CD1, the value of the address field SiB is a new address value AD1 + CD1.
And store it again.

As described above, in the processing of the optimizing processing section 8, the branch information table 11, which is the same number of temporary branch information as the number of temporary branch instructions described in the source file 1, is generated in the branch information table 11. Therefore, this branch information table 1
The memory capacity for storing 1 must be large enough.

[0019]

The conventional branch instruction processing device and the conventional branch instruction processing method described above require a large-capacity memory area for generating the same number of temporary branch information as the number of temporary branch instructions in the optimization process. There was the disadvantage of needing. Further, when a large number of temporary branch instructions are described, there is a drawback that an error occurs due to a shortage of memory capacity, and an execution time is delayed by using an external temporary file.

[0020]

According to the present invention, there is provided a branch instruction processing apparatus and a branch instruction processing method for a microprocessor having a code length of a branch instruction which differs depending on a distance between the branch instruction and a label to which the branch instruction is referred. Source file input means for reading a source file including the label described in the assembler language and the provisional branch instruction corresponding to the branch instruction for processing the assembler program; and analyzing the read source file for syntax to read the source file. Syntactic analysis means for generating a symbol table for storing the symbol entry of the above and a branch information table for storing a branch information entry corresponding to the temporary branch instruction, and a code length of the branch instruction generated by correcting the temporary branch instruction. Optimization processing means for performing optimization processing, which is processing to minimize the processing time In the branch information table having a circular list structure in which buckets, which are storage areas for storing a predetermined number of the branch information entries, are circularly arranged when the syntax analysis result is the temporary branch instruction. Executing the optimization processing by accessing the optimization processing means in response to reaching an upper limit of the number of branch information entries that can be stored in the branch information table; List upper limit determining means for releasing the bucket corresponding to the optimized branch information entry to empty.

[0021]

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which constituent elements common to those in FIG. 7 are denoted by common reference numerals / characters, and FIG. The branch instruction processing device of the example includes, in place of the assembler 2, a source file input unit 4, an intermediate information analysis unit 9, and an object file output unit 10 similar to the conventional one, and a syntax analysis unit 5 instead of the syntax analysis unit 5. A conventional branch information generating unit 51A for supplying branch information to the branch information table 12 having a circular list structure when the analysis result is a temporary branch instruction; and a list upper limit determining unit 52 for determining the upper limit of the list of the branch information table 12. In the same manner as the above, a syntactic analysis unit 5A that outputs the symbol table 6 and the intermediate information 7 and an optimization processing unit 8A that performs a branch instruction optimization process using the branch information table 12 instead of the optimization processing unit 8 are provided. It comprises assembler 2A.

Next, the operation of the present embodiment will be described with reference to FIG. 1. The overall processing flow is the same as that of the above-described conventional technique, and the syntax analyzer 5A directly related to the present invention.
The description of the other parts than the optimization processing unit 8A and the branch information table 12 will be omitted because they are duplicated.

First, the source file input section 4 sequentially reads the source file 1 and supplies it to the syntax analysis section 5A. The syntax analysis unit 5A analyzes the syntax of the read content, generates the symbol table 6, and outputs the analysis content as the intermediate information 7. When the content of the syntax analysis is a temporary branch instruction, the branch information generation unit 51A supplies the branch information to a branch information table 12 described later. After that, the optimization processing unit 8
A receives the provisional branch instruction, the symbol table 6, the intermediate information 7, and the branch information table 12, and corrects the provisional address of the symbol table 6 to a correct address after optimization, thereby performing the branch instruction optimization processing. Run.
Next, the intermediate information analysis unit 9 analyzes the intermediate information, generates an object code, and outputs the generated object code as the object file 3 via the object file output unit 10.

Referring to FIG. 2 showing the relationship between the symbol table 6 and the branch information table 12 according to the present embodiment, the branch information table 12 stores N buckets 121 to 12N which are areas for storing branch information entries. It has a cyclic wrist structure. This number of buckets N is twice the longest branch width that allows branching. For example, if the longest branch width is 128 bytes, the number of buckets N is 256. As described above, when n symbol definitions and k provisional branch instructions are described in the source file 1, the branch information entries B1 to Bk are stored in the buckets 121 to 12k of the branch information table 12, respectively. . Each of the branch information entries B1 to Bk has five fields of a branch destination field A, a branch address field B, a code increase product field C, a code increase possible product field D, and a code increase amount field E, as in the related art. With two fields. On the other hand, the symbol table 6 stores n symbol entries S1 to Sn having a branch information field A and an address field B as in the related art.

When the branch information generation unit 51A generates the branch information entry B, the list upper limit determination processing unit 52 stores the branch information entry B in the branch information table 12,
Branch information entry B that can store the branch information table 12
Is reached, that is, N, the optimization processing unit 8 is accessed to execute the optimization processing, and the bucket corresponding to the optimized branch information entry in the branch information table 12 is released as empty. . The storage of the branch information entry B in the branch information table 12 includes a bucket storage position indicating the position of the bucket for storing the generated branch information entry and a bucket last indicating the next bucket position of the last bucket that can store the branch information entry. This is performed using the position.
The initial value of the bucket storage position and the initial value of the bucket last position are both the first bucket 12 of the branch information table 12.
It is one.

The operation of the list upper limit determination process will be described with reference to FIG. 3 which is a flowchart of the algorithm of the process of the list upper limit determination processing unit 52. First, in the bucket storage process of step Q1, the bucket storage position is instructed. The branch information entry Bk is stored in the bucket (here, 12k for convenience of explanation). When the storage of the branch information entry Bk is completed, the bucket storage position is changed to the bucket 12k +
1 is performed to increase the bucket storage position (step Q2). Next, in step Q3, bucket storage position determination processing is performed. If the bucket storage position and the bucket end position match, the optimization processing unit 8 executes optimization processing (step S100), and after this optimization processing ends, the bucket last position where the bucket last position has not been released is not released. Bucket last position update processing (step Q
4) is performed, and the list upper limit determination process ends. If they do not match, the list upper limit determination process is terminated.

The algorithm of the optimization processing (step S100) in the optimization processing unit 8A of this embodiment will be described in more detail with reference to FIG.
First, initialization of the branch information position in the branch information table 12, initialization of the address increase amount, and initialization of the determined branch amount are performed by the initialization processing in step S1 similar to the related art. Also,
The processing unit for operating the branch information entry operates on the branch information entry at the branch information position. By initializing the branch information position, the address increment, and the determined branch amount, the branch information position is stored in the first entry of the branch information table 12, ie, the bucket 121, when the optimization process is performed for the first time. The second and subsequent times indicate the position set at the end of the preceding optimization process. The branch information last position indicates the branch information entry generated immediately before the execution of the optimization processing. The address increment is 0 bytes, and the determined branch amount is 0 bytes.

Here, for convenience of explanation, the branch information position indicates the branch information entry Bk stored in the bucket 12k, the temporary branch destination is the j-th symbol entry Sj, and the true branch is performed. It is assumed that the corresponding branch information entry is the i-th branch information entry Bi.

Step S2 similar to conventional step P2
In the address increase process, the address of the address field BkB is increased by the address increase amount. Next, in the branch information determination process (step S3), it is determined whether or not the information of the code increase field BkE is undecided and can be solved as in the conventional step P3. That is, assuming that the address AD1 of the branch destination address field SjB, the address AD2 of the branch destination field BkA and the code increase product CD1 of the code increase product field BiC, and the code increase possible product of the code increase possible product field BiD are CD2, AD2 and AD1 + CD1 + CD2. If the difference from the above is less than or equal to the replacement branch width, the temporary branch instruction is replaced by a short branch instruction, and if the difference exceeds the replacement branch width, the temporary branch instruction is replaced by a long branch instruction. If yes, the process proceeds to step S4 to perform a branch information solving process. If no, the process proceeds to step S5 to perform a code increase process.

The branch information solving process (step S4) stores 0 in the code increase amount field BkE and adds 1 byte to the determined branch amount when it is replaced with a short branch instruction corresponding to the above-described determination position in step S3. I do. When replaced by a long branch instruction, 1 is stored in the code increase field BkE, and 1 byte is added to each of the address increase and the determined branch.

In the code increase process (step S5), the address increase amount is added to the increase product of the code increase product field BkC, the number of determined branches is subtracted from the increase amount of the code increase product field BkD, and the branch information of step S6 is obtained. Perform position determination processing. Branch information position determination processing (step S
6) It is determined whether or not the branch information position matches the branch information end position. If not, the branch information position increasing process of step S7 is performed, and if the branch information position matches, the process proceeds to the unsolved determination process of step S10.

In the branch information position increase processing (step S7), the storage bucket 12k of the branch information entry Bk indicated by the branch information position is changed to the storage bucket 12k + 1 of the next branch information entry Bk + 1, and then the address increase processing (step S7). Return to S2). The unsolved determination processing (step S9) proceeds to the branch information exception resolution processing (step S13) when the determined branch amount is 0 bytes, and proceeds to the end determination processing (step S10) otherwise.

Branch information exception solution processing (step S13)
Determines all branch information entries stored from the bucket next to the last position of branch information to the N / 2th bucket as long branch instructions.

In the end determination process (step S10), if all branch information entries stored from the next bucket at the last position of the branch information to the N / 2th bucket have been determined, a symbol table conversion process (step S11) If not, the process returns to the initialization process (step S1), and steps S1 to S11 are executed again for the remaining portion.

Symbol table conversion processing (step S1)
In 1), the temporary addresses of all the symbol information entries S1 to Sn are corrected to correct addresses in the same manner as in the conventional step P9, and the bucket release processing in step S12 is performed, and this optimization processing is completed. .

The bucket release processing (step S12)
The memory area from the bucket next to the last position of the branch information to the N / 2-th bucket is released, the leading position of the branch information is set at the beginning of the released bucket, and the optimization process ends.

The operation of the above-described optimization processing will be described more specifically with reference to Table 1 showing an example of the source file 1. The assembler source shown in this table has 50
0 label definitions lab001 to lab500,
The description of the provisional branch instructions br lab001 to br lab500 is shown. Here, for convenience of explanation, the allowable maximum branch width by the short branch instruction in steps S3 and S4 is set to 128.
Therefore, the number of buckets N in the branch information table 12 is set to 256, which is twice the allowable maximum branch width.

[0038]

[Table 1]

The source file 1 having the contents shown in Table 1 is supplied as 1
When sequentially received for each line, the syntax analysis unit 5A performs a syntax analysis for each line and generates a corresponding symbol table 6 and a branch information table 12. If the syntax analysis result of a certain line is a temporary branch instruction, the branch information generation unit 51A generates a branch information entry. At the same time, the list upper limit determination unit 52 determines whether the list to be stored, that is, the upper limit of the number of buckets, has been exceeded. As described above, the number of buckets N is 256
Since the 256th branch information entry is generated, the above upper limit value is exceeded. The list upper limit judging section 52 responds to the excess of the upper limit value by optimizing the provisional branch instruction.
Perform optimization processing by.

When the optimization processing unit 8 is accessed, the symbol table 6 has 256 symbol entries,
The branch information table 12 stores 256 branch information entries. As a result of the execution of the optimization processing, provisional branch instructions corresponding to the 128th branch information entry from the top of the branch information table 12 are determined, and the corresponding 12
Eight buckets are empty.

After completion of the above-mentioned optimization processing, the syntax analysis unit 5
Resume parsing by.

Further, when the branch information entries corresponding to the 128 temporary branch instructions are generated, the upper limit value 256 is exceeded again. The optimization processing by the instruction optimization processing unit 8 is performed.

When the optimization processing unit 8 accesses again, the symbol table 6 has 1
28 symbol data entries or 384 symbol entries are stored, and the branch information table 12 stores 256 branch information entries. As a result of the optimization processing, the tentative branch instructions corresponding to the 129th to 256th branch information entries in the branch information table 12 are determined, and the corresponding 12
Eight buckets are empty.

After completion of the above-mentioned optimization processing, the syntax analysis unit 5
Resume parsing by.

As described above, in this embodiment, even if the memory capacity of the branch information table 12 having a fixed memory capacity is constant, it is possible to process a large number of temporary branch instructions exceeding this memory capacity.

Referring to FIG. 5 showing a second embodiment of the present invention, the optimization processing unit 8B of the assembler 2B of this embodiment shown in this figure presets the number of buckets in the branch information table as necessary. A bucket expansion processing unit 81 is provided, which increases the number by a number and shifts the bucket end position by the increase number.

The operation will be described with reference to FIG. 6 showing a flowchart of the optimization processing unit 8B of this embodiment. The difference from the first embodiment shown in FIG. That is, instead of the processing, the bucket expansion processing of step S14 is added. In this case, since the branch destination of the temporary branch instruction is far ahead, for example, 60 branches ahead, there is no branch information entry that can determine the temporary branch instruction in the normal optimization processing, and the unresolved determination is made. In this case, the problem can be solved by, for example, bucket expansion processing for adding 60 buckets.

[0048]

As described above, according to the branch instruction processing apparatus and the branch instruction processing method of the present invention, the syntax analysis means includes:
Branch information generating means for supplying the branch information to a branch information table having a circular list structure in which a fixed number of buckets are circularly arranged when the result of the syntax analysis is a temporary branch instruction; and a storable branch information entry of the branch information table List upper limit determination processing means for executing an optimization process in response to the upper limit of the number of data items, that is, reaching the certain number, and releasing the bucket corresponding to the optimized branch information entry to empty. Even if the number increases, the required memory area can be kept at the above-mentioned fixed number, so that the required memory area can be saved.

Further, there is an effect that occurrence of an error due to lack of memory capacity and occurrence of a delay in execution time due to use of an external temporary file can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a branch instruction processing device according to the present invention.

FIG. 2 is a diagram illustrating a configuration of a symbol table and a branch information table of the branch instruction processing device according to the embodiment.

FIG. 3 is a flowchart illustrating an operation of a list upper limit determination processing unit of the branch instruction processing device according to the present embodiment.

FIG. 4 is a flowchart illustrating a branch instruction processing method according to the embodiment.

FIG. 5 is a block diagram showing a second embodiment of the branch instruction processing device of the present invention.

FIG. 6 is a flowchart illustrating a branch instruction processing method according to the present embodiment.

FIG. 7 is a block diagram showing an example of a conventional branch instruction processing device.

FIG. 8 is a diagram showing a configuration of a symbol table and a branch information table of a conventional branch instruction processing device.

FIG. 9 is a flowchart showing a conventional branch instruction processing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Source file 2, 2A, 2B assembler 3 Object file 4 Source file input part 5, 5A Syntax analysis part 6 Symbol table 7 Intermediate information 8, 8A, 8B Optimization processing part 9 Intermediate information analysis processing part 10 Object file output part 11 , 12 branch information table 51 branch information generator 52 list upper limit determination processor 81 packet extension processor

Claims (7)

(57) [Claims] 1. A label and a branch instruction described in an assembler language for processing an assembler program for a microprocessor in which a code length of the branch instruction varies depending on a distance between the branch instruction and a label referenced by the branch instruction. Source file input means for reading a source file including a corresponding provisional branch instruction, a symbol table for storing the symbol entry corresponding to the label by performing syntax analysis of the read source file, and a branch information entry corresponding to the provisional branch instruction And a optimizing processing means for performing an optimizing process which is a process of correcting the tentative branch instruction to minimize the code length of the generated branch instruction. In the branch instruction processing apparatus, the syntax analysis unit may be configured such that the syntax analysis result is the temporary branch instruction. Branch information generating means for supplying the branch information to a branch information table having a circular list structure in which buckets, which are storage areas for storing a predetermined number of the branch information entries, are circularly arranged; and storing the branch information table. In response to the arrival of the upper limit of the number of possible branch information entries, the optimization processing means is accessed to execute the optimization processing, and the bucket corresponding to the optimized branch information entry is emptied. A branch instruction processing device comprising: a list upper limit determination processing unit to be released. 2. The symbol entry has a branch information field storing a pointer corresponding to the branch information entry that has been recently generated, and an address field storing an address of the symbol, wherein the branch information entry is the temporary branch instruction. A branch destination field for storing a pointer corresponding to the symbol entry of the branch destination, a branch address field for storing an address where the temporary branch instruction is described, and a branch address field for storing the address of the temporary branch instruction before the branch information. A code increase product field for storing a byte length that is greater than the second provisional branch instruction, a code increase product field for storing a byte length that is likely to be greater than the second provisional branch instruction, and a code for the branch information Information on whether the length has been determined is stored. If the length has been determined, the code length is stored. Branch instruction processing apparatus according to claim 1, characterized in that it comprises a code increment field. 3. The optimization processing means according to claim 2, wherein said optimizing processing means is configured such that when said optimizing processing becomes impossible because a branch destination of said temporary branch instruction branches forward beyond a predetermined first number of said branch instructions. 2. The branch instruction processing device according to claim 1, further comprising a bucket extension processing unit that increases the number of buckets by a predetermined second number. 4. The label and the branch instruction described in an assembler language for processing an assembler program for a microprocessor in which a code length of the branch instruction varies depending on a distance between the branch instruction and a label referenced by the branch instruction. Reading a source file including a corresponding temporary branch instruction, parsing the read source file, and storing a symbol entry corresponding to the label and a branch information table storing a branch information entry corresponding to the temporary branch instruction And a branch instruction processing method for performing an optimization process that is a process of correcting the temporary branch instruction to minimize the code length of the generated branch instruction, wherein the branch information table has a predetermined number of the A circular list structure in which buckets, which are storage areas for storing branch information entries, are arranged in a ring. And executing the optimization process in response to the reaching of the upper limit of the number of the branch information entries that can be stored in the branch information table, and releasing the bucket corresponding to the optimized branch information entry to empty. A branch instruction processing method characterized by performing a list upper limit determination process. 5. A bucket storage process in which the list upper limit determination process stores the branch information entry in the bucket indicated by a bucket storage position which is information indicating a position of the bucket storing the generated branch information entry. A bucket storage position increase processing step of changing the bucket storage position to indicate a second bucket storage position that is increased by a predetermined number from the bucket storage position; and a last storeable storage of the bucket storage position and the branch information entry. A comparison is made with a bucket end position indicating the next bucket position of the bucket. If the bucket storage position and the bucket end position match, the optimization processing is executed. Ending the bucket storage position, and ending the optimization process. 5. The branch instruction processing method according to claim 4, further comprising: a bucket last position update processing step of setting a last position to a last bucket that has not been released. 6. A branch information field in which the symbol entry stores a pointer corresponding to the recently generated branch information entry, and an address field in which an address of the symbol is stored, wherein the branch information entry is the temporary branch instruction. A branch destination field for storing a pointer corresponding to the symbol entry of the branch destination, a branch address field for storing an address where the temporary branch instruction is described, and a branch address field for storing the address of the temporary branch instruction before the branch information. A code increase product field for storing a byte length that is greater than the second provisional branch instruction, a code increase product field for storing a byte length that is likely to be greater than the second provisional branch instruction, and a code for the branch information Information on whether the length has been determined is stored. If the length has been determined, the code length is stored. A code increment field, wherein the optimizing process initializes the branch information position and the address increment and sets each of the determined branch values to a predetermined initial value; and the address field Address increase processing step of increasing the address by the address increase amount; branch information determination processing step of determining whether or not the information of the code increase amount field is undecided and can be solved, and generating a first determination result; A branch information solution processing step of executing a predetermined correction process for determining the branch instruction in response to the above determination if the first determination result is undecided and can be resolved; A code increase processing step of executing a predetermined code increase processing if it cannot be solved; and whether the branch information position matches the branch information end position. Branch information position determination processing step of determining whether or not the branch information position is to be generated, and if the second determination result is negative, the branch information position indicated by the branch information position is stored in the next branch information entry And a branch information position increasing process step of changing to the storage bucket of the above. If the second determination result matches, it is determined whether or not the determined branch amount corresponding to the branch information position is a predetermined value. An unresolved determination processing step of generating a determination result, and if the third determination result is the value, the branch information is stored from a bucket next to the last position of the branch information to a second predetermined bucket. A branch information exception solution processing step of determining all branch information entries as long branch instructions having a longer code length; and the second number bucket from the bucket next to the last position of the branch information. 5. A branch instruction processing method according to claim 4, further comprising the step of: releasing a memory area up to the first packet and setting a branch information head position to a head of the bucket after the release. 7. A bucket extension processing step of increasing the number of buckets in the branch information table by a predetermined number and shifting the last position of the bucket by the increase number instead of the branch information exception solution processing step. 7. The branch instruction processing method according to claim 6, wherein: