JP2567155B2 - Clock adjustment method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock adjusting system for suppressing skew between clocks supplied to an LSI and another circuit synchronized with the LSI.

When the LSI and other circuits are operated synchronously to transfer data between them, the same clock is used for both.

However, as the speed of data transfer increases, the skew between the clocks supplied to both of them increases, making it difficult to synchronize them.

For this reason, it has become necessary to adjust the delay of both clocks to suppress the skew between the clocks.

[0005]

2. Description of the Related Art In FIG. 3, flip-flops 57 and 58 of an LSI 22 and a flip-flop 36 operate synchronously to transfer data between them.

Therefore, the clock of the crystal oscillator 32 is used by the LSI 22 and the flip-flop 36.

In the figure, receivers 50 (delay amount = DL1), 5 are provided as elements for clock delay adjustment.
2 (delay amount = DL2), drivers 54 (delay amount = DL3), 56 (delay amount = DL4) are LSI 22
The clock of the crystal oscillator 32 is provided inside the main circuit portion 1 via the receivers 50, 52 and the driver 54.
6 flip-flops 57 and 58.

The clock of the crystal oscillator 32 is again sent to the outside of the LSI via the receiver 50 and the driver 56, and is supplied to the flip-flop 36 via the driver 60 (delay amount = DL5).

In the LSI 22, the flip-flop 5
Output data is obtained at 8 (delay amount = DL12), and the data is given to the external gate 64 (delay amount = DL7) via the driver 62 (delay amount = DL6).

The output data of the gate 64 is input to the flip-flop 36, and the output data of the flip-flop 36 (delay amount = DL10) is given to the receiver 66 (delay amount = DL8) of the LSI 22.

Further, the data received by the receiver 66 is input to the gate 68 (delay amount = DL13) via the flip-flop 57 (delay amount = DL11), and the output data of the gate 68 is input to the flip-flop 58 ( Delay amount for transfer between FFs inside LSI = DL11
+ DL13).

Here, the delay amount DL2 of the receiver 52
And the delay amount DL5 of the driver 60 are set to be equal (DL2 = DL5), and the delay amount DL3 of the receiver 54 is set.
And the delay amount DL4 of the driver 56 are also set to be equal (DL3 = DL4).

Therefore, the delay amount of the clock supplied from the crystal oscillator 32 to the circuit portion 16 (= DL1 + D
L2 + DL3) and the delay amount (= DL1 + DL4 + DL5) of the clock supplied to the flip-flop 36 are the same.

Therefore, the LSI 22 and the flip-flop 36 can be operated in synchronization.

[0015]

There are manufacturing variations in the characteristics of the receiver 52 (or drivers 54 and 56) in the LSI 22 and the external driver 60, and these characteristics are temperature, voltage, current, and the like. (DL2 ≠ DL5), the clock delay amount on the LSI 22 side and the clock delay amount on the flip-flop 36 side do not exactly match.

Therefore, when the crystal oscillator 32 having a higher oscillation frequency is used to operate the LSI 22 and the flip-flop 36 at a higher speed, the skew between both clocks increases, and as a result, the LSI 22 and the flip-flop 36. The synchronous operation of 36 becomes difficult.

FIG. 4 illustrates the example. Here, the delay amounts DL1, DL2, DL3, DL4 are small and the delay amount DL5 is large, so that the flip-flop 36 side is the delay amount DLx from the clock cycle of the flip-flop 57. Signal is delayed, therefore LSI2
2. It becomes impossible to transfer data between the flip-flops 36 at high speed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method capable of operating a LSI and an external circuit at a higher speed with clock synchronization.

[0019]

In order to achieve the above object, the following adjustment method is adopted in the present invention.

In FIG. 1, a clock output pin 10 and
A pair of clock input pins 12 and 14, and a first clock path 18 from one clock input pin 12 to the clock inputs of flip-flops 57 and 58 of the LSI body,
The other clock input pin 14 to the clock output pin 10
And a second clock path 20 leading to.

Further, delay adjusting elements 24, 26, 28 and 30 are inserted in both clock paths 18 and 20, respectively.

The clock of the clock generation source 32 is supplied to the input pin 12 through the first delay adjusting external element 34, and is directly supplied to the input pin 14.

Further, the circuit 36 for synchronizing the clock transmitted from the clock output pin 10 with the LSI 22.
Are supplied via the second external element 38 for delay adjustment, and the first and second external elements 34, 38 for delay adjustment are housed in the same IC 40.

[0024]

For example, the delay adjusting external elements 34 and 38 corresponding to the receiver 52 and the driver 60 of FIG.
Can be used.

In the present invention, since the delay adjusting external elements 34 and 38 are housed in the IC 40, the characteristics of both are made uniform and the elements 34, 38 and 24, 26, 2 are provided.
It is possible to operate 8 and 30 under the same operating environment.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a clock adjusting system according to the present invention will be described below with reference to the drawings.

In FIG. 1, a clock output pin 10 and a pair of clock input pins 12 and 14 are provided in an LSI 22. Inside the LSI 22, the first clock input pin 12 extends to the circuit portion 16 of the LSI main body. 1
And a second clock path 20 from the other clock input pin 14 to the clock output pin 10.

A receiver 24 (delay amount = dl1), a driver 26 (delay amount = dl2), and a receiver 28 (delay amount = dl) are provided on both clock paths 18 and 20.
3) and the driver 30 (delay amount = dl4) are respectively inserted, and the total delay amounts (dl1 + dl2) and (dl3 + dl4) of the paths 18 and 20 are set to be the same.

The clock of the crystal oscillator 32 is supplied to the input pins 12 and 14, and the receiver 34 (delay amount = dl5) is inserted in the clock supply path on the pin 12 side.

Further, the clock sent from the clock output pin 10 is synchronized with the LSI 22 in the circuit 36.
It is supplied to (delay amount = DL10) via a driver 38 (delay amount = dl6), and the receiver 34 and the driver 38 are housed in the same IC 40.

Here, the delay amounts dl5 and dl6 of the receiver 34 and the driver 38 are set to be the same, and their characteristics are also uniform.

Therefore, the clock delay amount (dl1 + dl2 + dl5) on the LSI 22 side and the clock delay amount (dl3 + dl4 + dl) on the flip-flop 36 side.
6) is the same.

Moreover, the receiver 24 and the driver 26,
Since the receiver 28 and the driver 30 are housed in the LSI 22, and the receiver 34 and the driver 38 are housed in the IC 40, the clock delay amounts on the LSI 22 side and the flip-flop 36 side are always the same (actually, in spite of the environmental changes thereof). 2, the clock delay amount on the flip-flop 36 side may fluctuate slightly from the LSI 22 side due to the difference in the load on the receiver 34 and the driver 38).

Therefore, there is a margin of the amount DLx in FIG. 2, and as a result, the clock frequency is further increased and the LSI
22 and the flip-flop 38 can be operated at higher speed.

[0035]

As described above, according to the present invention, it is possible to supply a clock whose delay amount is exactly the same to the LSI and its external circuit regardless of the operating environment, so that they can be synchronously operated at a higher speed. It becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an embodiment.

FIG. 2 is a time chart explaining the operation of the embodiment.

FIG. 3 is a block diagram illustrating a conventional example.

FIG. 4 is a time chart for explaining the operation of the conventional example.

[Explanation of symbols]

 10 clock output pin 12, 14 clock input pin 16 circuit part of LSI body 18, 20 clock path 22 LSI 24 receiver 26 driver 28 receiver 30 driver 32 crystal oscillator 34 receiver 36 flip-flop 38 driver 40 IC 56 driver 57, 58 flip-flop 62 driver 64 gate 66 receiver 68 gate

Front Page Continuation (72) Inventor Nobuhiko Akasaka 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujishidori Co., Ltd. (56) References JP 61-288218 (JP, A) JP 63-273119 (JP) , A) JP 64-3720 (JP, A) JP 60-256827 (JP, A) JP 59-105123 (JP, A) JP 58-82323 (JP, A) JP 55-102032 (JP, A)

Claims (1)

(57) [Claims] 1. A clock output pin (10), a pair of clock input pins (12, 14), and a first clock input pin (12) to a circuit portion (16) of an LSI body.
Clock path (18) and the other clock input pin (1
The second clock path (20) extending from 4) to the clock output pin (10) is provided in the LSI (22), and the delay adjusting element (24, 20) is provided in both clock paths (18, 20).
26, 28, 30) are respectively inserted, and the clock of the clock generation source (32) is supplied to one input pin (12) via the first delay adjustment external element (34), and the clock generation source (32) is supplied. The second delay adjusting external element is provided to the circuit (36) in which the clock of (32) is directly supplied to the other input pin (14) and the clock sent from the clock output pin (10) is clock-synchronized with the LSI (22). (3
8), and the first and second delay adjusting external elements (34, 38) are housed in the same IC (40).