JP2566517B2 - Dynamic semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device, and more particularly to a dynamic random access memory formed by a MOS process.

[0002]

2. Description of the Related Art Generally, a dynamic random access memory (dynamic RAM) uses a memory cell composed of one transistor and one capacitor. In this case, the smaller the ratio of the bit line capacitance to the capacitor capacitance, the larger the potential change of the bit line at the time of data reading, the larger the input potential difference to the sense amplifier, and the more reliable the reading operation. However, as the capacity of the memory increases and the degree of integration increases, the size of the memory cell decreases, and the capacity of the capacitor decreases. On the other hand, since the number of memory cells connected to one bit line increases, the bit line becomes longer and the bit line capacitance tends to increase. For this reason, the ratio of the bit line capacitance to the capacitor capacitance becomes large, and there is a possibility that the read operation may not be performed reliably.

In order to solve this problem, a method of dividing one bit line into a plurality of blocks to reduce the ratio of the capacitor capacity to the bit line capacity has been attempted. Two examples of such attempts are described below.

FIG. 4 shows the ISSCC 84, digest,
278-279 of the Technical Papers
It is a figure which shows a part of structure of the conventional dynamic RAM shown by page. In FIG. 4, the bit line pair is BL1, / B
A so-called shared sense amplifier configuration is adopted in which a sense amplifier is divided into L1 and BL2, / BL2 and shared by each divided bit line pair. Note that the above-mentioned document describes a case where the memory cell transistor is a P-channel transistor, the sense amplifier is a P-channel transistor, and the restore circuit is an N-channel transistor. For simplification, the case where the conductivity types of these transistors are reversed is shown.

Referring to FIG. 4, a folded bit line (folded)
The bit line pairs forming the bit line) are divided bit lines BL1, BLN, BL2 and / BL1, / BL, respectively.
It is divided into N and / BL2. A sense amplifier SA is connected to the divided bit lines BLN and / BLN, a restore circuit RE1 is connected to the divided bit lines BL1 and / BL1, and a restore circuit RE2 is connected to the divided bit lines BL2 and / BL2. Sense amplifier SA
Is composed of N-channel transistors QN1 and QN2 as described above, and the restore circuits RE1 and RE2 are respectively connected to P-channel transistors QP1 and QP1.
It is composed of QP2, QP3 and QP4.

The sources of the transistors QN1 and QN2 are connected to a common sense amplifier driving transistor QN5. A sense amplifier activation signal SN is applied to the gate of the transistor QN5. The sources of the transistors QP1 and QP2 are connected to the common restore circuit drive transistor QP5, and the sources of the transistors QP3 and QP4 are connected to the common restore circuit drive transistor QP6. Restore circuit activation signals SP1 and SP2 are applied to the gates of these transistors QP5 and QP6, respectively.

Divided bit lines BL1 and BLN and BLN
And BL2 are connected via transfer gate transistors QT1 and QT3, respectively, and the divided bit lines / BL1 and / BLN and / BLN and / BL2 are connected via transfer gate transistors QT2 and QT4, respectively. The transfer signal T1 is applied to the gates of the transfer gate transistors QT1 and QT2, and the transfer signal T2 is applied to the gates of the transfer gate transistors QT3 and QT4.

Split bit lines BL1 and / BL1 are connected to bus lines BU and / BU via column gate transistors QY1 and QY2, respectively. A column selection signal Y is applied to the gates of the column gate transistors QY1 and QY2.

A plurality of memory cells are connected to each divided bit line in accordance with the memory capacity. Here, memory cell MC1 connected to divided bit line BL2 is representatively shown.
I will show only. The memory cell MC1 is composed of a capacitor CS and a transistor QS. The gate of the transistor QS constitutes a part of the word line WL1. Further, one electrode of the capacitor CS is connected to VSG.

Next, the operation of the circuit of FIG. 4 will be described with reference to the capacitor CS of the memory cell MC1 connected to the divided bit line BL2.
Will be described with reference to FIG. 5, which is an operation waveform diagram, in the case where is not charged, that is, the case where the information “0” is stored in the memory cell MC1.

At time t0, the transfer signal T1 becomes "L", and the divided bit lines BLN and BL1 and / B.
LN and / BL1 are separated, respectively. By this time, the divided bit lines BL1, / BL1, BL2, / BL
2, BLN, / BLN are precharged to an intermediate potential (Vcc-Vss) / 2 by means not shown.

At time t1, the selected word line W
When L1 becomes “H”, the transistor QS is turned on, the potential of the divided bit line BL2 is slightly lowered, and the divided bit line B
A potential difference occurs between L2 and / BL2.

At time t2, the sense amplifier activation signal S
L becomes "H", and the potential difference between the divided bit lines BL2 and / BL2 is enlarged. That is, divided bit line / B
The potential of L2 is maintained near the intermediate potential, but the potential of the divided bit line BL2 passes through the transfer gate transistor QT3 and the sense amplifier SA to the ground potential Vss.
It is discharged to near.

At time t3, the restore circuit activation signal SP2
Becomes "L", the potential of divided bit line / BL2 is raised to near the power supply potential Vcc, and the potential difference between divided bit lines BL2 and / BL2 is further expanded.

When transfer signal T1 becomes "H" again at time t4, the potentials of divided bit lines BLN and / BLN are transmitted to divided bit lines BL1 and / BL1. As a result, the potential of the divided bit line BL1 is the ground potential V
It is discharged to near ss and the potential of the divided bit line / BL1 is pulled up in reverse.

At time t5, the restore circuit activation signal SP1
Becomes "L", the potential of divided bit line / BL1 is pulled up to near power supply potential Vcc.

At time t6, the column selection signal Y becomes "H",
The potentials of the divided bit lines BL1 and / BL1 are the bus line BU.
Information "0" transmitted to and / BU and stored in memory cell MC1 is read.

As described above, the information stored in the capacitor CS of the memory cell MC1 is first stored in the divided bit line BL.
2 and the potential difference between the divided bit lines BL2 and / BL2 is amplified by the sense amplifier SA. At this time,
The potential of the divided bit line BL2 is discharged by the sense amplifier SA through the transfer gate transistor QT3. Usually, in a dynamic RAM having a folded bit line structure, the bit line is formed of a low resistance material such as aluminum or a silicide of a refractory metal. Therefore, the bit line resistance can be lowered, and the potential of the bit line can be discharged faster.

However, as described above, in the dynamic RAM having the shared sense amplifier structure, since the transfer gate transistor is inserted between the divided bit line to which the memory cell is connected and the sense amplifier, the transistor portion is made of a low resistance material. Bit line cannot be formed.

Further, as shown in FIG. 4, it is necessary to provide the transfer gate transistor for each pitch of the bit lines, and therefore, the transistor width can be made equal to the pitch of the bit lines or only about twice thereof.
Considering the bit line pitch, for example, in the case of a 1 Mbit dynamic RAM, the pitch is about 3 μm. For this reason,
The transistor width of the transfer gate transistor is limited to about several μm or less. Therefore, there is a problem in that the conductance of the transfer gate transistor becomes small and the discharge of the potential of the divided bit line is delayed during the operation of the sense amplifier.

Further, since the source and the drain of the transfer gate transistor are formed by the diffusion layer provided in the substrate or the well, noise through the substrate or the well is transmitted to the bit line, which causes malfunction of the sense amplifier. There was also a problem that it might cause it.

FIG. 6 is a diagram showing the configuration of another conventional example which is of interest to the present invention, for example, Japanese Patent Laid-Open No. 59-101093.
No. The circuit of FIG. 6 is composed of only N-channel transistors, and the bit line is divided into three.
An active pull-up circuit AP and a bit line precharge circuit BC are connected to the divided bit lines BL4 and / BL4. Transfer gate transistors QT1, QT2, QT3, QT4 are provided between the divided bit lines, and between the divided bit line BL4 and the bus line BU and between the divided bit line / BL4 and the bus line / BU. , Column gate transistors QY1 and QY, respectively.
2 are provided. Split bit lines BL5 and / BL
5, a sense amplifier SA5 is connected to the divided bit line B
A sense amplifier SA6 is connected to L6 and / BL6.

Further, each divided bit line is
Although a plurality of memory cells are connected, here, of the memory cells connected to each divided bit line, only the memory cell MC1 connected to the divided bit line BL5 is shown. The memory cell MC1 is composed of a capacitor CS and a transistor QS, and the gate of the transistor QS forms a part of the word line WL1. Capacitor C
One electrode of S is connected to the memory cell plate potential VSG.

Next, the operation of the circuit of FIG.
The state where the capacitor CS of 1 is not charged, that is, the case where the information “0” is stored in the memory cell MC1 will be described with reference to FIG. 7 which is an operation waveform diagram.

Before time t0, both transfer signal BSC and reset signal RST are at "H" level, and transfer gate transistors QT1, QT2, QT3 and QT4 are all on. Therefore, the divided bit lines BL4, BL5, BL
6 are connected to each other and divided bit lines / BL4, /
BL5 and / BL6 are also connected to each other.

When the reset signal RST becomes "H", the bit line precharge circuit BC operates and the potential of each divided bit line becomes the intermediate potential (Vcc-Vs).
s) / 2 is precharged.

At time t0, the transfer signal B
Both SC and reset signal RST become "L",
At time t1, the selected word line WL1 becomes “H”, the potential of the divided bit line BL5 slightly drops, and a potential difference occurs between the divided bit lines BL5 and / BL5.

At time t2, the sense amplifier activation signal SA5
Becomes "H", the sense amplifier SA5 operates to expand the potential difference between the divided bit lines BL5 and / BL5.

When the transfer signal BSC becomes "H" at time t3, the transfer gate transistor Q
T1, QT2, QT3 and QT4 are turned on, and the potentials of divided bit lines BL5 and / BL5 are changed to divided bit line B.
It is transmitted to L4, BL6 and / BL4, / BL6, respectively.

At time t4, the sense amplifier activation signal SN6
Becomes "H", the divided bit lines BL6 and / B
The potential difference between L6 and the divided bit lines BL4 and / BL4 and BL5 and / BL5 is also enlarged.

At time t5, the active pull-up signal AP
E becomes "H", the active pull-up circuit AP operates, and the divided bit lines / BL4, / BL5 and / BL6
Are both raised to near the power supply potential Vcc.

Then, column select signal Y attains "H", the potentials of divided bit lines BL4 and / BL4 are transmitted to bus lines BU and / BU, respectively, and information is read.

[0033]

As described above, in the circuit shown in FIG. 6, the sense amplifier is provided for each divided bit line, but the active pull-up circuit is provided for each divided bit line. However, only one active pull-up circuit is provided for the entire bit line. Therefore, when operating the active pull-up circuit, it is necessary to raise the potential of the entire bit line by one active pull-up circuit, which requires an active pull-up circuit having a large driving capability. Therefore, there is a problem that the area of the active pull-up circuit increases.

In order to raise each divided bit line potential to the power supply potential Vcc by the active pull-up circuit, the gate potential of the transfer gate transistor, that is, the transfer signal BSC is set to the power supply potential Vc.
It is necessary to boost the voltage above c. However, as the degree of integration of the memory increases, the gate oxide film of the transistor tends to become thinner. For example, in a 1M bit dynamic RAM, the gate oxide film is about 200 to 300 Å. Therefore, boosting the gate potential above the power supply potential causes a problem that the reliability of the gate oxide film is deteriorated.

The present invention has been made in order to solve the problems of the conventional dynamic RAM as described above, and can read information at high speed and stably, and the reliability of the gate oxide film can be improved. The purpose is to provide a high dynamic RAM.

[0036]

A dynamic RAM according to the present invention divides each bit line pair into a plurality of divided bit line pairs, and includes a transistor of a first conductivity type for each divided bit line pair. A restore circuit including a sense amplifier and a second conductivity type transistor is provided. Further, in the column selection, in response to the column selection signal, in the bit lines corresponding to the selected column, the column selection means configured by transistors of the first conductivity type for connecting the first divided bit line pair to the data bus, Between the pair of divided bit lines, connection element means each for connecting an adjacent divided bit line associated with one bit line are formed of transistors of the first conductivity type.

In the first divided bit line connected to the bus line at the time of selection in each bit line pair, a restore circuit is provided at the end near the column selecting means, and a sense amplifier is provided at the end near the connecting element means. It is provided.

[0038]

In the dynamic semiconductor memory device according to the present invention, since the sense amplifier and the restore circuit are provided for each divided bit line pair, the sensing operation can be performed at high speed and stably, and the gate voltage of the transfer gate transistor can be controlled. Since it is not necessary to boost the voltage above the power supply potential, the access time of the dynamic semiconductor memory device can be shortened, the operation margin is expanded, and the reliability is further improved.

In addition, since the sense amplifier is provided on the connection element side in the first divided bit line pair connected to the data bus line, the signal is transmitted from the adjacent divided bit line via this first divided bit line pair. Since the memory cell read data can be detected and amplified by the sense amplifier at high speed without the signal propagation delay in the bit line of the first divided bit line pair, accurate and high speed sense operation can be realized and sense operation can be performed. The margin expands. Furthermore, since the connection element and the sense amplifier are composed of transistors of the same conductivity type, these circuit elements can be formed in the same substrate region (well), and the circuit occupied area can be reduced. Further, since the restore circuit composed of the second conductivity type transistor is provided in the vicinity of the column selecting means, a threshold voltage loss occurs in the bus selecting means during data writing, and the data is transmitted onto the bit line. Even in this case, the restore circuit can surely operate at a high speed to accurately set the potential on the bit line pair to the potential level according to the write data.

[0040]

FIG. 1 is a circuit diagram showing a part of the structure of a dynamic RAM according to an embodiment of the present invention.

Referring to FIG. 1, the bit line pair having the folded bit line structure is, for example, BL1, / BL1 and BL2, /.
It is divided into two, BL2 and BL2. A sense amplifier SA1 and a restore circuit RE1 are connected to the divided bit lines BL1 and / BL1. The sense amplifier SA1 is composed of N-channel transistors QN1 and QN2, and the restore circuit RE1 is composed of P-channel transistors QP1 and QP2.

A sense amplifier SA2 and a restore circuit RE2 are connected to the divided bit lines BL2 and / BL2. The sense amplifier SA2 is composed of N-channel transistors QN3 and QN4, and the restore circuit RE2 is composed of P-channel transistors QP3 and QP4.
It consists of.

The sources of the transistors QN1 and QN2 forming the sense amplifier SA1 are connected to a common sense amplifier drive transistor QN5, and the sense amplifier SA2 is used.
The sources of the transistors QN3 and QN4 configuring the above are connected to a common sense amplifier driving transistor QN6. The gates of these transistors QN5 and QN6 respectively have a sense amplifier activation signal SN1.
And SN2 are provided.

The sources of the transistors QP1 and QP2 constituting the restore circuit RE1 are connected to the common restore circuit drive transistor QP5, and the restore circuit RE2 is used.
The sources of the transistors QP3 and QP4 constituting the above are connected to a common restore circuit drive transistor QP6. Restore circuit activation signals SP1 and SP2 are applied to the gates of these transistors QP5 and QP6, respectively.

Divided bit lines BL1 and BL2 and / BL
1 and / BL2 are connected via transfer gate transistors QT1 and QT2, respectively, and the gates of both transistors QT1 and QT2 are
The transfer signal T is provided.

Split bit line BL1 and bus line BU, and split bit line / BL1 and bus line / BU are connected through column gate transistors QY1 and QY2, respectively. The column selection signal Y is applied to the gates of the transistors QY1 and QY2.

A plurality of memory cells are connected to each divided bit line in accordance with the memory capacity. Here, memory cell MC1 connected to divided bit line BL2 is representatively shown.
Shows only. The memory cell MC1 is a capacitor CS
And a transistor QS. The gate of the transistor QS constitutes a part of the word line WL1. Further, one electrode of the capacitor CS is connected to the memory cell plate electrode VSG.

Next, the operation of the circuit shown in FIG. 1 will be described. Here, first, the state where the capacitor CS of the memory cell MC1 is not charged, that is, the information “0” is stored in the memory cell M1.
The case of being stored in C1 will be described with reference to the operation waveform diagram of FIG.

Before time t0, the divided bit line BL
1, / BL1, BL2, / BL2 are precharged to an intermediate potential (Vcc-Vss) / 2 by means not shown, and the transfer signal T is "L".

When the word line WL1 selected at the time t0 becomes "H", the transistor QS is turned on and the potential of the divided bit line BL2 is slightly lowered, so that a potential difference is generated between the divided bit lines BL2 and / BL2.

At time t1, the sense amplifier activation signal SN2
Becomes "H", the potential difference between the divided bit lines BL2 and / BL2 is enlarged. That is, divided bit line / B
The potential of L2 is maintained near the intermediate potential, but the potential of the divided bit line BL2 is discharged to near the ground potential Vss through the sense amplifier SA2.

At time t2, restore circuit activation signal SP2
Becomes "L", the potential of the divided bit line / BL2 is raised to near the power supply potential Vcc through the restore circuit RE2, and the potential difference between the divided bit lines BL2 and / BL2 is further expanded.

At time t3, the transfer signal T is "H".
Then, the potentials of divided bit lines BL2 and / BL2 are transmitted to divided bit lines BL1 and / BL1. At this time, the potential of divided bit line BL1 begins to be discharged through transfer gate transistor QT1 and sense amplifier SA2, and the potential of divided bit line / BL1 begins to be raised from the intermediate potential through transfer gate transistor QT2 and restore circuit RE2.

At time t4, the sense amplifier activation signal SN1
Becomes "H", the sense amplifier SA1 operates to discharge the potential of the divided bit line BL1 to near the ground potential Vss.

At time t5, the restore circuit activation signal SP1
Becomes "L", the restore circuit RE1 operates to raise the potential of the divided bit line / BL1 to near the power supply potential Vcc.

Next, at time t6, the column selection signal Y becomes "H", the column gate transistors QY1 and QY2 are turned on, and the potentials of the divided bit lines BL1 and / BL1 are changed to the bus lines BU and / BU, respectively. Then, the information "0" stored in memory cell MC1 is read.

Next, the capacitor CS of the memory cell MC1
The state in which is charged, that is, the case where the information "1" is stored in the memory cell MC1 will be described with reference to FIG. 3 which is an operation waveform diagram.

The precharge of the divided bit lines and the operation of setting the transfer signal T to "L" are performed in the same manner as in the case where the information stored in the memory cell MC1 described above is "0".

At time t0, the selected word line W
When L1 becomes “H”, the transistor QS is turned on, the potential of the divided bit line BL2 rises a little, and the divided bit line B
A potential difference occurs between L2 and / BL2.

At time t1, sense amplifier activation signal SN2
Becomes "H", the potential difference between the divided bit lines BL2 and / BL2 is enlarged. That is, the divided bit line BL
The potential of 1 is kept a little higher than the intermediate potential, but the potential of the divided bit line / BL2 is the sense amplifier SA2.
Is discharged to near ground potential Vss.

At time t2, restore circuit activation signal SP2
Becomes "L", the potential of the divided bit line BL2 is raised to near the power supply potential Vcc through the restore circuit RE2, and the potential difference between the divided bit lines BL2 and / BL2 is further expanded.

At time t3, the transfer signal T becomes "H".
Then, the potentials of divided bit lines BL2 and / BL2 are transmitted to divided bit lines BL1 and / BL1, respectively. At this time, the potential of divided bit line / BL1 starts to be discharged through transfer gate transistor QT2 and sense amplifier SA2, and divided bit line BL1
Starts to be pulled up through the transfer gate transistor QT1 and the restore circuit RE2.

At time t4, the sense amplifier activation signal SN1
Becomes "H", the potential of the divided bit line / BL1 is discharged to near the ground potential Vss.

At time t5, the restore circuit activation signal SP1
Becomes "L", the potential of the divided bit line BL1 is raised to near the power supply potential Vcc.

Next, at time t6, the column selection signal Y becomes "H", and the information "1" is read onto the bus lines BU and / BU.

The configuration and operation of the preferred embodiment of the present invention have been described above in detail. In the circuit shown in FIG. 1, the restore circuit RE2 is added to the sense amplifier SA2.
However, the restore circuit RE is added to the sense amplifier SA1.
1 are provided separately from each other with a memory area. That is, the sense amplifier and the restore circuit are provided at one end and the other end of the divided bit line pair, respectively. As a result, CMOS (complementary MO
S) It is possible to reliably suppress the latch-up that tends to occur in the circuit.

In addition to this, the restore circuit RE2 is activated for the sense amplifier SA2 and the restore circuit RE1 is activated for the sense amplifier SA1 at different timings. The peak value of the current flowing toward the ground Vss via the sense amplifier can be reduced.

By reducing the peak current, the generation of noise can be suppressed and the latch-up can be prevented. At the same time, the operating margin of this dynamic RAM can be improved.

Furthermore, transfer gate transistors QT1 and QT are connected to bit lines BL1 and / BL1 connected to bus lines BU and / BU when selected.
A sense amplifier SA1 is provided at the end on the T2 side.
Therefore, when the selected memory cell data read onto bit lines BL2 and / BL2 is transmitted to bus lines BU and / BU, transfer gate transistors QT1 and QT2 are transmitted.
The sense amplifier SA1 can be activated immediately after the switch is turned on. This is because the signal line distance between the sense amplifier SA1 and the transfer gate transistor is extremely short, and signal propagation delay and change in signal potential do not occur.

In the above embodiment, the sense amplifier composed of N-channel transistors is operated first, and then the restore circuit composed of P-channel transistors is operated. However, this operation sequence is different. It can also be ordered. For example, it is possible to operate both the sense amplifier and the restore circuit at the same time, or it is possible to operate the sense amplifier after operating the restore circuit, even if the sense amplifier and the restore circuit are operated at different timings. The effects obtained by the present invention are not different.

In the above embodiment, the transfer gate transistor and the column gate transistor are N-channel transistors.
The transistors may have opposite conductivity types. In that case, the signal potential applied to the gate of each transistor may be appropriately selected.

Furthermore, in the above embodiment, the case where the memory cell transistor is an N-channel transistor has been described, but the memory cell transistor is configured by a P-channel transistor by appropriately selecting the potential of the word line. You can also

[0073]

As described above, according to the present invention, in a divided bit line pair provided with a sense amplifier and a restore circuit for each divided bit line pair and connected to the bus line at the time of selection, the divided bit line pair is provided. Since a sense amplifier is provided at the end of the transfer gate transistor for connection and a restore circuit is provided at the other end, it is possible to reliably prevent the latch-up phenomenon from occurring, and sense without causing signal propagation delay. The operation can be executed accurately, information can be read at high speed and stably,
Dynamic R with fast access time and wide operation margin
There is an effect that AM can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of a configuration of a dynamic RAM which is an embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing a part of the operation of the circuit of FIG.

FIG. 3 is a signal waveform diagram showing a part of the operation of the circuit of FIG.

FIG. 4 is a circuit diagram showing a part of the configuration of an example of a conventional dynamic RAM.

5 is a signal waveform diagram showing a part of the operation of the circuit of FIG.

FIG. 6 is a circuit diagram showing a part of another configuration of a conventional dynamic RAM.

7 is a signal waveform diagram showing a part of the operation of the circuit of FIG.

[Explanation of symbols]

 MC1 memory cell WL1 word line BL1 divided bit line / BL1 divided bit line BL2 divided bit line / BL2 divided bit line QT1 transfer gate transistor QT2 transfer gate transistor SA1 sense amplifier SA2 sense amplifier QN1 to QN4 transistor constituting a sense amplifier RE1 restore circuit RE2 restore circuit QP1 to QP4 transistors forming the restore circuit QY1 column gate transistor QY2 column gate transistor

Claims (8)

(57) [Claims] 1. A plurality of memory cells arranged in a plurality of rows and columns, a plurality of word lines arranged corresponding to the plurality of rows and connected to memory cells in a corresponding row, respectively. A plurality of bit line pairs arranged corresponding to a plurality of columns, each of which is connected to a memory cell of a corresponding column and each of which is divided into a plurality of divided bit line pairs; A transistor of the first conductivity type for connecting the first divided bit line pair of the plurality of divided bit line pairs of the corresponding bit line pair to the bus line in response to the column selection signal. a column selecting circuit configured in, in the plurality of rows each, provided between the divided bit line pairs adjacent of the plurality of divided bit line pairs, for connecting the adjacent divided bit line pairs, are each First conductivity type tiger
Connecting element means composed of a transistor, and one of the plurality of divided bit line pairs, which is provided in each of the divided bit line pairs and sets one divided bit line of the corresponding divided bit line pair to a first potential when activated. A plurality of sense amplifier means each composed of a transistor of one conductivity type and a plurality of divided bit line pairs provided in each of the plurality of divided bit line pairs, and the other divided bit line of the corresponding divided bit line pair is set to the second potential when activated A plurality of restore means each of which is configured by a second conductivity type transistor, and the sense amplifier means is provided at an end of the corresponding connection means in the first divided bit line pair in each of the plurality of columns. A dynamic semiconductor memory device which is arranged and a restoring means is arranged at an end of the column selecting means. 2. The sense amplifier means and the restore means in each of the plurality of divided bit line pairs except the first divided bit line pair are arranged so as to face each other at both ends thereof. Dynamic semiconductor memory device. 3. When a selected memory cell is connected to a second divided bit line pair different from the first divided bit line pair in each column, the sense amplifier means in the second divided bit line pair is activated. First activating means for activating the corresponding restoring means and then activating the sense amplifier means by the first activating means when the selected memory cell is connected to the second divided bit line pair. Second activating means for bringing the connecting element means provided between the second divided bit line pair and the first divided bit line pair into a conductive state after activation, and the second divided bit. When the selected memory cell is connected to the line pair, the sense amplifier means in the first divided bit line pair is activated after the connection element means is set to the conductive state by the second activation means, and then the corresponding restore means is activated. Activate Further comprising a third activating means, according to claim 1
Alternatively, the dynamic semiconductor memory device described in 2. 4. The connection element means comprises a transfer gate using a transistor.
5. The dynamic semiconductor memory device according to any one of 3 to 3. 5. The first activating means for activating the sense amplifier means and the restoring means in each of the first pair of divided bit lines, and the sense amplifier means of the first activating means. 2. The dynamic semiconductor memory device according to claim 1, further comprising second activating means for activating said column selecting means after activation. 6. The dynamic semiconductor memory according to claim 3, wherein said second activating means includes means for bringing said connecting element means into a conductive state after activating said restoring means by said first activating means. apparatus. 7. The dynamic semiconductor memory device according to claim 1, further comprising means for activating corresponding sense amplifier means and corresponding restore means at different timings in each of the plurality of divided bit line pairs. 8. The dynamic semiconductor memory according to claim 5, wherein said second activating means includes means for activating said column selection signal after activating said restoring means by said first activating means. apparatus.