JP2565236B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device suitable for use in a single-plate color camera.

[Outline of Invention]

The present invention is a solid-state imaging device suitable for use in a single-plate color camera, in which 2m × 2n light-receiving elements and n columns of vertical transfer units are provided on a semiconductor substrate in a matrix, and these vertical transfer units are also provided. At one end and the other end of the first, second and third, respectively
By providing the fourth horizontal transfer section, so-called 4-line simultaneous all-pixel reading is performed, and the signal processing circuit can be simplified.

[Conventional technology]

2. Description of the Related Art Conventionally, there is a solid-state imaging device that employs a so-called interline transfer system as a solid-state imaging device used in a single-plate color camera. On the one hand, the solid-state imaging device adopting such an interline transfer method has an advantage of low noise, but on the other hand, the saturation charge amount of the vertical transfer unit is small, and thus a high dynamic range can be obtained. It had the disadvantage that it could not be done. In this case, it is conceivable to increase the dynamic range by increasing the area of the vertical transfer section. However, in this case, the aperture ratio of the light receiving element is reduced, and the solid-state imaging device is downsized and has high resolution. There was an inconvenience that it could not be achieved.

Therefore, in recent years, as a solid-state imaging device that eliminates such inconvenience, a solid-state imaging device (image sensor with a charge sweep device) using a so-called charge sweeping method has been proposed (Technical Report of the Television Society, February 1985). Issued on 27th, Vol.18, No.44, TEBS1010-6, ED841).

In this solid-state imaging device, the vertical transfer section is composed of a charge sweep device, and the vertical transfer section is used as one large potential well to read out only the signal charges accumulated in a single light receiving element. It was done like this.

According to such a solid-state imaging device, a large amount of signal can be transferred even when the channel width of the charge sweeping element constituting the vertical transfer unit is narrowed. Can be achieved.

[Problems to be solved by the invention]

However, in such a conventional solid-state imaging device using a charge sweeping element, it is not possible to read out the signal charges for each horizontal line, and therefore, a signal processing circuit for forming a composite video signal is used. There was an inconvenience that it became complicated.

In view of such a point, an object of the present invention is to provide a solid-state imaging device capable of performing 4-line simultaneous all-pixel reading to obtain high resolution and simplifying a signal processing circuit.

[Means for solving problems]

A solid-state imaging device according to the invention, as shown in FIG. 1-FIG. 8 for example, on a semiconductor substrate (1), a light receiving element (2 ₁ provided 504 × 760 pieces matrix in the vertical and horizontal directions _{, 1} ~
2 _504,760 ) and light receiving elements (2 _1,1 to 2 _504,760 ) provided for each row, and these light receiving elements (2 _1,1 to 2 _504,760 )
Vertical transfer units (3 _{1 to} 3 ₇₆₀ ) for vertically transferring the signal charges obtained in the above, and the vertical transfer units (3 _{1 to} 3 ₇₆₀ ) are provided at one end and the other end of the vertical transfer units (3 _{1 to} 3 ₇₆₀ ), respectively. ₁ ~
3 ₇₆₀ ) to transfer the signal charges transferred in the horizontal direction, first, second and third and fourth horizontal transfer sections (4 ₁ ),
(4 ₂ ), (4 ₃ ), and (4 ₄ ), and the first, second, third, and fourth horizontal transfer units (4 ₁ ), (4 ₂ ), and (4 ₃ ),
The first, second, third, and fourth provided on the output side of (4 ₄ )
Signal charge detecting section (5 _1), (5 ₂₎ and _{(3), (4)} and has, in each horizontal period, the 2j-1 (where, j = 1, 2,
... 252) The signal charges of the horizontal line and the 2j-th horizontal line are read to the vertical transfer unit (3 _{1 to} 3 ₇₆₀ ), and the 1st, 3rd, ... 759 The signal charge of the vertical line is transferred to the first horizontal transfer section (4 ₁ ) and the second j
-1st, 2nd, 4th, ...
760 The signal charge of the vertical line is transferred to the second horizontal transfer unit (4 ₂ ), and the first, third, and
... to transfer signal charges of the 759 vertical lines third horizontal transfer portion (4 _3), the second of the signal charges of the first 2j horizontal line, the fourth, the ... # 760 vertical line signal charges Is transferred to the fourth horizontal transfer section (4 ₄ ).

[Action]

According to the present invention, the first horizontal transfer unit (4 ₁ ) has the
Of the signal charges of 2j-1 horizontal line, the first, third, ...
The signal charges of the 759th vertical line are transferred, and the signal charges of the 2nd, 4th, ... 760th vertical lines among the signal charges of the 2j−1th horizontal line are transferred to the 2nd horizontal transfer unit (4 ₂ ). The signal charges of the first, third, ... 759th vertical lines of the signal charges of the 2j-th horizontal line are transferred to the third horizontal transfer unit (4 ₃ ), and are transferred to the fourth horizontal transfer unit (4 The signal charges of the second, fourth, ... 760th vertical lines among the signal charges of the 2j-th horizontal line are transferred to ( ₄ ), so that, as a color filter array, for example, as shown in FIG. 2j-1 row, 2k-1
W (white), 2nd in a row (however, k = 1,2, ... 380)
Color formed by arranging Cy (cyan) at the j-1th row, the 2kth column, G (green) at the 2jth row, the G (green) at the 2k-1th column, and the Ye (yellow) filter at the 2jth row and the 2kth column. When the filter array (6) is provided, a W signal is obtained at the first signal charge detection unit (4 ₁ ) and a Cy signal is obtained at the second signal charge detection unit (4 ₂ ).
The G signal is obtained at the third signal charge detection unit (4 ₃ ), and the Ye signal is obtained at the fourth signal charge detection unit (4 ₄ ).

As described above, according to the present invention, it is possible to perform 4-line simultaneous all-pixel readout and simultaneously read out, for example, four colors of W, Cy, G, and Ye. Therefore, a signal processing circuit for obtaining a composite video signal is provided. It can be simplified.

〔Example〕

An embodiment of the solid-state image pickup device of the present invention will be described below with reference to FIGS.

FIG. 1 is a schematic plan view showing the main part of the solid-state imaging device of this example. In FIG. 1, (1) shows a P-type silicon substrate in which P-type impurities are diffused relatively thinly. ,
In this example, light receiving elements (2 _1,1 to 2 _504,760 ) composed of 504 (vertical) × 760 (horizontal) photodiodes are provided on the surface side of the P-type silicon substrate (1).

In addition, the second element is _placed on these light receiving elements (2 _1,1 to 2 _504,760 ).
The color filter array (6) shown is arranged. This color filter array (6) has a W in the 2j−1th row, a 2k−1th column, a 2j−1th row, a Cy in the 2kth column, a 2jth row, a G in the 2k−1th row, and a 2jth row. , 2k 2 by placing Ye color filters in the 2nd row
A pixel is a basic unit.

Further, a vertical transfer section (3 _{1 to} 3 ₇₆₀ ) is provided for each column of the light receiving elements (2 _{1,1 to} 2 _504,760 ) via a signal charge reading gate section (7 _{1,1 to} 7 _504,760 ). As shown in FIG. 3, these vertical transfer sections (3 _{1 to} 3 ₇₆₀ ) are composed of charge sweeping elements composed of transfer electrode arrays. That together with the P- type silicon substrate (1) providing a N-type region (8 _{1-8 760)} forming the signal charge transfer path on the surface side of, made of SiO ₂ on the N-type region (8 _{1-8 760)} Through the insulating layer (9)
It is configured by providing ₅₀₄ transfer electrodes g _{1 to} g ₅₀₄ . These transfer electrodes g ₁ to g _504, respectively the vertical transfer section (3 ₁ -
3 in common across ₇₆₀₎ and 1 1 electrode provided so as to correspond to the light receiving element, these transfer electrodes g ₁ to g ₇₆₀ vertical scanning signal phi _V1 is shown in Figure 6 for example, to [phi] _V504 Is supplied. The transfer electrodes g _{1 to} g ₅₀₄ are _{designed to also serve as} the read gate electrodes of the signal charge read gate sections (7 _{1,1 to} 7 _1,760 ) to (7 _{504,1 to} 7 _504,760 ). g ₁ is the to g ₅₀₄ addition of the above-mentioned vertical scanning signal φ _V1 ~φ _V504, the signal charge reading pulse phi _ROG supplied.

In addition FIG. 1, (10) the vertical transfer section (3 ₁ -
3 ₇₆₀₎ shows the vertical transfer driving circuit for driving, the vertical transfer drive circuit (10) has, for example, a 504 output pins for outputting a vertical scanning signal φ _V1 ~φ _V504 shown in Figure 6 , These 504 output terminals are respectively connected to the vertical transfer unit (3 _{1 to} 3
₇₆₀ ) corresponding transfer electrodes g _{1 to} g ₅₀₄ , respectively.

Further, (11) is a signal charge read gate section (7 _{1,1 to} 7).
_504,760 ) is a line address shift register that supplies a signal charge read pulse φ _ROG to this line
The address shift register (11) has 504 output terminals, and these output terminals are respectively transfer electrodes g _{1 to} g.
Connected to the ₅₀₄ . This signal charge readout pulse φ _{ROG
Has a} voltage value V _T higher than the high level voltage V _H of the vertical scanning signal as shown in FIG. 6, and this signal charge read pulse φ _{ROG is applied} to the signal charge read gate section (7 _1,1 to 7
_504,760 ), the light receiving element (2 _1,1 ~ 2
_504,760 ) and the signal charge accumulated in the vertical transfer path (3 _{1 to} 3
₇₆₀ ) can be read. In this case, the signal charge read pulse φ _ROG is supplied during the horizontal blanking period.

In this embodiment also, as shown in FIG. 1, a memory unit (12 ₁ to 12 ₇₆₀₎ at one end of the vertical transfer section (3 ₁ to 3 _760), a first vertical readout gate unit (13 _1), First horizontal transfer unit (4
₁ ), a second vertical read gate section (13 ₂ ) and a second horizontal transfer section (4 ₂ ) are sequentially provided.

Here, the memory section (12 _{1 to} 12 ₇₆₀ ) forms a memory gate area following the N-type area (8 ₁ to 8 ₇₆₀ ) of the vertical transfer section (3 _{1 to} 3 ₇₆₀ ) as shown in FIG. N ^- type region (14 _{1 to} 14 ₇₆₀ )
And an N-type region (15 ₁ to 15 ₇₆₀ ) forming a memory region, and an insulating layer (9) on the N ^- type region (14 _{1 to} 14 ₇₆₀ ) and the N-type region (15 ₁ to 15 ₇₆₀ ). A memory control electrode g _MC1 is provided via the memory control electrode g _MC1 . These electrodes g
_MC1 is supplied with the memory control signal phi _MC1 shown in Figure 6 for example.

The first vertical read gate section (13 ₁ ) is provided with N-type areas (16 _{1 to} 16 ₇₆₀ ) following the N-type areas (15 ₁ to 15 ₇₆₀ ) of the memory section (12 _{1 to} 12 ₇₆₀ ). It is configured to provide a vertical readout gate electrode (g _Vog1) through these N-type regions (16 ₁ to 16 ₇₆₀₎ insulating layer on (9). The first vertical read gate signal φ _VOG1 shown in FIG. 6 is supplied to the vertical read gate electrode (g _VOG1 ).

As shown in FIG. 4, the _first horizontal transfer section (4 ₁ ) has an N-type area (17) extending in the horizontal direction as a gate area (16) of the first vertical read gate section (13 ₁ ). _{1 to} 16 ₇₆₀ ), the N-type region (17) is used as a signal charge transfer region, and the transfer electrode (18T ₁ ) is provided on the N-type region (17) through the insulative layer (9). , Storage electrode (18
S ₁ ), a transfer electrode (18T ₂ ) and a storage electrode (18S ₂ ) are provided. Well-known two-phase drive pulses φ _H1 and φ _H2 are supplied to the transfer electrode (18T ₁ ), the storage electrode (18S ₁ ), the transfer electrode (18T ₂ ) and the storage electrode (18S ₂ ). In this example, the N-type impurity concentration of the N-type regions (17) below the transfer electrodes (18T ₁ ) and (18T ₂ ) is equal to the N-type regions below the storage electrodes (18S ₁ ) and (18S ₂ ). The transfer electrode (18) is made thinner than the N-type impurity concentration of (17).
The N-type regions below T ₁ ) and (18T ₂ ) are transfer regions (17T ₁ ) and (17T ₂ ), and the N-type regions below the storage electrodes (18S ₁ ) and (18S ₂ ) are storage regions (17S _1). ) And (17S ₂ ).

The second horizontal transfer section (4 ₂₎ is parallel to the N-type region of the first horizontal transfer section (4 ₁₎ (17), N-type region of the first horizontal transfer portion the (4 ₁₎ An N-type region (19) similar to that of (17) is provided, and a transfer electrode (20T ₁ ) and a storage electrode (20) are provided on the N-type region (19) via an insulating layer (9).
S ₁ ), a transfer electrode (20T ₂ ) and a storage electrode (20S ₂ ) are provided. In this example, the transfer electrode (20T ₁ ) and the storage electrode (20T ₁ )
S ₁ ), transfer electrode (20T ₂ ) and storage electrode (20S ₂ ) are integrated with the transfer electrode (18T ₁ ), storage electrode (18S ₁ ), transfer electrode (18T ₂ ), and storage electrode (18S ₂ ), respectively. Has been formed. The N-type impurity concentration of the N-type region (19) below the transfer electrodes (20T ₁ ) and (20T ₂ ) is the same as that of the N-type region (19) below the storage electrodes (20S ₁ ) and (20S ₂ ). The transfer electrodes (20T ₁ ) and (20T ₂ ) are made thinner than the impurity concentration.
The lower N-type region is the transfer region (19T ₁ ) and (19T ₁ )
T ₂ ), the storage electrode (20S ₁ ) and N below (20S ₂ )
The mold areas are adapted to be the storage areas (19S ₁ ) and (19S ₂ ).

The second vertical read gate section (13 ₂ ) is connected to the second, fourth ... 760th gate regions (16 ₂ , 16 ₄ ... 16 ₇₆₀ ) of the first vertical read gate section (13 ₁ ). the first horizontal transfer section (4 ₁₎ of the storage space (17S ₁₎ second horizontal transfer portion of the front half-bit storage region of the first horizontal transfer portion of Toko (4 ₁₎ (17S ₁₎ which is ( 4 ₂ ) is connected to the storage area (19S ₂ ) by an N-type area (21), and this N-type area (21) is used as a gate area. In areas other than this area, P-type impurities are diffused to stop the channel. Area (22) and
These N-type region (21) and channel stop region (22)
A vertical read gate electrode g _VOG2 is provided on the top.

Further, in this example, as shown in FIGS. 1, 3, and 5, the memory section (23 ₁ to 23 ₇₆₀ ) and the third section are provided on the other end side of the vertical transfer section (3 _{1 to} 3 ₇₆₀ ). Vertical read gate section (13 ₃ ),
The third horizontal transfer section (4 ₃ ), the fourth vertical read gate section (13 ₄ ) and the fourth horizontal transfer section (4 ₄ ) are connected to the vertical transfer section (3 ₄ ).
_{1 to} 3 ₇₆₀ ) memory part (12 ₁ to _{1 760} )
2 ₇₆₀ ), a first vertical read gate section (13 ₁ ), a first horizontal transfer section (4 ₁ ), a second vertical read gate section (13 ₂ ), and a second horizontal transfer section (4 ₂ ). It is provided symmetrically.
Note that in FIG. 3, (24 _{1-24 760)} a memory unit (23 ₁
~ 23 ₇₆₀ ) N ^- type region that forms the memory gate region, (25 ₁ ~
25 ₇₆₀₎ is N-type region forming the memory area, (g _MC2) memory control electrodes, (26 ₁ to 26 ₇₆₀₎ is read gate region of the third vertical readout gate unit (13 _3), g _VOG3 vertical read It is a gate electrode. Further, in FIG. 5, (27) is an N-type area forming the signal charge transfer path of the third horizontal transfer section (4 ₃ ), (27S ₁ ) and (27S ₂ ) are storage areas, and (27S ₁ )
T ₁ ) and (27T ₂ ) are transfer areas, (28S ₁ ) and (28S ₂ ) are storage electrodes, and (28T ₁ ) and (28T ₂ ) are storage electrodes.
T ₂ ) is a transfer electrode, (29) is an N-type region forming a signal charge transfer path of the fourth horizontal transfer section (4 ₄ ), (29S ₁ ) and (29S ₂ ) are storage regions, and (29T ₁ ) And (29
T ₂ ) is a transfer area, (30S ₁ ) and (30S ₂ ) are storage electrodes, (30T ₁ ) and (30T ₂ ) are transfer electrodes, and (31) is a fourth vertical read gate section (13).
₄ ) gate region, (32) channel stop region, g
_VOG4 is a vertical read gate electrode.

Further, in this example, the signal charge detecting unit (5) is provided on the output side of the first, second, third and fourth horizontal transfer units (4 ₁ ), (4 ₂ ), (4 ₃ ) and (4 ₄ ). _1), (5 _2), it is provided with ₍₃₎ and _(4). These signal charge detectors (5 ₁ ), (5 ₂ ),
(5 ₃ ) and (5 ₄ ) are composed of a floating diffusion amplifier and are transferred by the horizontal transfer sections (4 ₁ ), (4 ₂ ), (4 ₃ ) and (4 ₄ ). The incoming signal charge is detected and this signal charge is converted into an electrical video signal. In addition, (33 ₁ ), (3
3 ₂ ), (33 ₃ ) and (33 ₄ ) are output terminals for outputting a video signal.

Next, with reference to FIGS. 6 to 8, the operation of the solid-state imaging device of the example of FIG. 1 will be described by taking the operation in the j-th horizontal period as an example.

Figure 6 is a vertical transfer unit in the j-th horizontal period (3 ₁ to 3
₇₆₀ ) gate electrodes g _{1 to} g ₅₀₄ for vertical scanning signals φ _{V1 to} φ _V504 , memory control signals φ _MC1 , φ _MC2 ,
Vertical read gate signal φ _VOG1 , φ _VOG2 , φ _VOG3 , φ
_VOG4 and horizontal drive pulses phi _H1, indicates phi _H2, FIG. 7 is a vertical transfer section (3 ₁₎ signal transfer unit _(81), a memory unit (12 ₁₎
Memory gate area (14 ₁ ) and memory area (15 ₁ ), the vertical read gate area (16 ₁ ) of the first vertical read gate section (13 ₁ ), and the memory gate area (24 _{1 of the} memory section (23 ₁ ). ), The memory region (25 ₁ ), and the potential change in the vertical read gate region (26 ₁ ) of the third vertical read gate portion (13 ₃ ).

First, in the j-th horizontal period, at T = t ₁ in FIG. 6, a high level voltage is supplied to the electrodes g _MC1 and g _MC2 of the memory units (12 ₁ ) and (23 ₁ ), and these memory units (12 ₁ ) And (23 ₁ ) are turned on, and the potential of the vertical transfer section (3 ₁ ) becomes as shown in FIG. 7A.

Next, at T = t ₂ , a high level voltage is supplied to the transfer electrodes g _2j and g ₇₆₀ and a read pulse φ _ROG is supplied to the transfer electrode g _2j, and the potential of the vertical transfer portion (3 ₁ ) is shown in FIG. As shown in B. At this time, the signal charge Q _{2j, 1} accumulated in the light receiving element (2 _{2j, 1} ) is read out to the potential well formed below the transfer electrode g _2j .

Next, at T = t ₃ , the transfer electrode g _2j is set to the low level, and the signal charge Q _{2j, 1} read to the potential well formed below the transfer electrode g _2j is as shown in FIG. 7C. , To the potential well side formed below the transfer electrode g _{2j + 1} .

After that, at T = t ₄ , the transfer electrode g _{2j + 1} is at low level, and T = t
_{At 5} , the transfer electrode g _{2j + 2} is at low level, ... At T = t ₈ , the transfer electrode g ₅₀₃ is at low level, at T = t ₉ , the transfer electrode g ₅₀₄ is at low level, and the signal charge Q _{2j, 1} is 7D, 7E and 7D
After the process shown in FIGS. H and 7I, at T = t ₁₀ , the data is completely stored in the memory area (25 ₁ ) as shown in FIG. 7J.

Incidentally, it is supplied read pulse phi _ROG transfer electrodes g _2j-1 with a high level voltage is supplied to the T = t ₄ transfer electrodes g _2j-1 to g ₁ described above, the vertical transfer section (3 ₁₎ The potential is as shown in FIG. 7D. At this time, the signal charges Q _2j-1,1 accumulated in the light receiving element (2 _2j-1,1 ) are read out to the potential well formed below the transfer electrode g _2j-1 .

Then T = t ₅ at the transfer electrodes g _2j-1 is set to the low level and the transfer electrode g _2j-1 of the signal charge read out to the potential well formed under Q _{2j-1, 1,} the seventh As shown in FIG. E, the transfer electrode is moved to the potential well side formed below the transfer electrode g _2j-2 .

After that, at T = t ₆ , the transfer electrode g _2j-2 is at low level, and T = t
₇ the transfer electrodes g _2j-3 is a low level, the transfer electrodes g ₂ is low in ··· T = t _10, the transfer electrodes g ₁ at T = t ₁₁ becomes the low level, the signal charge Q _{2j-1, 1} Is stored in the memory area (15 ₁ ) as shown in FIG. 7K through the processes shown in FIGS. 7F, 7G and 7J.

Then, at T = t ₁₂ , the vertical read gate sections (13 ₁ ) and (13 ₃ ) are turned on, and the memory areas (15 ₁ ) and (25
_The signal charges Q _2j-1,1 and Q _{2j, 1} accumulated in ₁ ) are shown in FIG.
It is transferred to the storage area of the storage region of the first horizontal transfer portion, respectively (4 ₁₎ as shown in (17S ₁₎ and the third horizontal transfer unit (4 ₃₎ (27S _1), memory T = t ₁₃ Parts (12 ₁ ) and (23 ₁ ) are turned off, the potential state becomes as shown in FIG. 7M, and subsequently, at T = t ₁₅ , the first and third vertical read gate parts (13 ₁ ) And (13 ₃ ) are turned off, and the potential state becomes as shown in FIG. 7N.

Thus, in the jth horizontal period, the 2j−1th
Row, 1st column and 2jth row, 1st column light receiving element (2 _2j-1,1 )
And the signal charges Q _2j-1,1 and Q _{2j, 1} accumulated in (2 _{2j, 1} )
Is transferred to the first horizontal transfer units (4 ₁ ) and (4 ₃ ). In this case, the second J-
_Light receiving elements (2 _2j-1,2 ~ 2
_2j-1,760 ) is transferred to the storage areas (17S ₁ , 17S ₂ ) of the first horizontal transfer section (4 ₁ ) and the light receiving elements (2j and 2nd row of the 2jth horizontal line) _{2j, 2} ~ 2
_{2j, 760)} to accumulate the signal charges are transferred to the storage area of the third horizontal transfer unit _{(4 3) (27S 1,} 27S 2).

Here, the storage area (17) of the first horizontal transfer unit (4 ₁ )
Of the signal charges Q _{2j-1,1 to} Q _2j-1,760 transferred to S ₂ ),
The signal charges Q _{2j-1,1 to} Q _{2j-1,759 on} the 2k−1th vertical line are
Until the first horizontal transfer section (4 ₁ ) is driven, it is held as it is, but the signal charge of the 2k-th vertical line is T = after the state (T = t ₁₃ ) shown in FIG. 8A. At t ₁₄ , the second vertical read gate portion (13 ₂ ) is turned on (FIG. 8B), T = t ₁₅
The first vertical read gate section (13 ₁ ) is turned off (8th
After the process shown in FIG. C), φ _H1 is set to a low level at T = t ₁₆ , so that as shown in FIG. 8D, the first vertical read gate portion (13 ₂ ) is passed through the gate region of the second vertical read gate portion (13 ₂ ). 2 is transferred to the storage area (19S ₂ ) of the horizontal transfer section (4 ₂ ),
At T = t ₁₇ , the state shown in FIG.

In addition, the storage area of the _third horizontal transfer unit (4 ₃ ) (27
Of the signal charges Q _{2j, 1 to} Q _{2j, 760} transferred to S ₁ ), the second k
The signal charges Q _{2j, 1 to} Q _{2j, 759 on the} −1 vertical line are
It is held as it is until the horizontal transfer section (4 ₃ ) is driven, but the signal charge of the 2k vertical line is T = t ₁₄ after the state (T = t ₁₃ ) shown in FIG. 8A. The process of turning on the fourth vertical read gate section (13 ₄ ) (FIG. 8B) and turning off the third vertical read gate section (13 ₃ ) at T = t ₁₅ (FIG. 8C). After that, when T = t ₁₆ , φ _H1 is set to the low level, and as shown in FIG. 8D, the fourth horizontal transfer section (4) passes through the gate region of the fourth vertical read gate section (13 ₄ ). ₄ ) is transferred to the storage area (29S ₂ ) and T = t ₁₇
Then, the state becomes as shown in FIG. 8E.

Here, the storage area (17) of the first horizontal transfer unit (4 ₁ )
S ₂ ) has signal charges Q _{2j-1,1 to} Q on the _2j- 1th horizontal line.
Signal charge Q of the 1st, 3rd, ... 759th column of _{2j-1,760
2j-1,1,} Q _2j-1,3 ... Q _2j-1,759 are accumulated and retained,
The storage area (19S ₂ ) of the second horizontal transfer unit (4 ₂ ) has a
Of the signal charges Q _{2j-1,1 to} Q _2j-1,760 of the 2j-1 horizontal line, the signal charges Q _2j-1,2 , Q _{2j-1,4 of the second} , fourth, ... 760th column
・ Q _2j-1,760 is stored and held, and the third horizontal transfer unit (4 ₃ )
Of the signal charges Q _{2j, 1 to} Q _{2j, 760} of the 2j-th horizontal line in the storage area (27S ₂ ) of _{the 1st ,} 3rd, ... 759th column, the signal charges Q _{2j, 1} , Q _{2j, 3.}・ Q _{2j, 759} is accumulated and retained, and the 4th
Horizontal transfer section (4 ₄₎ in the storage area of (29S ₂₎ signal charges of the first 2j horizontal line Q _{2j, 1} to Q _2j, second and fourth of the _760-
..Signal charges Q _{2j, 2} , Q _{2j, 4} ... Q _{2j, 760 in the 760th} column are accumulated and held.

Therefore, when the first, second, third and fourth horizontal transfer sections (4 ₁ ), (4 ₂ ), (4 ₃ ) and (4 ₄₎ are driven simultaneously, the first signal charge detection is performed. In the portion (5 ₁ ), the signal charges Q _2j-1,1 , Q of the 1st, 3rd, ...
_j-1,3 ··· Q _2j-1,759 to based on the signal (W signal) is obtained, the second signal charge detector (5 ₂₎ is a 2,4, & among the first 2j-1 horizontal line ..Signal charge Q _2j-1,2 , Q of 760 columns
_A signal (Cy signal) based on _j-1,4 ... Q _2j-1,760 is obtained, and the first, third, ... Of the 2j horizontal lines are supplied to the third signal charge detection unit (5 ₃ ). Signal charge Q _{2j, 1} , Q _{2j, 3}
· · Q _{2j, 759} to the signal (G signal) is obtained based, the fourth signal charge detecting section (5 ₄₎ of the second of the first 2j horizontal line,
4, ... 760 column signal charges Q _{2j, 2} , Q _{2j, 4} ... Q _{2j, 760}
A signal (Ye signal) based on is obtained.

Although illustration and description are omitted, all pixels are read out during one field by the same operation as described above.

As described above, according to the present embodiment, the 4-line simultaneous all-pixel reading can be performed and, for example, the W signal, the Cy signal, the G signal, and the Ye signal can be simultaneously read, so that the composite video signal, for example, the NTSC signal is obtained. There is an advantage that the signal processing circuit can be simplified.

In the above embodiment, supplies a vertical scanning signal φ _V1 ~φ _V504 shown in Figure 6, respectively two potential wells formed in the vertical transfer path (8 _{1-8 760),} the potential wells The case where the vertical transfer path (8 ₁ to 8 ₇₆₀ ) is moved to one end and the other end has been described, but instead of this, as shown in FIG. 9, the vertical transfer portion (8 ₁ to 8 ₇₆₀ ) is The smear control gates (34 _{1 to} 3) are provided at one end and the other end, respectively.
4 ₇₆₀ ) and (35 _{1 to} 35 ₇₆₀ ), and smear drain regions (36 _{1 to} 36 ₃₈₀ ) and (37 _{1 to} 37 ₃₈₀ ) are provided.
Supplying a vertical scanning signal φ _'V1 ~φ' _V504 shown in Fig, 11
As shown in the figure, the potential wells W _A and W _B for transferring the signal charges Q _2j-1,1 and Q _{2j, 1} are formed, and the potential wells W _a and W _b preceding them are formed. Smear charge Q due to potential wells W _a and W _b
Transfer the _m1 and Q _{m @ 2,} the smears control gate portion of the smear charges Q _m1 and Q _{m @ 2} above (34 ₁ to 34 ₇₆₀₎ and (35
_{1 to} 35 ₇₆₀ ) through the smear drain region (36 _{1 to} 36 ₃₈₀ )
And may be the (37 ₁ to 37 ₃₈₀₎ to sweep as, in this case, in addition to above-mentioned same effect can be obtained, it is possible to reduce the smear.

Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

〔The invention's effect〕

According to the present invention, since 4-line simultaneous all-pixel reading can be performed, there is an advantage that a signal processing circuit for obtaining a composite video signal can be simplified.

[Brief description of drawings]

FIG. 1 is a schematic plan view showing a main part of an embodiment of a solid-state image pickup device of the present invention, FIG. 2 is a schematic plan view showing a color filter array used in the example of FIG. 1, and FIG. 3 is a vertical transfer. FIG. 4 is a cross-sectional view showing the main part of the first portion, FIG.
Of the horizontal transfer section, the second vertical read gate section, and an essential part of the second horizontal transfer section, and FIG. 5 is a plan view showing a third vertical read gate section, a third horizontal transfer section, FIG. 6 is a schematic partially enlarged plan view showing essential parts of a fourth vertical read gate section and a fourth horizontal transfer section, FIG. 6 is a waveform diagram showing various signals used in the j-th horizontal period, and FIG. 7 is vertical transfer. Of the signal transfer paths of the first, second, third, and fourth horizontal transfer sections, and FIG. 8 is a diagram showing potential changes of the signal transfer paths of the first section, the memory area, and the first and second vertical read gate areas. And a diagram showing potential changes in the first, second, third and fourth vertical read gate portions, FIG. 9 is a schematic plan view showing an essential portion of another embodiment of the present invention, and FIG. FIG. 9 is a waveform diagram showing an example of the vertical scanning signal used in the example, and FIG. 11 is a potential variation of the signal transfer path of the vertical transfer section. It is a diagram showing conversion. (2 _1,1 ) to (2 _504,760 ) are light receiving elements, (3 ₁ ) to (3 ₇₆₀ )
Is a vertical transfer unit, (4 ₁ ), (4 ₂ ), (4 ₃ ) and (4 ₄ ) are the first, second, third and fourth horizontal transfer units, respectively (5 ₁ ),
(5 _{2), (3)} and ₍₄₎ is a signal charge detector.

Front page continuation (72) Inventor Maki Sato 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Within Sony Corporation (56) References Japanese Patent Laid-Open No. 59-103486 (JP, A) Shoukai 58-56458 (JP, U)

Claims (1)

(57) [Claims] 1. A vertical and horizontal direction on a semiconductor substrate.
2m × 2n light-receiving elements arranged in a matrix, a vertical transfer section that is provided for each column of the light-receiving elements and vertically transfers the signal charges obtained in the light-receiving elements, and one end of the vertical transfer section And the first, second, third, and fourth horizontal transfer units, which are respectively provided at the other end and horizontally transfer the signal charges transferred through the vertical transfer unit, and the first, second, and second horizontal transfer units. And 3rd and 4th signal charge detection parts provided on the output side of the horizontal transfer part, and 2j-1 (where j = 1,2, ...
m) The signal charges of the horizontal line and the 2j-th horizontal line are read out to the vertical transfer unit, and the 2k-1 (k = 1, 2, ... N) of the signal charges of the 2j-1-th horizontal line are read. The signal charge of the vertical line is transferred to the first horizontal transfer unit, and the signal charge of the 2k-th vertical line of the signal charges of the 2j-1th horizontal line is transferred to the second horizontal transfer unit. Of the signal charges of the 2j horizontal lines, the signal charges of the 2k-1 vertical lines are transferred to the third horizontal transfer unit, and the signal charges of the 2k vertical lines of the signal charges of the 2j horizontal lines are transferred to the fourth The solid-state imaging device is characterized in that the image is transferred to the horizontal transfer unit of.