JP2565109B2 - Virtual ground type semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a virtual ground type semiconductor memory device having a floating gate type non-volatile memory cell virtual ground memory array.

[0002]

2. Description of the Related Art A nonvolatile memory cell having a floating gate has, for example, a source diffusion region and a drain diffusion region provided in a P-type semiconductor substrate, and is electrically insulated from the outside by an insulating film on the P-type semiconductor substrate. A floating gate and a control gate for switching control of the memory cell are provided. When writing information to this memory cell, a high voltage is applied to the control gate and drain diffusion region of the memory cell and the source diffusion region is set to the ground potential. Information is stored by injecting electrons into the floating gate by injecting hot carriers generated thereby and changing the threshold voltage of the memory cell viewed from the control gate.

A conventional high density semiconductor memory virtual ground type semiconductor memory device using the above floating gate type nonvolatile memory cell will be described with reference to FIG. 8 (reference: Boaz Ei).
tan: IEEE Electron Device
Letters, Vol. 12, No. 8, pp. 45
0-452, Aug. 1991).

In FIG. 8, the memory cell array has a plurality of array segments SEG _i-1 , SEG _i , SEG _{i + 1} ...
Are divided into a plurality of array segments SE
Main bit lines MBL ₁ , MBL ₂ , ... Are provided in common for G _i-1 , SEG _i , SEG _{i + 1} . An array segment such as SEG _i has a plurality of sub-bit lines SB.
L _i1 , SBL _i2 , ... _Are provided, and these sub bit lines SBL _i1 , SBL _i2 ,.
It exists between L ₁ and MBL ₂ . That is, the sub-bit lines SBL _i1 , SBL _{i2 of} each array segment SEG _i ,
The number of main bit lines MBL ₁ , MBL ₂ , ... Is almost the same. Further, each array segment SEG _i is provided with a plurality of word lines WL _i1 , WL _i2 , ..., WL _i32 . In each array segment SEG _i , floating gate type nonvolatile memory cells Q _m1 , Q _m2 connected between two bit lines, that is, one main bit line and one sub bit line and controlled by one word line, ... is provided. For example, the memory cell Q _m3 is connected between the main bit line MBL ₂ and the sub bit line SBL _2, and is controlled by the word line WL _i1 . For accessing the memory cells Q _m1 , Q _m2 , ..., It is necessary to connect the sub bit lines to the main bit lines. For this,
Selector transistors Q _S1 , Q _S2 , Q _S1 ', Q _S2 ' ... _Are provided, and selector lines SEL _i1 and SE for controlling them are provided.
L _i2 , SEL _i1 ′ and SEL _i2 ′ are provided.

The operation of the circuit shown in FIG. 8 will be described. For example, in order to perform the read operation of the memory cell Q _m1 , the selector lines SEL _i1 and SEL _i1 'of the array segment SEG _i are set to 5 times.
V, and the selector line SEL of the array segment SEG _i
The selector lines of _i2 , SEL _i2 'and other array segments are set to 0V. As a result, the select transistor Q _S1 ,
Q _S2 , Q _S1 'and Q _S2 ' are turned on and the other select transistors are turned off. Further, the word line WL _{i1 is set} to 5V and the other word lines are set to 0V. Further, the main bit line MBL _{1 is set} to 2V and the main bit line MBL _{2 is set} to 0V. As a result, only the current path of the main bit line MBL ₁ , the memory cell Q _m1 , the sub bit line SBL _i1 , the select transistors Q _S1 , Q _S1 ', and the main bit line MBL ₂ exists, and the current flowing through this current path. Information in the memory cell Q _m1 can be read _{depending on} the presence or absence of. In the write operation, the same selection operation as in the read operation is performed, but the applied voltage is high. For example, the voltage of the selected selector lines SEL _i1 and SEL _i1 ′ is set to 12V, the voltage of the selected word line WL ₁ is set to 12V, and the voltage of the selected main bit line MBL ₁ is set to 7V. As a result, a channel current is made to flow and otto electrons are injected into the floating gate to perform writing.

Next, another conventional virtual ground type semiconductor memory device will be described with reference to FIG. 9 (see Japanese Patent Laid-Open No. 2-241).
No. 060 publication). Also in FIG. 9, the main bit line MB
L ₁ , MBL ₂ , ... Are array segments SEG _i-1 , S
EG _i , SEG _{i + 1} are commonly provided, and the sub-bit lines SBL _i1 , SBL _i2 , ... Are provided in each array segment SEG.
_i−1 , SEG _i , SEG _{i + 1} ... However, the memory cells Q _m1 , Q _m2 , ... Are connected between two adjacent sub-bit lines, and the main bit lines MBL ₁ , MB
Not directly connected to L ₂ , ...

The circuit operation of FIG. 9 will be described. For example, in order to perform the read operation of the memory cell Q _m1 , the selector line SEL _i of the array segment SEG _i is set to 5V and the selector lines of the other array segments are set to 0V. As a result, the select transistors Q _S1 , Q _S2 , ... Of the array segment SEG _i are turned on, and the select transistors of the other array segment select are turned off. Also,
The word line WL _{i1 is set} to 5V and the other word lines are set to 0V. Further, the main bit line MBL _{1 is set} to 2V and the main bit line MBL _{2 is set} to 0V. As a result, the main bit line MBL ₁ , the select transistor Q _S1 , the sub bit line SBL _i1 , the memory cell Q _m1 , and the sub bit line SBL.
_i2 , select transistor Q _S2 , main bit line MBL
_Since there are only _two current paths, the information in the memory cell Q _m1 can be read _{depending on} the presence / absence of a current flowing in this current path. In the write operation, the same selection operation as in the read operation is performed, but the applied voltage is high. For example, the voltage of the selected selector line SEL _i is 12V, the voltage of the selected word line WL ₁ is 12V, and the voltage of the selected main bit line MBL ₁ is 7V. As a result, a channel current is made to flow and otto electrons are injected into the floating gate to perform writing.

[0008]

In the conventional virtual ground type semiconductor memory device shown in FIG. 8, the main bit line pitch is one for every two memory cells in the column direction.
Although advantageous in terms of high integration, the memory cells Q _m1 , Q _m2 ,
The drain (or source) of ... Is directly connected to the main bit line, and as a result, even in the non-selected array segment, a high voltage is applied to the drain of the memory cell at the time of writing, and therefore due to this voltage stress. There is a problem of causing a program disturb phenomenon in which written data is erased. This is particularly remarkable when the insulating layer below the floating gate electrode of the memory cell is thin. Further, in the conventional virtual ground type semiconductor memory device shown in FIG. 9 described above, since the memory cells are not directly connected to the main bit lines, there is an advantage that the program disturb phenomenon is less likely to occur, but the pitch of the main bit lines is Since one memory cell is arranged in the column direction, there is a problem that the degree of integration is reduced. Further, in any of the conventional virtual ground type semiconductor memory devices, it is possible to erase by ultraviolet irradiation, but it is impossible to electrically erase, and therefore,
It is disadvantageous in terms of manufacturing cost unless it is assembled in an expensive window package.

Therefore, it is an object of the present invention to provide a virtual ground type semiconductor memory device which prevents the program disturb phenomenon and has a high degree of integration. Another object is to provide an electrically erasable virtual ground type semiconductor memory device.

[0010]

In order to solve the above problems, the present invention provides a virtual ground type semiconductor memory device in which a memory cell array is divided into a plurality of array segments.
A plurality of main bit lines provided in common to each array segment are provided. Each array segment is connected to a plurality of word lines, a plurality of sub-bit lines, and two sub-bit lines adjacent to each other among the plurality of sub-bit lines, and is controlled by one of the plurality of word lines. Floating gate type nonvolatile memory cell and the (2n-1) th and 2nth subbit lines (n = 1, 2, ...) Of the plurality of subbit lines are the nth of the plurality of main bit lines. Of the plurality of sub-bit lines, the first selector means connected to the main bit line of the
Second selector means for connecting the + 1st sub bit line to the nth main bit line of the plurality of main bit lines.

[0011]

According to the above means, no memory cell is directly connected to the main bit line. Further, the pitch of the main bit lines is one for every two memory cells in the column direction.

[0012]

1 is a circuit diagram showing a first embodiment of a virtual ground type semiconductor memory device according to the present invention. 1 is the same as in the conventional example of FIG. 8 in that the pitch of the main bit lines MBL ₁ , MBL ₂ , ... Is one for every two memory cells in the column direction, and the memory cells Q _m1 , Q _m2 ,
Is not directly connected to the main bit lines MBL ₁ , MBL ₂ , ... Is the same as the conventional example of FIG.
The virtual ground type semiconductor memory device of FIG. 1 has an advantage of high integration in the conventional example of FIG. 8 and an advantage of preventing the program disturb phenomenon in the conventional example of FIG. The memory cells Q _m1 , Q _m2 , ... In FIG. 1 have sub-bit lines SBL _i1 , SB similarly to the conventional example shown in FIG.
Of L _i2 , ... Connected between two adjacent sub-bit lines and controlled by one of the word lines WL _i1 , WL _i2 ,.

The select transistors Q _S1 , Q _S2 , ... Include main bit lines MBL ₁ , MBL ₂ ,.
BL _i1 , SBL _i2 , ... _Are connected and controlled by the select signal SEL _i0 . That is, when the select signal SEL _i0 becomes active (high level), the main bit line MBL ₁ becomes the sub bit line SBL _i1 ,
The main bit line MBL ₂ is connected to SBL _i2 , and the main bit line MBL ₂ is connected to sub-bit lines SBL _i3 and SBL _i4 . In general, the n-th main bit line MBL _n the (2n-1) -th, is connected to the 2n-th sub-bit line SBL _2n-1, SBL _2n. However, it is a natural number such that n = 1, 2, 3, ... The select transistors Q _S1 , Q _S2 , ... Are connected to the main bit lines MBL ₁ , MBL ₂ ,.
BL _i1 , SBL _i2 , ... _Are connected and controlled by the select signal SEL _i0 . That is, when the select signal SEL _i0 becomes active (high level), the main bit line MBL ₁ becomes the sub bit line SBL _i1 ,
The main bit line MBL ₂ is connected to SBL _i2 , and the main bit line MBL ₂ is connected to sub-bit lines SBL _i3 and SBL _i4 . In general, the n-th main bit line MBL _n the (2n-1) -th, is connected to the 2n-th sub-bit line SBL _2n-1, SBL _2n. However, it is a natural number such that n = 1, 2, 3, ...

The select transistor Q _S1 ',
Q _S2 ', ... even main bit line MBL _1, MBL _2, ... and the sub-bit line SBL _i1, SBL _i2, be one that connects ... and is controlled by the select signal SEL _i1.
That is, when the select signal SEL _i1 becomes active (high level), the main bit line MBL ₁ is connected to the sub bit lines SBL _i2 and SBL _i3 , and the main bit line MB
L is connected to the sub bit lines SBL _i4 and SBL _i5 . Generally, the nth main bit line MBL _n is the 2nth and (2n + 1) th sub bit lines SBL _2n and SB.
It is connected to L _{2n + 1} . However, it is a natural number such that n = 1, 2, 3, ...

The substrate electrodes of the memory cells Q _m1 , Q _m2 , ... And the substrate electrodes of the select transistors are connected to the substrate bias line V _BB .

The read operation of FIG. 1 will be described with reference to FIGS. For example, the case of reading the memory cell Q _m2 of the array segment SEG _i is shown in FIG. In this case, the word line WL _i1 connected to the control gate of the memory cell Q _m2 is set to 5V and the other word lines are set to 0V. This is performed by an X decoder provided for each array segment (not shown), for example, SEG _i . Further, the select line SEL _i0 of the array segment SEG _i is set to 5V, and the select line SEL _i1 of the array segment SEG _{i and} the select lines of other array segments are set to 0V. This is performed by a decoder which is enabled for each array segment (not shown), for example, SEG _i , and receives 1 bit of the Y address. Further, the main bit line MBL _{1 is set} to 0.
V, and the main bit line MBL _{2 is set} to 1V. In this case, the voltage of the non-selected main bit line is set to be the same as or open to the voltage of the adjacent selected main bit line. For example, the voltage of the main bit line on the left side of the selected main bit MBL ₁ (in this case, it is assumed that the main bit line does not exist, but exists) is set to 0V or the open voltage of the selected main bit line MBL ₁ , and the right side of the selected main bit MBL ₂ . The voltage of the main bit lines MBL ₃ , MBL ₄ , ... Is set to the voltage 1V of the selected main bit line MBL ₂ or open.
This is performed by a Y decoder (not shown). This allows
Although the word line is selected, the source-drain potential of the half-selected memory cell in which the bit line is in the non-selected state becomes 0 or open, so that the leak current due to the half-selected memory cell can be prevented. As a result, the main bit line MBL
₂ , select transistor Q _S3 , sub bit line SB
Since only the current path of L _i3 , the memory cell Q _m2 , the sub bit line SBL _i2 , the select transistor Q _S2 , and the main bit line MBL ₁ exists, the information of the memory cell Q _m2 can be read _{depending on} the presence / absence of current in this current path. it can.
That is, if the threshold voltage electrons are written in the floating gate of the memory cell Q _{m @ 2,} for example, 5V or the current does not flow, on the contrary, the floating gate of the memory cell Q _{m @ 2} electrons in an erase state without If so, the threshold voltage becomes less than 5 V and the current flows. The presence or absence of such a current is detected by a sense amplifier (not shown). In addition, in FIG. 2, the voltage of the substrate bias line V _BB is 0V.

The array segment SEG_iMemory of
Cell Q_m3Is read out as shown in FIG. in this case,
Memory cell Q_m3Word line connected to the control gate of
WL _i1To 5V and the other word lines to 0V. Also,
Array segment SEG_iSelect line SEL_i1To 5V
And the array segment SEG_iSelect line SEL_i0
And the select lines of other array segments are set to 0V.
Furthermore, the main bit line MBL₁To 0V,
Line MBL₂To 1V. In this case as well, non-selected
The voltage on the bit line and the voltage on the selected main bit line
Set to the same or open state. This makes the word
The line is selected, but the bit line is not selected.
The source-drain potential of the selected memory cell is 0 or
Since it becomes a bun, the leakage current due to the half-selected memory cell
Can be prevented. As a result, the main bit line MBL₂,
Rect transistor Q_S3, Sub bit line SBL_i4, Notes
Resel Q_m3, Sub bit line SBL_i3, Select transition
Star Q_S2, Main bit line MBL₁Only current path exists
By doing this, the memory is
Resel Q_m3Information can be read. Note that FIG.
At the substrate bias line V_BBIs 0V.

The write (program) operation of FIG. 1 will be described with reference to FIGS. The selection method is basically the same as that in the read operation. For example, the case of writing the memory cell Q _m2 of the array segment SEG _i is shown in FIG. In this case, the word line WL _i1 connected to the control gate of the memory cell Q _m2 is set to 12V and the other word lines are set to 0V. This is performed by an X decoder provided for each array segment (not shown), for example, SEG _i . Further, the select line SEL _i0 of the array segment SEG _i is set to 12V, and the select line SEL _i1 of the array segment SEG _{i and} the select lines of other array segments are set to 0V. This is performed by a decoder which is enabled for each array segment (not shown), for example, SEG _i , and receives 1 bit of the Y address. further,
The main bit line MBL _{1 is set} to 0V and the main bit line M
Set BL ₂ to 6V. In this case as well, the voltage of the non-selected main bit line is set to be the same as or open to the voltage of the adjacent selected main bit line. For example, the voltage of the main bit line on the left side of the selected main bit MBL ₁ (in this case, it does not exist, but it is assumed that it exists) is the selected main bit line MB.
The voltage of L ₁ is set to 0 V or opened, and the main bit lines MBL ₃ and MBL on the right side of the selected main bit MBL ₂ are set.
BL _4, is ... voltage and the voltage 6V or open the selected main bit line MBL _2. This is performed by a Y decoder (not shown). As a result, the potential between the source and drain of the half-selected memory cell in which the word line is selected but the bit line is in the non-selected state becomes 0 or open, so that the leak current due to the half-selected memory cell can be prevented.
As a result, since only the current path of the main bit line MBL ₂ , the select transistor Q _S3 , the sub bit line SBL _i3 , the memory cell Q _m2 , the sub bit line SBL _i2 , the select transistor Q _S2 , and the main bit line MBL ₁ exists, this current Channel current flows in the path and memory cell Q
_m2 will be programmed. In addition, in FIG. 4, the voltage of the substrate bias line V _BB is 0V or −2V.

FIG. 5 shows the case of writing the memory cell Q _m3 of the array segment SEG _i . in this case,
The word line WL _i1 connected to the control gate of the memory cell Q _m3 is set to 12V, and the other word lines are set to 0V. Further, the select line SEL _i1 array segment SEG _i to 12V, the select line S of the array segment SEG _i
The select lines of EL _i0 and other array segments are set to 0V. Further, the main bit line MBL _{1 is set} to 0V and the main bit line MBL _{2 is set} to 6V. In this case as well, the voltage of the non-selected main bit line is set to be the same as or open to the voltage of the adjacent selected main bit line. This allows
Although the word line is selected, the source-drain potential of the half-selected memory cell in which the bit line is in the non-selected state becomes 0 or open, so that the leak current due to the half-selected memory cell can be prevented. As a result, the main bit line MBL
₂ , select transistor Q _S3 , sub bit line SB
Since only the current path of L _i4 , the memory cell Q _m3 , the sub bit line SBL _i3 , the select transistor Q _S2 , and the main bit line MBL ₁ exists, a channel current flows in this current path to program the memory cell Q _m3. become. In FIG. 5, the voltage of the substrate bias line V _BB is 0V or -2 V.

FIG. 6 is a diagram showing a bias state of each memory cell at the time of writing (programming). FIG. 6A shows a memory cell in the selected array segment, where A is the selected memory cell, B and C are the half-selected memory cells in which the word line is selected and the sub-bit line is unselected, and D is the word line in non-selected. Selected, semi-selected memory cell with sub-bit line selected,
F and E are non-selected memory cells. Also, FIG. 6 (B)
Indicates a memory cell in an unselected array segment, and G is an unselected memory cell. As shown in FIG. 6C,
Since no voltage is applied to the drains of the unselected memory cells G of the unselected array segment and the unselected memory cells F of the selected array segment, the applied voltage stress is small and the change in the floating gate accumulated data due to the program, that is, the program disturb phenomenon. Rarely occurs. Therefore, it is highly likely that the program disturb phenomenon will occur in the half-selected memory cells B, C, D and the non-selected memory cells E, all of which are memory cells in the selected array segment. Among them, the memory cells C, D, and E having a high drain voltage (6 V) are particularly prone to the program disturb phenomenon. For example, it is remarkable when the thickness of the insulating layer under the floating gate electrode is 150 Å or less. Further, since the memory cells D and E which have already been written are in a bias state in which electrons in the floating gate are extracted, the program disturb phenomenon easily occurs. In any case, the applied voltage stress time is proportional to the number of programmed cells in the array segment. Therefore, since the memory cells F and G in which the above program disturb phenomenon hardly occurs are present, the occurrence of the program disturb phenomenon is substantially reduced.

The erase operation of FIG. 1 will be described with reference to FIG. The erase operation is collectively performed in array segment units.
For example, when performing an erase operation of the memory cell array segment SEG _i, all the word lines WL _i1, WL _i2 ... of array segment SEG _i, the WL _i32 to negative high voltage -13 V, the other array segment word The line is 0V
And Further, the select signals SEL _i0 and SEL _i1 of any of the array segments are set to 0 V, and the main bit lines MBL ₁ , MBL ₂ , ... Are opened. further,
The substrate bias line V _{BB is set} to 5V. As a result, in the memory cell in the selected array segment SEG _i , the electric field becomes strong between the floating gate electrode and the substrate. In this case, if the thickness of the insulating film under the floating gate electrode is set to a thin film of, for example, about 100 Å, the electric field becomes strong enough to cause the FN tunnel phenomenon, so that the electrons are emitted from the floating gate electrode. Can occur and can be erased. It is necessary to perform erasing after programming in advance in order to adjust the cell threshold voltage to a high voltage before erasing for collective erasing. Even in the non-selected array segment, 5 V is applied to the substrate from the substrate bias line V _BB , but the voltage of the word line is as low as 0 V and the electric field between the floating gate electrode substrates is small, so that erasing does not occur.

[0022]

As described above, according to the present invention, the number of main bit lines can be reduced, so that high integration can be achieved.
Moreover, since the memory cell is not directly connected to the main bit line, the program disturb phenomenon of the memory cell in the non-selected array segment can be prevented. Further, according to the present invention, it is possible to electrically erase the virtual ground type semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a virtual ground type semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram illustrating a read operation of FIG.

FIG. 3 is a circuit diagram illustrating a read operation of FIG.

FIG. 4 is a circuit diagram illustrating the write operation of FIG.

5 is a circuit diagram illustrating the write operation of FIG. 1. FIG.

6 is a diagram showing a bias state of the memory cell at the time of writing in FIG. 1. FIG.

FIG. 7 is a circuit diagram illustrating the erase operation of FIG.

FIG. 8 is a circuit diagram showing a conventional virtual ground type semiconductor memory device.

FIG. 9 is a circuit diagram showing a conventional virtual ground type semiconductor memory device.

[Explanation of symbols]

SEG _i-1 , SEG _i , SEG _{i + 1} ... Array segment MBL ₁ , MBL ₂ ... Main bit lines SBL _i1 , SBL _i2 ... Sub bit lines WL _i1 , WL _i2 ... Word lines SEL _i0 , SEL _i1 ... Select line Q _m1 , Q _m2 ... Memory cells Q _S1 , Q _S2 , ..., Q _S1 ', Q _S2 ' ... Select transistor V _BB ... Substrate bias line

Claims (3)

(57) [Claims] _1. A virtual ground type semiconductor memory device in which a memory cell array is divided into a plurality of array segments (SEG _i-1 , SEG _i , SEG _{i + 1} ) and a plurality of memory cells provided in common to each array segment. Main bit lines (MBL ₁ , MBL ₂ ...), each array segment (SEG _i ) includes a plurality of word lines (WL _i1 , WL _i2 , ...), and a plurality of sub-bit lines (SBL _i1 , SBL _i) . _i2 , ...) and a plurality of floating gate nonvolatile memory cells (Q _m1 which are connected between two adjacent sub-bit lines of the plurality of sub-bit lines and controlled by one of the plurality of word lines). , Q _m2 , ...) And the (2n−1) th and 2nth sub-bit lines (n = 1, 2, ...) Of the plurality of sub-bit lines are the n-th of the plurality of main bit lines. of First selector means (SEL _i1 , Q _S1 , Q _S2 , connected to the main bit line,
...), and 2n-th and 2n + th of the plurality of sub-bit lines
Second selector means (SEL _i2 , Q _S1 ′, Q _S2 ′, ...) For connecting the first sub bit line to the nth main bit line of the plurality of main bit lines. A characteristic virtual ground type semiconductor memory device. 2. One of the word lines is selected and a predetermined voltage (for example, 5V or 12V) is applied, and two of the main bit lines are selected and a predetermined potential difference (for example, 1V or 6V) is applied. Then, the potential of the unselected main bit line is made equal to or open to the potential of the closest main bit line of the selected main bit lines, and one of the first and second selector means is selected. 2. The virtual ground type semiconductor memory device according to claim 1, wherein a read operation or a write operation is performed. 3. A substrate bias line (V _BB ) for commonly connecting substrate electrodes of the memory cells is provided, and a predetermined voltage (for example, − is applied to all word lines of one array segment of the plurality of array segments). 13 V) is applied to apply a predetermined voltage (for example, 5 V) to the substrate bias line.
2. The virtual ground type semiconductor memory device according to claim 1, wherein the electrical erasing operation is performed for each array segment by applying V) and deselecting the first and second selector means. .