JP2564699B2 - Queue control memory circuit - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional technology (FIGS. 3 and 4) Problem to be solved by the invention (FIG. 5) Means for solving the problem (first embodiment) Fig.) Action Embodiment (Fig. 2) Effect of the invention [Overview] Regarding a queue control memory circuit, the purpose is to manage processing requests of a plurality of priorities with a single queue memory, and A queue control memory circuit that holds a processing request and that has a pointer portion in which a processing request number to be processed next is written, and in a queue control memory circuit that sequentially processes processing requests, holds a processing request with different priority. The memory, the top number holding means for holding the top number which is the address number of the queue memory to be processed next for each priority, and the address of the queue memory in which the latest processing request number is entered. The bottom number holding means for holding the bottom number, which is the serial number, is provided.

[Industrial applications]

The present invention relates to a queue control memory circuit, and more particularly to a queue control memory circuit capable of managing a queue by one queue memory even when a processing request source has a plurality of priorities.

[Conventional technology]

In some cases, the data processing device wants to receive processing requests from a plurality of processing request sources and perform processing in observance of the received order (FIFO: First In First Out). In this case, if the number of processing request sources increases, it becomes difficult to store the accepted order, so that the queue memory is used.

A control circuit using a conventional queue memory will be described with reference to FIG. In FIG. 3, reference numeral 30 denotes a queue memory, which has a pointer section 30-0, a valid section 30-1, and an ECC (Error
Correcting Code) section 30-2. Reference numeral 31 is a write register, 32 is an address register, 33 is an ECC generation unit, and 34 is a check correction unit.

When a processing request is issued from a processing request source (not shown),
This is set in the enqueue register 35. In addition,
When a processing request is generated, the control unit (not shown) writes this processing request in a buffer (not shown), and the address (number) of the buffer is set in the enqueue register 35. The number to be processed next is entered in the top register 36 indicating the processing request source number at the head of the FIFO queue,
The latest processing request number is written in the bottom register 37 indicating the processing request source number corresponding to the end of the FIFO queue. This number is the address of the queue memory 30 and is the same as the address of the buffer.

The counter 38 counts the number of queues that should be requested to be processed. When enqueuing, the counter register 38-
The value of 1 is incremented by 1 and re-entered.
Do 1

Now, when the counter 38 is not zero, that is, when a value of 1 or more is written in the counter register 38-1, when the enqueue process is performed as shown in the uppermost column in FIG. 4, the stage "0" is set. As shown, set the address register 32 to the most recently written address in the bottom register 37, which was written to the queue memory 30,
Set queue memory 30 to write mode and write register
The number written in the enqueue register 35 in the queue write data section 31-0 of 31 is set as the next address, the valid bit V is set, the counter 38 is incremented by 1, and the bottom register 37 is set to the enqueue register 35. Set the entered number. Of course the ECC according to this
It is created by the generator 33 and this is written in the ECC section 31 of the write register 31.
-2, so that at stage "0" these are bottom address register 37 or address register 32.
Is written in the address of the counter and the counter 38 is incremented by one. Then enqueue to the bottom address register 37
The number entered in register 35 is newly set.

In the next stage "1", the number written in the enqueue register 35 is set in the address register 32, the queue memory 30 is set to the write mode, and the valid bit V is written. At this time, the pointer unit 30-0 writes Nill processing, for example, all zeros.

Also, as shown in the third column of FIG. 4, the counter 38 is set to "1".
The case where the dequeuing processing is not performed below, that is, when it is "2" or more will be described.

At stage “0”, the address register 32
The number set in the register 36 (that is, the address number of the queue to be processed next time) is set, the read mode is set, and the counter 38 is decremented by one. As a result, the number to be processed next is output from the pointer section 30-0. Therefore, at stage "1", the read / correct data is checked by the check / correction section 34 using the ECC, and the correct one is checked by the top register. Fill in 36 for the next address to process. At this time, since the queue memory 30 is set to the write mode, the pointer unit 30-0 is Nill-processed and the valid is dropped in the stage "1".

As shown in the fifth column of FIG. 4, in the case of priority change (PCHG), the queue to be processed next is processed at the last position, so at stage “0”, the queue memory 30 is read. In the mode, the number set in the top register 36 is set in the address register 32, and the queue memory 30 is read. At the stage "1", the queue memory 30 is set to the write mode, and the number indicating the next address of the pointer portion 30-0 previously read from the queue memory 30 is written in the top register 36. Then, the number set in the bottom register 37 is set in the address register 32, the number held in the top register 36 is written in the destination number of the bottom register 37, and the valid is set. Then, in stage "2", the number set in the bottom register 37 (the number previously set in the top register 36) is set in the address register 32, the queue memory 30 is set to the write mode, and the pointer section 30 Nil processing is performed for -0, and a valid is set in the valid unit 30-1.

Further, as shown in the last column of FIG. 4, in the case of the test, the queue memory 30 is set to the read mode, and the test target number is written in the address register 32. As a result, if the number of the test target is written in the queue memory 30, the valid bit is set, so that it can be tested that the predetermined queue has been written in the queue memory 30.

It should be noted that each processing request source issues one processing request. The control unit, which is omitted in FIG. 3, manages this queue.

[Problems to be Solved by the Invention]

By the way, when each processing request source issues a processing request in which priority classes are divided into several types, it is necessary to prepare as many as shown in FIG. 3 the number of classes shown in FIG. Become.

That is, when classes are classified into 0 to n types, queue memories 40-0 to 40-n, ECC generation units 41-0 to 41-n, check correction units 42-0 to 42-n, address registers 43-
0-43-n, input register 44-0-44-n, top register 45-0-45-n, bottom register 46-0-46-
n, counters 47-0 to 47-n, etc. are required. That is, the capacity of the memory is required to be equal to the number of classes of the priority, which reduces the efficiency of use of the memory and causes a cost increase.

Therefore, an object of the present invention is to provide a queue memory control circuit capable of managing a processing request having a priority class with a small capacity queue memory.

[Means for solving the problem]

In order to achieve the above object, in the present invention, FIG.
As shown in FIG. 3, the queue memory 1 is provided with a class unit 1-3 in addition to the pointer unit 1-0, the valid unit 1-1, and the ECC unit 1-2. It should be noted that in FIG. 1 (A), the priority levels 2 are “0” and “1”.
In the case of fractions, 2 is a write register, 3 is an address register, 4 is an ECC generation unit, 5 is a check correction unit, 6-0 and 6-1 are counters, 7-0 and 7-, respectively.
Reference numeral 1 is a counter register, and 8-0 and 8-1 are addition / subtraction units. Where 6-0, 7-0, 8-0
Indicates each part for the class “0”, and 6-1, 7-1, 8
-1 indicates each part for the class "1". 9-0 is a top register for class "0", 9-1 is a top register for class "1", 10-0 is a bottom register for class "0", 10-1 is a bottom register for class "1". It is Regis A. Further, 11 is an enqueue register, which has a queue unit 11-0 and a class unit 11-1.
In the enqueue register 11, a processing request source (not shown) outputs a processing request and writes it in the processing request. Note that the processing request source outputs only one request at a time. In this example, the class "1" is high level (H) and the class "0" is low level (L).

[Action]

The operation of the present invention will be described with reference to FIG. In FIG. 1 (B), the operation is illustrated for 17 cases as shown by to, but for simplification of the description, representative several examples will be described.

Enqueue processing for class 1 (when the counter on the H side is not "0") Stage 0 is an empty cycle. For example, in the case of priority change, since three stages are required, an empty cycle is prepared for simplifying the hardware. In the stage 1, the queue memory 1 is set to the write mode, the number of the bottom register 10-1 on the H side, that is, the class "1" is written in the address register 3, and the pointer portion 1-0 of the queue memory 1 is entered. Enter the number (enqueue number) entered in the queue section 11-0 of the enqueue register 11 and enter the same R as valid V in the valid section 1-1.
, H in class section 1-3, and counter 6-
Increment 1 by 1. Then, the number entered in the queue section 11-0, which has arrived, is entered in the bottom register 10-1 on the H side. In the stage 2, the queue memory 1 is also set to the write mode, the enqueue number is set in the address register 3, the pointer portion 1-0 of the corresponding word portion of the queue memory 1 is Nill processed, and the valid portion 1-1.
Enter R indicating valid V and H in class part 1-3.

Enqueue processing for class 1 (when the H side counter is "0") Stage 0 is an empty cycle. In stage 1, the data written in the bottom register 10-1 on the H side is set in the address register 3, but it is not necessary to access the queue memory 1. The counter 6-1 controls +1, and the enqueue number, the valid bit R, and H indicating the class are entered in the queue section 11-0 of the enqueue register 11 in the H side top register 9-1. , H
Write this enqueue number also in the bottom register 10-1 on the side. Then, in stage 2, the queue memory 1 is set to the write mode, the enqueue number is set in the address register 3, the pointer portion 1-0 of the corresponding word in the queue memory 1 is Nill processed, and the valid portion 1-1 is validated. Fill in and fill in H in class section 1-3.

Dequeuing processing for class 1 (when the counter on the H side is 2 or more) At stage 0, the number written in the top register 9-1 on the H side is set in the address register 3, and the queue memory 1 is set to the read mode. To read the data. In the stage 1, the queue memory 1 is set in the write mode, and the address register 3 is set to the number written in the top register 9-1 as in the stage 0.
Then, the pointer portion 1-0 is Nill-processed, and the valid portion 1-1 and the class portion 1-3 are zero-filled. Then, the counter 6-1 is decremented by 1, and the next number and the valid bit and class 1 (H) obtained from the pointer unit 1-0 read at the stage 0 are written in the H side top register 9-1. Stage 2 is an empty cycle.

Dequeue process for class 1 (when counter on H side is 1) Stage 0 is the same as above. Stage 1 processes queue memory 1 and counter 6-1 as follows.
Same as above, but the top register 9-1 contains Ni
ll processing, 0 for each valid bit and class
Fill in. And the bottom register 10-1 also has Nill
Perform processing. Stage 2 is an empty stage as described above.

Test processing In stage 0, the request number to be tested is written in the address register 3 and the queue memory 1 is set to the read mode. If the valid bit is output by this, the test is successful. The stages 1 and 2 are empty stages.

Next, the priority change control will be described.

The priority can be changed from the top of class 1 to the bottom, the top of class 1 to the bottom of class 0, class 0.
For the three cases from top to bottom of the class, the counter on the class 1 side corresponds to 2 depending on the state of each counter.
There are cases where the counter on the class 0 side is 1 or more, and cases where it is 0. Representative examples of the above three examples will be described below.

Priority change (change from top to bottom of class 1 and counter is 2 or more) At stage 0, add address register 3 to the top of H side
The number of the register 9-1 is set, the queue memory 1 is set to the read mode, and the pointer portion 1-0 is read. At the stage 1, the number of the bottom register 10-1 on the H side is set in the address register 3, the queue memory 1 is set to the write mode, and the number of the top register 9-1 on the H side is set in the pointer section 1-0. , The valid section 1-1, the valid section R, and the class section 1-3, the H section.
Then, the stage 0 is added to the top register 9-1 on the H side.
Enter the number (RQD) read from the pointer section 1-0 of the queue memory 1 and the valid R and class H in the bottom register 10-1 on the H side until that time.
Enter the number written in -1. On stage 2,
Address register 3 has bottom register 10-1 on the H side.
The newly entered number is set to, the queue memory is set to the write mode, the pointer portion 1-0 is Nill processed, the valid portion 1-1 is filled with the valid R, and the class portion 1-3.
Enter H in.

Change priority (when the top of class 1 is changed to the bottom of class 0, the counter on the H side is 2 or more and the counter on the L side is 1 or more)
The number of the register 9-1 is set, the queue memory 1 is set to the read mode, the pointer portion 1-0 thereof is read, and the counter 6-1 on the H side is decremented by -1. At the stage 1, the number of the bottom register 10-0 on the L side is set, the queue memory 1 is set to the write mode, the number of the top register 9-1 on the H side is written in the pointer section 1-0 thereof, and the valid number is set. Enter the valid R in Part 1-1 and L in Class Part 1-3
Fill in. Then, the counter 6-0 on the L side is incremented by 1.
The bottom register 10-0 on the L side is connected to the top register on the H side.
The number of the register 9-1 is set, and the number read from the pointer unit 1-0 at stage 0, the valid R and the class H are written in the top register 9-1 on the H side. In stage 2, the number newly set in the bottom register 10-0 on the L side is set in the address register 3, the queue memory 1 is set to the write mode, the pointer part 1-0 of the corresponding word is Nill processed, and the valid Valid R in part 1-1
And H in class section 1-3.

Change priority (change from top of class 0 to bottom of class 0, when counter on L side is 2 or more) At stage 0, set number of top register 9-0 on L side to address register 3 and queue The memory 1 is set to the read mode, and the pointer section 1-0 is read.
In stage 1, the bottom of the address register 3 on the L side
The number of the register 10-0 is set, the queue memory 1 is set to the write mode, the number of the top register on the L side is written in the pointer section 1-0 of the relevant word, and the valid section 1-1.
Fill in the valid R and L in the class section 1-3. Further, the number of the top register 9-0 on the L side is set in the bottom register 10-0 on the L side, and the top register 9-0 on the L side is read from the pointer unit 1-0 at stage 0. Enter the number. In stage 2, the bottom register 10-0 on the L side is newly added to the address register 3.
Set the number entered in the queue memory 1, set the queue memory 1 to the write mode, Nill-process the pointer portion 1-0, write valid R in the valid portion 1-1, and L in the class portion 1-3.
Fill in.

When entering data in the cue memory 1, use EC
The C generation unit 4 creates an ECC and writes it in the ECC unit 1-2. When reading data from the queue memory 1, the check correction unit 5 is based on the data written in the ECC unit 1-2. Therefore, the presence or absence of an error and the correction in the case of a 1-bit error are corrected. However, these are well-known methods and are omitted for simplification of description.

〔Example〕

In FIG. 1 (A), the priority classes are "0" (L) and "1".
The configuration of the embodiment in the two cases of (H) is shown.

In general, FIG. 2 shows the configuration when there are n + 1 priority classes. In FIG. 2, the same symbols as in FIG. 1 (A) indicate the same parts.

In this case, as compared with FIG. 1 (A), top registers 9-0, 9-1 ... 9-n and bottom registers 10-0, 10-1 ... 10-n are provided for each class. , Counters 6-0, 6-1 ... 6-n are prepared for each class, and the number of queues for each class is known.

The operation of FIG. 2 is substantially the same as that of FIG.

Further, each control described above is performed by a control unit (not shown), but is omitted for simplification of the configuration.

The present invention is effective in a channel control device and the like, but is not limited to this.

〔The invention's effect〕

According to the present invention, it is possible to manage a processing request from a processing request source having a plurality of priority classes under a complete FIFO in one queue memory, improve the utilization efficiency of the queue memory, and Can be made smaller and the cost can be reduced.

[Brief description of drawings]

FIG. 1 shows an embodiment with two priorities, FIG. 2 shows an embodiment with three or more priorities, FIG. 3 shows a conventional queue memory, and FIG. 4 is an operation explanatory diagram of FIG. FIG. 5 is an explanatory diagram of a queue memory corresponding to a plurality of priorities. 1 ... Queue memory 2 ... Write register 3 ... Address register 4 ... ECC generation unit 5 ... Check correction unit 6-0, 6-1 ... Counter 9-0, 9-1 ... Top register 10-0, 10-1 ... bottom register 11 ... enqueue register

Claims (1)

(57) [Claims] 1. A queue control memory circuit which holds a processing request from a plurality of processing request sources and has a queue section having a pointer portion in which a processing request number to be processed next is written, and which sequentially processes the processing requests. In the above, the queue memory that holds processing requests with different priorities, the top number holding means that holds the top number that is the address number of the queue memory to be processed next for each priority, and the latest processing request number A queue control memory circuit characterized by comprising bottom number holding means for holding a bottom number which is the written address number of the queue memory.