JP2561796B2 - Personal computer system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to personal computers and, more particularly, to a personal computer system having an input / output (I / O) controller that provides flexibility in the design and operation of the system. .

[0002]

2. Description of the Related Art A general personal computer system, particularly an IBM personal computer, has been widely used by exhibiting its function in many fields in modern society. Personal computer·
The system is usually defined as a desk top, floor-standing, or portable microcomputer, and includes one system processor and associated volatile and non-volatile storage elements, display monitor, keyboard device, 1 It consists of a system unit consisting of one or more disk drives, fixed disk storage, and an optional printing device. One of the salient features of these systems is the use of a motherboard or system planar to electrically connect these components together.
These systems basically provide independent computing power to one user, and are designed at a price that can be purchased inexpensively by individuals and small businesses. Examples of such personal computer systems include IBM's personal computer AT and personal system /
2 models 25, 30, L40SX, 50, 55, 56,
57, 65, 70, 80, 90, 95.

These systems are generally divided into two families. One, commonly referred to as the Family I model, primarily uses a bus architecture represented by IBM's personal computer AT and other "IBM compatible" machines. Although this bus architecture is referred to herein as the "AT bus," this bus is also known as the "industry standard architecture" or "ISA."
This bus architecture is well known and is known from IBM.
The company's technical manual, and the more general text WinnRosch Hardwareware Bib
le (Brady, New York, 1989). Therefore, for more detailed information, please refer to the two texts above. In the industrial usage of the term "AT bus", it is often not possible to distinguish between an entire architecture and a particular segment of the architecture (also pointed out below). Similarly, the usage in this disclosure may refer to the entire architecture or to a specific segment of the architecture, so in the following disclosure, care should be taken to discriminate that usage.

Many Family I models are generic Int
An EL8088 or 8086 microprocessor has been used as the system processor. These processors have the ability to address 1 megabyte of memory. Recently, some family I models have high speed microprocessors 80286, 80386
And 80486 are used.

The other family is called the Family II model, which is a personal system / IBM system.
It uses a Micro Channel bus architecture represented by two models 50-95. Family II
Models are typically high speed Intel 80286, 8038
6 and 80486 microprocessors, and for some models these processors
In real mode it is possible to emulate a slow Intel 8086 microprocessor and in protected mode the address range can be extended from 1 MB to 4 GB. That is, 80286, 80386, 80486
The real mode functionality of the microprocessor provides hardware compatibility for software written for the 8086 and 8088. Family II model personal computers are not critical to the present invention, except to illustrate the use of higher performance microprocessors. These microprocessors are also unique in personal computers with AT bus architectures (as described above), despite some technical limitations in their effectiveness due to more limited bus architectures. Has been found to be used.

With the evolution and migration of personal computer technology from 8-bit to 16-bit, and ultimately to 32-bit wide bus interactions and high-speed microprocessors, a wide variety of personal computer architectures have been developed. Attempts have been made to achieve that performance by partitioning it across the bus area. More specifically, in the original IBM PC, what has been known as an expansion bus is essentially a direct extension of a connecting portion of a microprocessor, and a buffer and a demultiplexer are provided if necessary. . afterwards,
As the AT bus specifications have evolved and become widely used, it has become possible to break the almost direct connection between the microprocessor and the bus, resulting in what is known as a local processor bus. What changed its name from the expansion bus to the input / output bus (or I / O bus) was created. Because of the high performance of local processor buses, they typically operate at faster clock speeds (usually expressed in Hertz) than I / O buses.

The AT bus is designed as one of three different buses in the system. The first bus is the local processor bus, which is the system processor or C
A PU, possibly a numerical coprocessor, and a processor support chip are located. The second bus is the input / output or option bus (also known as the AT bus), where the adapter card is located. The third bus is what is referred to herein as the XD bus (also known as the planar I / O bus), and is located between the local processor bus and the AT bus and has some standard I / O controller. Get burned.

[0008]

Further, in the AT architecture of IBM, direct memory access (DM
A) The possibility of running more than one microprocessor on the I / O bus when used for interrupts is allowed. The AT bus usually has a limited number of DMA channels defined. The functions required for the DMA channel are
It is added directly into one or more channels, or is actually wired. The function so provided will take full ownership of the channel, so the DMA
It becomes difficult or impossible to change the channel configuration or share the channel.

[0009]

In order to solve the above problems, the present invention increases flexibility in the construction and allocation of DMA channels and facilitates sharing of DMA channels. This is accomplished by providing a DMA crossbar switch to route the registers to allow the receipt and storage of data indicating allocation of a particular DMA channel to a particular function.
Since the registers are programmable at initial power-up and / or system configuration (such as by a programmable option or POS register), DMA channel assignments can be easily changed at system power-up or as needed. It is possible.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to the accompanying drawings, a personal computer 10 embodying the present invention is shown in FIG.
As described above, the computer 10 includes a monitor 11, a keyboard device 12, and a printing device or plotter 14 which are connected to the computer 10.
It has. The computer 10 includes a cover 1 including an exterior member 16 (FIG. 2) and an inner shield member 18.
5, the cover 15 and chassis 19 combine to form a retracted and shielded body. A data processing component and a storage component which are operated by a power source are housed therein. At least some system components are mounted on the multilayer planar 20 or motherboard. The multi-layer planar 20 is attached to the chassis 19,
It provides a means for electrically interconnecting the components of computer 10 including those identified above and related elements such as floppy disk devices, various forms of direct access storage devices, accessory cards or boards.

The chassis 19 includes a bottom plate 22 and a front panel 2.
4 and a back panel 25 (FIG. 2). The front panel 24 is provided with at least one chamber with an opening (four chambers are shown in the figure), in which data for a disk drive for magnetic or optical disks, tape backup drive, etc. A memory device is accepted. The figure shows a pair of upper chambers 26 and 28 and a pair of lower chambers 2.
9 and 30 are provided.

Before describing the above structure of the present invention, it is considered appropriate to review the general operation of a conventional personal computer, such as personal computer system 10. Figure 3 shows the conventional personal
1 is a block diagram of a computer system in which various components according to the present invention, such as system 10, are depicted. These components include those mounted in the planar 20 and I / O slots and connections of the planar to other hardware in this computer. The system processor 32, which is a microprocessor, is connected to the planar and is further connected to the memory control unit 36 via the bus control timing unit 35 by the high speed local processor bus 34,
The memory control unit 36 is a volatile random
It is connected to access memory (RAM) 38. Any suitable microprocessor can be used, but one preferred example is the Intel 8038.
6 is mentioned.

The invention will be described hereinafter mainly with reference to the block diagram of the system according to FIG. 3, but before that, the device and method according to the invention can be used in other hardware configurations of a planar board. Please understand that it is supposed to be. For example, the system processor is Intel's 80286 or 80386.
A microprocessor is also possible. In particular, in the following description, when the system in the personal computer 10 according to the present invention is different from the arrangement shown in FIG. 3, that fact is pointed out.

Returning to FIG. 3, local processor bus 34 (comprising data, address, and control buses).
Is a microprocessor 32, a numerical operation coprocessor 3
9, the cache control device 40, and the cache memory 41 are connected. In addition, local processor
A buffer 42 is connected to the bus 34. The buffer 42 is connected to the slower system bus 44 (compared to the local processor bus) and again consists of a data, address and control bus. System bus 44
Extends from buffer 42 to buffer 68. It is also connected to the bus control timing unit 35 and the DMA unit 48. The DMA unit 48 comprises a central arbitration unit 49 and a DMA controller 50. The buffer 51 interfaces between the system bus 44 and an optional function bus 52 such as an AT bus. Adapter cards are inserted into the plurality of input / output slots 54 connected to the bus 52, and they are further connected to input / output devices or memories.

The arbitration control bus 55 is used for the DMA controller 50.
The central arbitration unit 49 is connected to the input / output slot 54 and the diskette adapter 56. The system bus 44 is also connected to the memory control unit 36, which consists of a memory controller 59, an address multiplexer 60, and a data buffer 61. The memory control unit 36 is further connected to the RAM represented by the RAM module 38. The memory control unit 36 has logic for associating (mapping) the microprocessor 32 and the address of a specific area of the RAM 38. This logic is used to reclaim the RAM before it is occupied by the BIOS. In addition, the ROM select signal (ROMSEL) generated by the memory control unit 36 is used to enable or disable the ROM 64.

Personal computer system 10
Although a basic 1 MB RAM module is shown in Figure 3, additional memory can be connected to each other as represented by optional memory modules 65-67 in Figure 3. For ease of explanation, the present invention will be described by a basic 1 MB memory module 38.

Latch buffer 68 connects system bus 44 to planar I / O bus 69. The planar input / output bus 69 comprises address, data, and control buses. A display adapter 70 (used to drive the monitor 11) along the planar I / O bus 69.
Various I / O adapters and other parts, CMOS clock 72, non-volatile CMOS RAM 74 (hereinafter NVRA)
RS232 adapter 76, parallel adapter 78, timers 80, diskette adapter 56, interrupt controller 84, and read only memory (ROM) 64. ROM64 is BIO
S, which interfaces the I / O bus with the operating system of the microprocessor 32. The BIOS stored in ROM 64 can be copied into RAM 38 to reduce its execution time. In addition, ROM 64 responds (via the ROMSEL signal) to memory controller 59. When the ROM 64 is enabled by the memory control unit 36, the BIOS is executed from the ROM. When disabled, the ROM does not respond to address inquiries from the microprocessor 32 (ie, the BIOS is R
Run from AM).

The planar input / output bus 69 described below is
It includes a portion defined by the conductive paths formed in the inner layers of the multilayer planar 20. In particular, many of such paths have a portion extending to the end of the planar 20, and the end of the planar 20 is extended and installed close to either the front or rear panel of the chassis. Because of the planar design, many I / O connectors can be placed along the side edges of the planar to exchange signals with devices such as monitors, keyboard devices, and printing devices. .

As mentioned above in the description of the technical field of the invention, the local processor bus 34 is provided with a system processor or CPU, optionally a numerical coprocessor, and a processor support chip. . An adapter card is located on the input / output or option bus (also known as the AT bus) 52. The planar input / output bus 69 is also called an XD bus. The interface specifications for each of these three buses differ from each other, which is well known to computer system designers working with AT bus specifications.

An important and salient feature of the present invention is the use of an I / O controller connectable via either a planar I / O bus 69 or an I / O or option bus (also known as an AT bus) 52. That is. Such an input / output control device is shown in FIG. Attention will now be given to the description of this controller and the difference between the general structure of the computer 10 of FIGS. 1 and 2 and that of the prior art computer of FIG.

In particular, the I / O controller 80 (FIG. 4) of the present invention includes an interface 81 for serial port connection that replaces the original RS232 port 76, and a parallel interface that replaces the original parallel port connection 78. An interface 82 for port connection is provided.
In the field of expertise, it is often the case that a serial port sends data signals by means of bits and bytes that flow sequentially in series, and a parallel port sends data signals with all the bits in a byte flow in parallel. It is known. Serial and parallel interfaces have been standardized in the personal computer industry, and their port characteristics are well established and well known.

Further, the input / output controller 80 is a bus interface 8 to which an AT bus or XD bus can be connected.
4, which allows the placement of input and output datapaths to be substantially changed using only a single component. In particular, by using only one type of input / output control device 80, it is possible to effectively connect any input / output device using serial or parallel connection via any of the above-mentioned buses. Yes, and there is no need to redesign other elements of the system for that.

The I / O controller 80 further includes a counter segment 85, a C2 security interface,
It has a segment 86, a DMA crossbar switch segment 88, an interface segment 89 to the RTC and NVRAM, and an interface 90 for chip test.

This interface is designed to exchange signals with multiple signal lines, as shown next to the segment in the segment connection portion of the bus interface 84 of FIG. These signal lines are the AT bus 52 and the planar input / output bus (here, the XD bus 69).
It is determined by the publicly available specifications. Further, the input / output control device 80 is
It has one line called "k" (or "feedback"), which is connectable to the bus controller 35. The Fdback signal line is the input / output control device 8
It is an output from 0 and an input to the bus controller 35. And, if connected, provided to the bus controller to identify that the device accessed via the I / O controller 80 has data to be sent over the planar I / O bus 69. To be Therefore, the I / O controller 80 according to the present invention is used in the planar I / O bus 69
Fdbac when installed by connecting to
k signal lines are connected and used.

The flexibility of the I / O controller 80 of the present invention results from the fact that it can be installed directly on the AT bus 52 as well. In that case, simply Fdbac
Appropriate functions can be obtained simply by not connecting the k signal line. If such a connection change were to be made by another device, it would be necessary to make a major change to the bus controller 35. The present invention eliminates the need for such modification of the bus controller 35.

Since the Fdback signal line is driven by an open collector driver, other chips can be simultaneously (as needed or appropriately) connected to the planar I / O bus 69 to which the I / O controller 80 is connected. .

A particularly important segment in the present invention is
A DMA crossbar switch segment 88, a more detailed schematic diagram (for a representative portion of either or both serial and parallel port interfaces 81, 82) is shown in FIG. The function of the crossbar switch segment 88 is to allocate DMA channels according to the data stored in the POS port routing register 91.

In particular, the serial and parallel port functions instructed via the input / output control unit 80 are universally used.
Requires one DMA channel. Input / output control device 80
5 DMs connected to the DMA unit 48
An A channel connection unit is provided, and the input / output control device 8
The signal sent to 0 is the POS port routing register 9
Directed to the DMA channel by crossbar switch segment 88 as directed from 1. As a result, the data provided to register 91 may be set at system startup (from configuration information stored in CMOS RAM or NVRAM, etc.) or dynamically by software using serial and parallel ports. You may set it.

In normal operation, the input / output controller 8
0 External DMA signal pair DACK # (0..4) and DR
EQ (0..4) is tri-enabled until correctly enabled through POS register and desired I / O function.
Have a state. If the software you are using does not use any of the I / O controller functions, the POS
It is not necessary to change the register 91 from the tri-state at the time of starting. In this case the software must take care not to put the serial or parallel port in DMA mode.

If the I / O function wants to use a particular DMA channel without changing the start-up state of register 91, the hardware system designer may
Care must be taken in the S configuration and proper DMA channel connection must be made.

The AT bus has seven DMA channels, but (in one working embodiment of the invention) the I / O controller has only five pairs of connections. Thus, the hardware system designer may connect five pairs of I / O controllers 80 to a minimum of five AT bus channels that may use them. It will reduce the potential for contention with other devices trying to use some of the available DMA channels.

If the software uses any of the functions of the I / O controller, first of all the AT bus DMA
You must decide if the channel is desirable to use. Then, by considering the system design logic, the programmer can determine which external pair the target AT bus D
It can be decided whether it should be connected to the MA channel. After the internal DMA signals in I / O controller 80 are properly routed, the port function is put into DMA mode,
The crossbar switch portion of the input / output control device 80 is transparent to its function.

Two or more internal DMA signal pairs from serial and parallel ports can be replaced by the same external DMA signal pair (DMA).
The I / O controller 80 acquires the DMA share by routing to ACK0-4 and DMA REQ0-4). In this case, ACKnowled of the external DMA
The ge signal (acknowledgement signal) will be routed to both (or more) functions sharing that channel. Further, the REQuest signal (request signal) of the external DMA is the R of the internal DMA generated by each sharing function.
It is the logical "or" of EQuest. Internal to external DMA routing can be changed immediately by modifying the appropriate POS routing registers.

The results obtained are similar to those obtained in microchannel operation with arbitration. However, it was obtained with a crossbar switch that was completely different from arbitration, within the limits imposed by the AT bus architecture.

[0035]

According to the present invention, a DMA channel is provided by providing a DMA crossbar switch to route registers to enable reception and storage of data indicating allocation of a particular DMA channel to a particular function. Flexibility in configuration and allocation of
Channel sharing becomes easier.

[Brief description of drawings]

FIG. 1 is a perspective view of a personal computer embodying the present invention.

2 is an exploded perspective view of some of the elements of the personal computer of FIG. 1 including a chassis, a cover, an electromechanical direct access storage device, and a planar board, showing the relationships between those elements.

FIG. 3 is a schematic diagram showing a configuration of a conventional personal computer similar to the configurations of FIGS. 1 and 2.

4 is a partial replacement of the configuration outlined in FIG.
3 is a schematic view of an input / output control device according to the present invention used in the computer of FIGS. 1 and 2.

FIG. 5 is a schematic view of a segment including an input / output control device showing an example of an environment using the present invention.

[Explanation of symbols]

 10 personal computer system 11 monitor 12 keyboard device 14 printing device 15 cover 19 chassis 20 planar board 32 microprocessor 34 local processor bus 35 bus control (timing) device 36 memory control unit 42 buffer 44 system bus 48 DMA Unit 51 Buffer 52 Option Bus (AT Bus) 54 Input / Output Slot 64 ROM 68 Latch Buffer 69 Planar Input / Output Bus (XD Bus) 76 RS232 Adapter (RS232 Port) 78 Parallel Adapter (Parallel Port) 80 Input / Output Control Device 81 Serial interface 82 Parallel interface 84 Bus interface

 ─────────────────────────────────────────────────── ————————————————————————————————————————————————————————————————————————————————————————————————————————————–————————— Photo # 7 # 2 of 5th Floor, Don't miss it! Raton No. 225, Olive Wood Place 301 (72) Inventor Roy E. Snidou, Jr. United States 33322 Northwest 28th Street, San Rise, Florida 10900 (56) Reference JP-A-2-278361 (JP , A)

Claims (6)

(57) [Claims] 1. A high speed local processor bus for sending data signals, a microprocessor connected to the bus for transferring data signals over the local processor bus, and an option card. An option bus for passing data signals to and from the option card, a planar I / O bus for sending data signals, and the planar operation by operation to receive, store and allow access to data. A random access memory connected to the I / O bus, and the planar I / O bus and the random access memory operatively to control direct access to the random access memory by system elements other than the microprocessor. Connected to a certain number of DMAs
A DMA controller for defining a channel, a first segment that is a serial port for exchanging data signals with the planar input / output bus, and a parallel segment for exchanging data signals with the planar input / output bus.
A second segment, which is a port, and the predetermined number of DMs
A plurality of segments which are connected to the A channel and which are DMA switches provided in the DMA controller and which are selectively connectable to the first and second segments; Of the first segment and the second segment of the DMA
And an input / output controller having a register for receiving data indicating whether the channel is connected to the channel, and the data stored in the register allows the serial and parallel port A personal computer system that determines a connection to the DMA channel. 2. The input / output control device comprises the option
2. The personal computer system according to claim 1, wherein the personal computer system is directly connected to the bus. 3. The I / O controller is directly connected to the planar I / O bus.
The personal computer system described. 4. The registers of the I / O controller are set to a predetermined state when the computer system is booted to provide a predetermined connection in the interconnection between the DMA channel and the serial and parallel ports. The personal computer system of claim 1, which constructs a pattern. 5. The register of the I / O controller is set to a selected state by the operation of software on the computer system so that the DMA channel and the serial and parallel ports can interact with each other. The personal computer system according to claim 1, which constructs a predetermined pattern of connection. 6. A high speed local processor bus for sending data signals, a microprocessor operably connected to the bus for transferring data signals over the local processor bus, and an option card. Bus for receiving and transmitting data signals to and from the option card, a planar I / O bus for sending data signals, the local processor bus, the option bus, and the planar I / O bus A bus controller connected to the three buses for controlling the passing of data signals between the microprocessor and the microprocessor; and a serial port for exchanging data signals with the local processor bus. Segment of
A second segment which is a parallel port for exchanging data signals with the local processor bus; and D
A third segment including a DMA switch connected to a predetermined number of DMA channels provided in the MA controller and selectively connectable to the first and second segments, and the third segment being the third segment. An I / O controller having a register for receiving data indicating which one of the first segment and the second segment is connected to the DMA channel, the data being stored in the register. A personal computer system for determining connection of serial and parallel ports to the DMA channel via the I / O controller.