JP2560435B2 - A-D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention performs high-accuracy by performing A / D conversion of a low bit number at a sampling rate which is considerably faster than the signal band and passing a digital filter at the output. The present invention relates to a so-called oversampling A-D converter that realizes A-D conversion.

(Prior Art) A delta-sigma type AD converter is more efficient because the noise spectrum is distributed more in the high frequency region as the order of the filter in the conversion loop is higher, and the noise in the signal band is reduced. Are known. However, it is difficult to realize a high-order ideal filter characteristic.
A converter having a bit quantizer and a loop filter of third order or higher is unstable and has not been realized. As a method of eliminating this instability, the transfer characteristics of the multi-order noise shaping AD converter are equivalently realized by continuously connecting the primary noise shaping AD converters in multiple stages and synthesizing each output code. A so-called MASH converter is known. Hayashi et al. In 1986 for the two-stage type, ISSCC Digest of Technical Papers, Matsuya et al. In 1987 for the three-stage type. Papers (ISSCC Digest of
Techical Papers) and JP-A-61-177819, the details of the operation are omitted.

(Problems to be Solved by the Invention) Conventionally, MASH type AD converters have been realized up to the third order. The analytical transfer function suggests that the performance can be further improved by increasing the number of unit delta-sigma modulators connected in cascade to four or more, but in reality, the converter does not operate stably. This is because the unit delta-sigma modulator is a converter that is premised on that the input voltage does not exceed the output of the internal 1-bit DA converter. Even in the case of the three-stage configuration, there is a sign that it does not operate stably. FIG. 7 shows the configuration of a three-stage MASH converter, and FIG. 8 shows a circuit for combining three outputs. Three
In the staged MASH circuit, unit delta-sigma modulators 72 enclosed by the broken line in FIG. 7 are connected in three stages. The input of the rear stage uses the input of the comparator of the front stage. The output of the comparator 70 is synthesized by a circuit using the differentiating circuit 80 shown in FIG. The transfer characteristics of the output are Y (z) for the combined output and X (z) for the input.
If the quantization noise is Q (z), Y (z) = X (z) +
A third-order noise shaping characteristic represented by (1-Z ^-1 ) ³ Q (z) should be realized.

However, in the case of this configuration, for example, when the input signal voltage of the first stage is ½ of the maximum input amplitude, it reaches 1.5 times the quantization voltage in the second stage and about 2.5 times or more in the third stage. This can be confirmed by simulation. Fig. 9 shows that the input signal is 0.00 against the maximum input level.
1st stage input signal when the sine wave is 1, 2nd stage input,
The third stage input waveform is shown. In addition, a Hanning window is applied to the output code synthesized by the circuit of FIG. 8 in FIG.
It is an FFT spectrum. Oversampled A-
In the D converter, the spectrum of the conversion output is often distributed in the signal band particularly for a small input signal, so that the frequency of 1/32 of the sampling frequency is 1 / of the step size.
A square wave signal with an amplitude of 4 is superimposed on the input sine wave signal. FIG. 11 shows a signal waveform similar to that of FIG. 9 when the input signal is 0.5, and FIG. 12 shows an output signal spectrum similar to that of FIG. As can be seen from Fig. 11, the comparator input voltage in the third stage cell has increased to more than ten times the step size, and this excessively accumulated voltage is the unit delta sigma modulator of the third stage. It takes a considerable sampling period to return to a voltage near the equilibrium point at the comparator input position due to the feedback action of. That is, 1 or 0 continues in the output code over a long period.
If the output code is 1 or 0 continuously for a long time, it means that the noise shaping effect is hindered during this sampling period. Actually, this effect appears in the spectral distribution of the output signal in FIG. 12, and the noise in the low frequency region is larger than that in the small signal input in FIG. The purpose of this type of AD converter is to obtain a high signal-to-noise ratio by filtering the output code through a digital filter and extracting only low-frequency components. Become.

An object of the present invention is to provide an A / D converter which eliminates such drawbacks, operates stably even in a configuration of four or more stages, and can obtain a good signal-to-noise ratio even when the input signal is large. Especially.

(Means for Solving the Problem) The present invention provides a signal input terminal, a 1-bit DA, and a signal output from the 1-bit DA converter input from the signal input terminal. The outputs of the means for accumulating the difference and the means for accumulating are compared with a predetermined reference voltage, and the magnitude is output as a digital value of 1 and 0, and also output to the DA converter. Use a plurality of unit delta-sigma modulators composed of comparators connected in cascade
A D converter for transmitting the accumulated result of the unit digital sigma modulator to the input of the next stage after being attenuated by half and adding the respective comparator outputs of the unit delta sigma modulator It is characterized by taking an n-1 order difference for the data at the time of continuous sampling with respect to the nth output and adding a value multiplied by 2 ^n-1 .

(Example) The present invention will be described in detail by taking the case where n is 4 as an example. FIG. 1 shows a four-stage type noise shaping circuit including a circuit for synthesizing output codes. In this figure, the voltage division of 1/2 is written where the analog signal outside the feedback loop is transmitted to the next stage to make the figure easier to see, but the voltage division of 1/2 is compared in the feedback loop. The characteristics are the same even in front of the vessel 10. In terms of circuitry, it is easier to implement. In the conventional multi-stage delta-sigma modulator, deterioration of characteristics occurs because the amplitude of the signal transmitted to the next stage exceeds the voltage of the internal DA converter. The internal voltage of the primary noise shaping circuit is within twice the step size unless the input amplitude exceeds the step size. There
By dividing the transmitted signal voltage to 1/2 the voltage of each stage, the transmitted signal voltage will not exceed the quantized voltage of each stage, and the operation should be stable. To divide the voltage by 1/2, the ratio of the capacitance of the feedback capacitor of the integrator to the capacitance of the signal input capacitor may be set to 2: 1 as shown in FIG. When the signal voltage to be transmitted is divided, it is also necessary to change the transfer function for synthesizing the output pulses and equivalently realizing the multi-order noise shaping characteristic. For this signal type, Y ₁ digital output of the first stage, the second stage digital output Y _2, 3-stage digital output Y _3, when the output Y ₄ digital fourth stage, the fourth-order 8 (1-z ^-1 ) ³ Y ₄ + 4z ^-1 (1-z ^-1 ) ² Y ₃ + 2z ^-1 (1-z ^-1 ) Y ₂ + z ^-1 to realize the transfer characteristics of delta-sigma modulation the _{Y 1 = X 1 + 8Q 4} (1-z -1) 4. The circuit that realizes this left side is the portion surrounded by the broken line in FIG. 1 (data synthesizing circuit 12).

The root mean square value of the noise voltage in the signal band obtained by this transfer function is f _{B for} the signal band and f _{B for} the sampling frequency.
s, where Δ is the voltage of the 1-bit DA converter, Is. here It is represented by. Although this noise voltage is 8 times more noisy than when the 4th-order delta-sigma modulator operates ideally, the fs and 2f _B ratio is at least 32 times, so the 3rd-order delta-sigma modulator is The characteristics are improved significantly.

When connecting N stages, the transfer function is Therefore, it can be configured similarly to the case of the fourth order.

(Effects of the Invention) By using the present invention, the analog signal input to each unit delta-sigma modulator does not exceed the voltage fed back by the DA converter. FIG. 3 is a diagram showing the waveform of each part when a minute input sine wave is used, and FIG. 4 is a spectrum obtained by performing FFT on the combined output. Fourth
In the figure, the first peak from the left is the spectrum of the input signal, and the second is the spectrum of the superimposed square wave. FIG. 5 is a diagram showing the waveform of each part when a sine wave having an amplitude half that of the maximum input is input, and FIG. 6 is a spectrum obtained by performing an FFT on the combined output. In FIG. 6, the first peak from the left is the spectrum of the input signal, and the second is the spectrum of the superimposed square wave. As can be seen from FIG. 5, the phenomenon that the internal signal becomes large, which was a problem in the conventional method, disappears, and the noise spectrum in the vicinity of the signal becomes very small as shown in the FFT result of FIG. 6, A good signal to noise ratio can be obtained. In this case, when the input signal is large, the signal-to-noise ratio is improved by about 20 dB compared to the conventional one.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a four-stage delta-sigma modulator that is an embodiment of the present invention. FIG. 2 is a diagram showing an example of an integrating circuit when implementing the present invention. FIG. 3 is a waveform diagram simulating the internal voltage waveform when a minute sine wave is input to the circuit of FIG. FIG. 4 is a spectrum diagram obtained by performing FFT on the output when the simulation of FIG. 3 is performed. FIG. 5 is a waveform diagram simulating the internal voltage waveform when a sine wave of 1/2 of the maximum input signal is input to the circuit of FIG. FIG. 6 is a spectrum diagram obtained by performing FFT on the output when the simulation of FIG. 5 is performed. FIG. 7 is a circuit configuration diagram of a multi-stage delta-sigma modulator according to the related art. FIG. 8 is a circuit diagram for synthesizing the digital outputs of FIG. FIG. 9 is a waveform diagram simulating the internal voltage waveform when a minute sine wave is input to the circuit of FIG.
FIG. 10 is a spectrum diagram obtained by performing FFT on the output when the simulation of FIG. 9 is performed. 11th
The figure is a waveform diagram simulating the internal voltage waveform when a sine wave of 1/2 of the maximum input signal is input to the circuit of FIG. FIG. 12 is a diagram of a spectrum obtained by performing FFT on the output when the simulation of FIG. 11 is performed. The numbers in the figure indicate the following. 10, 70 Comparator, 12 Data synthesis circuit, 72 Unit delta-sigma modulator, 80 Differentiation circuit.

Claims (1)

(57) [Claims] 1. A signal input terminal, a 1-bit D / A converter, and a difference between a signal input from the signal input terminal and a signal output from the 1-bit D / A converter is accumulated. And a comparator for comparing the output of the accumulating means with a predetermined reference voltage and outputting the magnitude as a digital value of 1 and 0 and also for outputting to the DA converter. A plurality of unit delta-sigma modulators are connected in cascade, and the accumulated result of the unit delta-sigma modulator is attenuated by half and transmitted to the input of the next stage, and When the comparator outputs of the unit delta-sigma modulator are added together, the n-1th order difference is taken for the data at the time of continuous sampling for the nth output and the value multiplied by ^2n-1 times is added. A-D change characterized by Vessel.