JP2558793B2 - EEPROM drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an EEPROM including a booster circuit and a voltage control circuit.
(Electrically Erasable and Programmable ROM) drive circuit, especially to improvement of voltage control circuit.

(Prior Art) As shown in FIG. 6, a conventional voltage control circuit of this type has a voltage corresponding to the number of connected stages, for example, by connecting one or more stages in which gates and drains of MOS transistors are commonly connected. The level of the applied voltage is clamped to the control value for control. That is, in the circuit shown in FIG. 6, when the control start point is time To as shown in FIG. 7 and a voltage as shown by the alternate long and short dash line is applied to the terminal OUT,
The voltage is controlled to the voltage control value L2 as shown by the solid line.

Such a voltage control circuit is connected to the output terminal of a circuit whose amplified output changes depending on the input condition, such as a voltage amplifier, and controls the output voltage of the amplifier when the output voltage becomes excessive due to the input condition. It is used for applications such as controlling and reducing the load on the circuit connected to the subsequent stage.

(Problems to be Solved by the Invention) In the conventional voltage control circuit as described above, once the voltage control value is determined, the voltage control value is fixed to that value, and the voltage control value is changed according to the situation. I can't do it. Furthermore, the time required for the controlled voltage to reach the control value is determined by the output characteristics of the circuit in the preceding stage, and the voltage control circuit itself cannot control the time until it reaches the voltage control value. Therefore, in a circuit connected to a subsequent stage of a circuit that outputs a relatively high voltage, a high voltage may be suddenly applied and the transistors and the like therein may be destroyed. For example, when it is used in a drive circuit for an EEPROM as shown in FIG. 8, the high voltage generated from the booster circuit 1 is applied to the EEPROM cell 3 through the voltage control circuit 2 to perform writing and erasing. At this time, when the conventional voltage control circuit is used, a high voltage is instantaneously applied to the EEPROM cell having the thin oxide film (gate insulating film) a in the tunnel region as shown in FIG. Will destroy.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an EEPROM drive circuit capable of preventing destruction of a thin insulating film of an EEPROM cell.

[Structure of Invention]

(Means for Solving the Problem) In order to achieve the above object, an EEPROM drive circuit of the present invention is an EEPROM drive circuit that generates a high voltage output for writing / erasing data to / from an EEPROM memory cell. ,
A level clamp circuit capable of clamping the high voltage output to a plurality of voltage levels, and controlling the level clamp circuit to temporarily suppress the rising of the high voltage output to an intermediate voltage level of the plurality of voltage levels, And a clamp control circuit for preventing dielectric breakdown of the gate insulating film of the memory cell.

(Operation) In the above configuration, the high voltage output (absolute value) rises by controlling the level clamp circuit connected to the high voltage output line that writes / erases data to / from the EEPROM memory cell. In, the voltage is increased via the clamp to the intermediate voltage, and is temporarily suppressed so that the rising characteristic does not become abrupt.

As a result, abrupt high voltage generation is avoided, and destruction of the insulating film of the EEPROM cell, especially the thin gate insulating film, is prevented.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.

As shown in the circuit diagram of FIG. 1, an enhancement type N
The gate and drain of the channel-type voltage control MOS transistor T1 are connected in common, and this is connected to the terminal OUT.
The controlled voltage, that is, the output voltage of the preceding circuit (not shown) is applied to this terminal OUT. The source of this first-stage transistor T1 is the same-type voltage control MOS of the next stage.
Connect to the common connection point of the gate and drain of transistor T2. Similarly, the same type of voltage control MOS transistor T
3, T4 and T5 are connected to form a basic circuit consisting of five-stage connection of MOS transistors.

Next, at the potential reference points of the transistors T1 to T5 of each stage, that is, three points A, C and E of the source points A to E in this embodiment, the depletion type N channel type switching MO is respectively provided.
The drains of the S transistors T6, T7, and T8 are connected. Then, the control signals V _x , V _y , and T of different timings are applied to the respective gates of these switching transistors T6, T7, T8.
V _z is applied, and the power supply voltage V _CC is applied to the source. In this way, the level clamp circuits (T1 to T8) are constructed.

In order to generate the gate control signals V _x , V _y , V _z at different timings, for example, the following clamp control circuit is provided (not shown). For example, two binary counters are connected, and three terminals, that is, an input terminal and an output terminal of the first-stage counter and an output terminal of the second-stage counter are provided corresponding to the switching transistors T6, T7, and T8, respectively. Three of three
Connect to each input terminal of the input decoder. Status values from "000" to "111" appear on the three terminals of the two-stage counter as the counting progresses. When the state value matches the set value of each decoder, the output of the matched decoder becomes "1" and the output of the other decoder becomes "0".

The output level of each decoder is set so that the output "1" of each decoder becomes the power supply potential V _CC and the output "0" becomes the non-conducting gate potential V _{SS of the} switching transistor. Then, added their three outputs of the decoder gates control signals V _x, V _y, as V _z, the corresponding gates of the switching transistors T6, T7, T8. The gate control signals V _x , V _y , and V _z are set according to the setting method of each decoder.
Timing is set.

 Next, the operation of this embodiment will be described.

Now, it is assumed that the voltage indicated by the alternate long and short dash line is applied to the terminal OUT with the time t0 as the control start point as shown in FIG. At this time, as shown in FIG. 2, the gate control signal of the switching transistor T6 is provided from time t0 to time t1.
Only V _x is the power supply potential V _CC , and the other gate control signals V _y and V _z are held at the non-conducting potential V _SS . Then, since the switching transistor T6 becomes conductive, the power supply potential V _CC is applied to the source point A of the first-stage transistor T1. Therefore, the terminal OUT
And the power supply potential V _CC are applied to the first-stage transistor T1. Since the first-stage transistor T1 is in the saturation region, the potential of the terminal OUT is VGS ≧ VTH + ΔVTH (1) VGS: Gate-source voltage VTH: Threshold voltage is not satisfied for this transistor 1. Settle down to the potential. That is, terminal OU
The potential of T is set to L ₀ = V _CC + V TH1 + ΔV TH1 (2) V TH1: The voltage control value L ₀ indicated by the threshold voltage of the first-stage transistor T1 (see FIG. 3).

Next, from time t1 to t2, only the gate control signal VY of the switching transistor T7 is set to the power supply potential V _CC ,
The other gate control signals V _x and V _z are set to the non-conducting potential V _SS . Then, the switching transistor T6 that was conducting until now
Becomes non-conductive, the potential at the source point A of the first-stage transistor T1 rises above the power supply potential V _CC . at the same time,
Since the switching transistor T7 is in the conductive state, the potential of the terminal OUT is the same as in the case of the transistor T1 described above.
The potential at which the condition of equation (1) is not satisfied, that is, VTHn: Determined to the voltage control value L1 indicated by the threshold voltage of the n-th stage transistor Tn (see FIG. 3).

Next, after the time t2, the switching transistor T8
Of the gate control signal V _z is set to the power supply potential V _CC , and the rest is set to the non-conduction potential V _SS . Then, similarly to the above, the potential of the terminal OUT is set to the transistors T1 to T5 of the first to fifth stages.
The potential at which the condition of equation (1) is not satisfied, that is, Is determined by the voltage control value L2 indicated by (see FIG. 3).

In this way, each switching transistor T6, T7, T8
As shown in FIG. 3, gate control signals VX, VY, and VZ are added with a staggered timing as shown in FIG. 2 to gradually increase the voltage to the voltage L2 via the level clamp to the intermediate voltages L0 and L1. Turn on the voltage control value. This makes it possible to control the stage of the intermediate voltage and the rise time from the initial potential to the final voltage control value L2 in synchronization with the generation of the high voltage, and suppress the rapid generation of the high voltage.

Further, as shown in FIG. 3, not only is it changed in three steps, but the timing of the gate control signals VX, VY, VZ is freely changed as shown in FIG. It is also possible to control the voltage control value in two steps.

As described above, according to the present invention, the potential of the potential reference point of each stage transistor of the level clamp circuit is changed to set the change pattern of the voltage control value. Therefore, the type of switching transistor and the condition of the power supply connected thereto are As described in the above embodiment, it does not matter as long as the operating point is moved in the direction in which the condition VGS ≧ 2VTH + ΔVTH is not satisfied for each stage transistor above the point where the switching transistor is connected. Therefore,
Not only the embodiment shown in FIG. 3, but also an embodiment in which enhancement type N-channel type MOS transistors T9, T10, T11 are used as switching transistors and each source is connected to ground as shown in FIG. And so on.

In the above embodiment, the voltage control transistor is 5
Although the case has been described in which three switching transistors are connected in stages, the present invention is not limited to this. The number of switching transistors is determined by the number of voltage control values. Further, although the MOS transistor is used as the voltage controlling transistor in the above embodiment, it is needless to say that another type of transistor may be used and another switching element may be used instead of the switching transistor. .

Such a voltage control circuit has an EEPR as shown in FIG.
It is used in the drive circuit of the OM, and if the intermediate level up to the final control value and the time axis are controlled so as to temporarily suppress the sudden application of high voltage by changing the voltage control value stepwise, it is shown in FIG. It is possible to prevent a high voltage from being suddenly applied to the thin oxide film (gate insulating film) in the tunnel region a of the EEPROM shown, and to prevent the oxide film from being destroyed.

〔The invention's effect〕

As described above, according to the drive circuit of the EEPROM of the present invention, the level clamp circuit connected to the high voltage output used for writing / erasing the memory cell of the EEPROM is configured to enable clamping to a plurality of levels. Since the level clamp circuit is controlled to suppress the rising of the high voltage output to the intermediate voltage for a time, it is possible to prevent the gate insulating film of the memory cell transistor from being destroyed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration example of a level clamp circuit of an EEPROM drive circuit according to the present invention, and FIG. 2 is an example of a gate control signal applied to a switching transistor of the level clamp circuit shown in FIG. FIG. 3 is a waveform diagram showing the change over time of the controlled voltage when the gate control signal of FIG. 2 is applied to the level clamp circuit. FIG. 4 is another waveform diagram of the level clamp circuit. FIG. 5 is a waveform diagram showing an example of the gate control signal and the time change of the controlled voltage at that time, FIG. 5 is a circuit diagram showing another embodiment of the present invention, and FIG. 6 is a level used in a conventional EEPROM drive circuit. Clamp circuit, FIG. 7 is a waveform diagram showing the time variation of the controlled voltage in the conventional example, FIG. 8 is a block diagram showing the voltage control circuit when connected to the drive circuit of the EEPROM, and FIG. 9 is In cross section of EEPROM cell That. Explanation of symbols T1 to T5 …… voltage control MOS transistors, T6 to T11 …… switching MOS transistors, A to E …… potential reference point of each stage voltage control transistor, VX, VY, VZ, VU, VV, VW: Gate control signal.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kenji Toyoda 25-1 Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microcomputer Engineering Co., Ltd. (56) Reference JP-A-62-275395

Claims (3)

(57) [Claims] 1. Writing data to a memory cell of an EEPROM
An EEPROM drive circuit for generating a high voltage output for erasing, comprising: a level clamp circuit capable of clamping the high voltage output to a plurality of voltage levels; and a rise of the high voltage output by controlling the level clamp means. And a clamp control circuit that temporarily suppresses the voltage to an intermediate voltage level of the plurality of voltage levels to prevent dielectric breakdown of the gate insulating film of the memory cell, and an EEPROM drive circuit. 2. The clamp control circuit controls the level clamp circuit to temporarily suppress the rising of the high voltage output in a stepwise manner via clamping to a plurality of voltage levels. An EEPROM drive circuit according to claim 1. 3. The drive circuit for an EEPROM according to claim 2, wherein the control of the level clamp circuit is performed in synchronization with the generation of the high voltage output.