JP2557228B2 - Failure analysis device for elevator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention, when controlling an elevator using a microcomputer, accumulates a change in data such as a control signal based on a calculation cycle to analyze an elevator failure. The present invention relates to a failure analysis device.

[Prior Art] A conventional device of this type is known, for example, as disclosed in Japanese Patent Laid-Open No. 61-86376, which holds a state at the time of an accident and outputs the state to an external device.

FIG. 4 shows a schematic configuration of an elevator control device for controlling an elevator traveling on a plurality of floors by a microcomputer. In FIG. 4, (1) is an elevator car, (2) is a counterweight, (3) is a rope wound around the sheave (4), and a car ( 1) and the counterweight (2) are connected. Further, (5) is an electric motor for driving the sheave (4), and (6) is a microcomputer for performing speed control calculation and the like.

FIG. 5 is a block diagram showing a detailed configuration of the microcomputer (6). An input port (6a) for inputting signals such as calls generated in the elevator car (1) shown in FIG. 4, an output port (6b) for outputting a speed control command to the electric motor (5), and a CPU (6c) , ROM (6d), RAM (6
e).

ROM (6d) and RAM (6e) are respectively coupled to CPU (6c), and CPU (6c) has input port (6a) and output port (6b)
Data is exchanged with the keyboard (7) and the printer (8) via the. ROM by input from keyboard (7)
A program for outputting the designated storage area (6e) to the printer (8) is stored in the ROM (6d), and can be processed by the CPU (6c).

Next, a method of accumulating data for each calculation cycle (hereinafter referred to as tracing) will be described. Elevator control signals include start commands and designated commands, and these signals are represented by "0" or "1" inside the computer. This 8
Handled as bit OOH to FFH data. These data are stored in the RAM (6e). For example, when tracing data for 8 cycles, data consisting of OOH or FFH is represented by "0" or "1", and this 1-bit data is traced for 8 cycles to form 8-bit trace data.

FIG. 6 shows such 8-bit trace data. Eight bits from D0 to D7 are prepared, and the data of the latest operation cycle is stored in the D0 bit. Then, the data is shifted to the left as the calculation progresses. As a result, the D7 bit data becomes the oldest and the D0 bit data becomes the newest.

In this way, trace data for 8 cycles is created. Next, the tracing method will be described in detail with reference to the flowchart shown in FIG. Prior to the explanation, the RAM shown in Fig. 5
The data structure of (6e) will be briefly described with reference to FIG. In FIG. 9, COUNT for counting the data to be traced is stored in the address 0 of the RAM (6e), and N pieces of data DATA (N) for tracing are stored in the addresses 100 to 99 + N. , 200 to 199 + N stores N pieces of trace data TRACE (N), and the data after the address 100 and the data after the address 200 correspond to each other.

First, in step (11) shown in FIG. 7, it is determined by a detection circuit (not shown) whether or not an abnormality that hinders elevator control has occurred. If so, it ends without doing anything. If not, execute step (12). The step (12) is composed of steps (112) to (116), and traces N pieces of data.

First, in step (112), the C stored at address 0
Clear OUNT to 0. Then in step (113) COUNT
Shift DATA (COUNT) at the address indicated by to the left. Then, the D7 bit data is stored in the carry flag CY.

Next, in step (114), trace data TRACE
Shift (COUNT) to the left. Then carry flag C
The Y data is stored in the D0 bit of TRACE (COUNT).

Then, in step (115), +1 is added to COUNT to update the data pointer. In the next step (116), it is determined whether or not COUNT has reached N,
If equal, end.

If not, steps (113) to (116)
repeat. Thus from RAM 100 (6e) from address 99
Addresses 200 to 1 as trace data for the past 8 cycles when the N number of data stored at address + N is "0" or "1"
Stored at address 99 + N.

If an abnormality occurs, in order to perform failure analysis
Although it is necessary to output the trace data stored in the RAM (6e) to the printer (8), the processing will be described based on the flowchart shown in FIG.

In this case, a method for printing out data to the printer (8) already connected at the same time when an abnormality occurs will be described. At step (41), COUNT is first cleared to "0". Then, in step (42), the trace data TRACE (COUNT) at the address indicated by COUNT is output to the printer (8) via the output port (6b).

Next, in step (43), +1 is added to COUNT, and in step (44), it is determined whether or not COUNT has reached N, and if it is equal, the processing ends, otherwise step (42)-
Repeat (44).

[Problems to be Solved by the Invention] Since the conventional elevator failure analysis device is configured as described above, when an abnormality that hinders the operation control of the elevator occurs, when a failure necessary for failure analysis occurs. Control information can be obtained as trace data. However, there are various levels of abnormal states, and if a major fault occurs after another minor fault occurs due to another factor, the control information from the previous minor fault remains as trace data. There is a problem that time control information cannot be obtained.

Therefore, when failure analysis becomes impossible,
There was a problem that the personnel shut down the power when a failure occurred, and the trace data at the time of the failure disappeared.

The present invention has been made to solve the above problems, and an elevator failure analysis device capable of accumulating control information at the time of occurrence of each abnormality even when an abnormality occurs in elevator control a plurality of times. The purpose is to provide.

[Means for Solving the Problems] An elevator failure analysis apparatus according to the present invention is provided with one storage device that stores an elevator operation control signal for a predetermined cycle, and at least one storage device other than the one storage device. , Another storage device that receives and sequentially stores the data stored in each storage device in the preceding stage, and an abnormality detection unit that detects an abnormal state that interferes with the operation control of the elevator,
Transfer means for sequentially transferring the data stored in the other storage device to the other storage device in the subsequent stage after the one storage device stores data indicating the abnormal state during the operation of the abnormality detecting means, When the abnormality detecting means detects a serious failure of the elevator, after storing data corresponding to the serious failure of the elevator in the one storage device, a means for preventing accumulation of data in all the storage devices is provided. It will be.

[Operation] The storage means according to the present invention stores and accumulates the trace data while sequentially transferring the trace data in the order of occurrence of abnormality, and stops the accumulation of data when a serious failure is detected. Therefore, the data of the control signal at the time of occurrence of an abnormality can be extracted later and used for failure analysis.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic block diagram of an embodiment of the present invention. In FIG. 1, an elevator failure analysis apparatus according to this embodiment is provided with an input port (6a), an output port (6b), a CPU in the conventional apparatus. (6c), ROM (6d) and RAM (6e)
The CPU (6c) and the RAM (6e) are different from those of the conventional device, and an uninterruptible power supply (9) for backing up the power supply is added to the RAM (6e).

The CPU (6c) performs a verification operation based on the input data from the input port (6a), outputs the operation result from the output port (6d), and controls the entire microcomputer (6) (operation processing unit ( 6c1) and the arithmetic processing unit (6c1)
An abnormality detection unit (6c2) for detecting an abnormal state that interferes with the elevator operation control based on the elevator data input from the input port (6a) via the abnormality detection unit (6
It is configured to include a transfer control unit (6c3) that transfers the storage contents of a plurality of storage areas (6e1), (6e2), and (6e3), which will be described later, in the RAM (6e) during the operation of c2).

Further, the RAM (6e) is a first storage area (6e1) for storing a motion control signal of the elevator for a predetermined cycle.
And a second storage area (6e2) for storing the operation control signal stored in the first storage area (6e1) based on the transfer operation of the transfer control section (6c3), and the second storage area (6
The operation control signal stored in e2) is transferred to the transfer control unit (6c).
The third storage area (6e) which is stored based on the transfer operation of (3)
3) is provided, the power is backed up by the uninterruptible power supply (9) when the main power is shut off, and the data can be taken out without being stored and retained.

FIG. 2 is a flow chart showing the steps pre-programmed in the RAM (6e) shown in FIG.
The data structure of e) is as shown in FIG. The second below
The operation of the apparatus of this embodiment will be described with reference to FIGS.

First, when the power is turned on, in step (20),
Initialization is performed, and all the data in RAM (6e) except for initial data settings and trace data in each step below are reset to "0". Then step (21)
In the above, general elevator processing such as speed control of the hoisting motor and call registration response, and processing for setting the abnormality detection flag FLAG2 when a preset abnormal state occurs are performed.

In step (22), it is determined whether or not the data transfer flag FLAG1 is present. If yes, the process proceeds to step (28),
If no, go to step (34).

That is, in step (34), the trace stop flag
It is determined whether or not FLAG3 is set. When it is set, the procedure returns to the first step (21), and when it is not set, the procedure proceeds to the next step (24).

Here, the flag FLAG3 can be set in addition to the RAM (6e). When an abnormality is detected in step (24), it is determined in step (36) whether the abnormality can be activated. In other words, when restarting, if there is an abnormality that would impair passenger safety or damage the equipment, proceed to step (38) and trace stop flag.
If FLAG3 is set, otherwise, that is, if it is a minor failure that does not lead to passenger safety or equipment damage, the data transfer flag FLAG1 is set in step (26).

On the other hand, if no abnormality is detected in step (24), the process directly proceeds to step (12). The operation of step (12) is similar to that of step (12) shown in FIG. 7, and the states of addresses 100 to 99 + N are stored in the D0 bit of the trace data of addresses 200 to 199 + N as shown in FIG. . As a result, the trace data TRACE1 (0) to TRACE1 (N-1) as one storage device stores the data state of 7 cycles before and the data state of this cycle.

On the other hand, if FLAG1 is set in the above step (26), the process proceeds to step (28) and the data transfer flag FLAG1
Is reset, and in the next step (30), the abnormality detection flag FLAG2 is reset. Further steps (3
In 2), addresses 300 to 299 stored until then
+ N trace 2 (another storage device), that is, the trace data TRACE2 (0) to TRACE2 (N-1) have an address 400
Trace data TRACE3 (0) to TRACE3 (N-)
It is stored as 1).

Until then, trace 1 in step (12)
Trace 1 of the addresses 200 to 199 + N stored in the area of, that is, trace data TRACE1 (0) to TRACE1 (N
-1) is transferred to the area of trace 2 at addresses 300 to 299 + N, respectively, and trace data TRACE2 (0) to TRACE2
It is stored as (N-1).

Then proceed to the next step (12), address 200 to 1
The trace of 99 + N trace data is restarted, the process returns to the first step (21) again, and the following series of processes are repeated and executed.

As described above, only when an abnormality is detected, in step (32), the trace data at that time is stored in the area of the trace 2 in the storage area, and the trace data in the area of the trace 2 stored until then is stored in the old data. It is transferred and stored with the area of the trace 3 of the area.

That is, the trace data of the latest abnormality is stored in the area of trace 2, and the trace data of the previous abnormality is stored in the area of trace 3 so that the trace data of the abnormality can be easily obtained. Failure analysis can be performed. After this, the process proceeds to step (12), and then data tracing is restarted.

If the abnormality is a serious mode in which activation is not possible, FLAG3 is set in step (38) as described above, and the data at the time of abnormality is TRACE1 (0) to TRACE1 in step (12).
After the data trace processing is performed to (N-1), the process returns to the first step (21), the process proceeds to step (34) because FLAG1 is not set, and since FLAG3 is set, the first step ( By returning to 21) and repeating, the data trace operation will be stopped. Therefore, it is possible to prevent the trace data at the time of serious abnormality from being lost by the storage operation of the trace data at the time of an abnormality that occurs thereafter, and it is possible to increase the reliability of failure analysis.

These data are output to the printer (8) connected to the output board (66) by an input signal from the keyboard (7) as needed. As a measure for a staff member when a failure occurs, firstly, the power is often shut off.

In this invention, since the uninterruptible power supply (9) is provided in the RAM (6e) for backup, the data stored in the areas of trace 1 to trace 3 will not be lost, and the printer (8) will be restored when the power is restored. Can be output via.

Further, in this embodiment, the storage area of the trace data has three stages from trace 1 to trace 3, but it is possible to further expand the storage area if necessary as far as the capacity and cost of the storage device allow.

[Effects of the Invention] As described above, according to the present invention, when an abnormality that interferes with elevator control occurs, the trace data of the control information at that time is sequentially stored in the storage area of the determined storage device. As a result, the latest control information at the time of occurrence of the most serious abnormal state can be obtained as necessary, and it is possible to utilize for highly accurate failure analysis of the elevator control device.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an elevator failure analysis apparatus according to an embodiment of the present invention, FIG. 2 is a flow chart for explaining the operation of the embodiment of the present invention, and FIG. FIG. 4 is a data configuration diagram of a RAM (6e) in the embodiment, FIG. 4 is a configuration diagram showing an overall configuration of an elevator controller
FIG. 5 is a block diagram showing a schematic configuration of the microcomputer (6) shown in FIG. 4, FIG. 6 is a configuration diagram of trace data, and FIGS. 7 and 8 are flow charts showing tracing in a conventional device. FIG. 9 is a data configuration diagram of the RAM (6e) of the conventional device in FIG. (6) is a microcomputer, (6d) is a ROM, (6e)
Is RAM and (9) is an uninterruptible power supply In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A storage device for storing an elevator operation control signal for a predetermined number of cycles, and at least one storage device provided in addition to the one storage device. Other storage device to store,
Abnormality detecting means for detecting an abnormal state that interferes with elevator operation control, and the one storage device stores data indicating the abnormal state during operation of the abnormality detecting means, and then stored in the other storage device. The transfer means for sequentially transferring the stored data to another storage device in the subsequent stage and the abnormality detection means detects a serious failure of the elevator, and then stores the data corresponding to the serious failure of the elevator in the one storage device. , A failure analysis device for an elevator, comprising means for stopping the accumulation of data in all the storage devices. 2. The failure analysis device for an elevator according to claim 1, wherein the data stored in the storage device is backed up and held by the uninterruptible power supply when the main power supply is cut off.