JP2555334B2 - Wheel speed signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wheel speed signal processing device, and more specifically, it takes in the rotational speeds of a plurality of wheels to control a braking force and a driving force. The present invention relates to a wheel speed signal processing device applied to a system that performs the above, or a navigation system that takes in the rotational speeds of a plurality of wheels and calculates the traveling distance, the traveling direction, and the like.

<Prior Art> Conventionally, in order to control the braking force and the driving force based on the relative value of each wheel speed by fetching the wheel speed signals from a plurality of wheels, or for all wheel speeds. The number of vehicles incorporating a microcomputer for calculating a traveling distance, a traveling direction and the like based on the current position and displaying the traveling direction is increasing.

As is well known, the wheel speed signals taken from the plurality of wheels are sinusoidal, and the frequency thereof is proportional to the vehicle speed. The microcomputer obtains vehicle speed information by reading this frequency.

The wheel speed signal detected for each wheel does not normally have a signal level that can be handled by the microcomputer, and the waveform is not a pulse-shaped waveform. Therefore, since it cannot be supplied to the microcomputer as it is, it is necessary to connect an interface circuit between the wheel speed sensor and the microcomputer.

FIG. 3 is a block diagram showing an electrical configuration of a wheel speed interface circuit that has been conventionally used. Wheel speed output from a wheel speed sensor (not shown) on the front right (hereinafter abbreviated as FR) is shown. Traffic light, front left (hereinafter abbreviated as FL)
, A wheel speed signal output from a wheel speed sensor (not shown), a rear right (hereinafter abbreviated as RR) wheel speed signal (not shown), a rear left (hereinafter RL) A wheel speed signal output from a wheel speed sensor (not shown) (referred to as "abbreviated as") is supplied to the protection elements (21) (22) (23) (2), respectively.
It is supplied to the binarization circuit (25) through 4). Then, the four kinds of binarized signals output from the binarization circuit (25) are composed of four D flip-flops (27) (28) (29) (30) which constitute the input stage of the custom IC (26). And the Q output signals from the D flip-flops (27), (28), (29) and (30) are supplied to the microcomputer (31).

The binarization circuit (25) is an IC incorporating four comparators corresponding to each system, and the timing terminals of the D flip-flops (27) (28) (29) (30). The same timing signal is supplied through the inverter gate (32), and the same clear signal is supplied through the inverter gate (33) to the clear terminal.

Therefore, reduction of the number of parts and reduction of the number of gates of the custom IC are effectively achieved.

FIG. 4 is a block diagram showing another structure of a wheel speed interface circuit which has been conventionally used.
The only difference from the configuration of the figure is that the test signal output from the microcomputer (31) is supplied to the binarization circuit (25) through the injection circuit (34).

Therefore, by supplying a test signal from the microcomputer (31), the state of the wheel speed interface can be checked.

<Problems to be Solved by the Invention> In the wheel speed interface having the configuration shown in FIG. 3, since the binarization circuit (25) is configured by one IC,
When a failure occurs in this IC, all the wheel speed signals are not supplied to the microcomputer (31), and the D flip-flops (27) (28) are also provided.
(29) Even if a failure occurs in the timing signal system or the clear signal system supplied to (30), all the wheel speed signals are not supplied to the microcomputer (31). When such a state occurs, it is impossible to detect that the microcomputer (31) has any one of the types of failures described above, and there is no wheel speed signal input. That is, there is a problem that the vehicle is erroneously recognized as being in a stopped state and control based on this erroneous recognition state is continued.

In the wheel speed interface circuit having the configuration shown in FIG. 4, the test signal from the microcomputer (31) is supplied to the wheel speed interface circuit through the injection circuit (34), and the output from the wheel speed interface circuit (34) is output. Although it is possible to recognize whether or not a failure has occurred by comparing the signal with the original test signal, an extra injection circuit (34) is required and is incorporated in the microcomputer (31). With regard to the program as well, it is necessary to add operations such as outputting a test signal under certain conditions, such as during start-up operation, and comparing the signal output from the wheel speed interface circuit with the test signal, increasing the number of parts. Along with this, the physical configuration becomes complicated, and the software installed in the microcomputer (31) is also complicated. There is a problem that to become.

The present invention has been made in view of the above problems, and detects a failure of a system for incorporating a wheel speed signal into a microcomputer while avoiding complication of a physical configuration and complication of software. An object of the present invention is to provide a processing device for a wheel speed signal that can be used.

<Means for Solving Problems> A wheel speed signal processing device of the present invention for achieving the above object corresponds to a wheel speed signal from each wheel of a four-wheeled vehicle, to the front right and rear left. Binarization circuit element which takes in signals independently by dividing into two systems of the wheel system of front wheel and the system of front left wheel and rear right wheel, and both binarization circuit elements (5, 6)
The signal is output from the device or both binary circuit elements (5,
If the signal is not output from 6), the system is considered to be normal, the signals of both systems are taken as signals corresponding to the running state of the vehicle, the wheel speed signal is processed, and either one of the binarization circuits is processed. If the signal is output only from the element (5,6), the system without the output is regarded as a failure, and the signal of the binary circuit element (5,6) system that outputs the signal is output to the vehicle. And a signal processing means (7) for processing a wheel speed signal by taking in as a signal corresponding to the running state of the vehicle (claim 1).

Further, the wheel speed signal processing device of the present invention is in a state where signals are output from both binary circuit elements (5, 6) or a signal is not output from both binary circuit elements (5, 6). If so, the system is regarded as normal and the signals of both systems are acquired as signals corresponding to the running state of the vehicle to process the wheel speed signal.
If a signal is output from only one of the binarization circuit elements (5, 6), the system without the output is regarded as a failure and the processing based on the signals of all systems is interrupted. (Claim 2).

<Operation> With the wheel speed signal processing device according to the first aspect of the present invention, the front right and rear left wheel systems and the wheel systems corresponding to the wheel speed signals from the respective wheels of the four-wheel vehicle are provided. Since the signals are independently acquired by dividing them into the two systems of the front left and rear right wheels, even if there is no signal to be acquired from one of the systems, there is no malfunction and normal operation. The wheel speed signal can be processed based on the signal from the system.

In this case, in the four-wheel vehicle, the two systems of the front right and rear left wheels and the front left and rear right wheels are divided into the front two wheels and the rear two wheels when longitudinal acceleration is applied. Since there is a comparatively large deviation in the rotational speed of the vehicle and the rotational speed between the two left wheels and the two right wheels when traveling on a curve, erroneous detection of a failure due to an imbalance in the take-in signal of each wheel in such a case is prevented. This is because

With the wheel speed signal processing device according to claim 2, when there is no acquisition signal from any one of the systems, the system without the output is regarded as a failure and only the system without the output is provided. However, the processing based on the signals of all systems is interrupted. As a result, it is possible to perform reliable control on the safer side.

<Example> Hereinafter, an example will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a wheel speed interface circuit relating to a wheel speed signal processing device of the present invention. The FR wheel speed signal and the RL wheel speed signal are respectively protective elements (1) (2). ), And a binary circuit (6) supplied with FL wheel speed signals and FL wheel speed signals and RR wheel speed signals through protective elements (3) and (4), respectively. 2 output from the digitizing circuits (5) and (6)
It is composed of a microcomputer (7) to which a binary signal for each type is supplied.

More specifically, each of the binarization circuits is composed of an IC that incorporates two comparators, and in a state where a failure such as a wiring error in the power supply or an abnormality in the power supply circuit occurs, A configuration is adopted in which no signal is output from the corresponding binarization circuit.

In the wheel speed interface circuit having the above configuration,
In the state where no failure occurs, the binarizing circuit (5) outputs the FR wheel speed signal and the binary signal obtained by binarizing the RL wheel speed signal, and the binarizing circuit (6).
2 which binarized FL wheel speed signal and RR wheel speed signal from
Since the value signal is output, these binary signals do not become significantly different signals.

Therefore, in the microcomputer (7),
It can be recognized that the wheel speed interface is normal, and necessary processing can be performed based on the four types of binary signals.

When a failure occurs in the binarizing circuit (5), no binary signal corresponding to the FR wheel speed signal and the RL wheel speed signal is output and the FL wheel speed signal and RR wheel speed signal are not output. A binary signal corresponding to the wheel speed signal is output as a value corresponding to the running state of the vehicle. That is, the signal output from the binarization circuit (5) and the signal output from the binarization circuit (6) are significantly different.

Therefore, in the microcomputer (7),
It is possible to recognize that the binarization circuit (5) side of the wheel speed interface is abnormal, and it is necessary based on two kinds of binary signals from the normal binarization circuit (6) side. Processing can be performed. However, it is also possible to interrupt the processing based on all binary signals.

On the contrary, when a failure occurs on the binarization circuit (6) side, in the microcomputer (7), the binarization circuit (6) side of the wheel speed interface is abnormal in the same manner as described above. It can be recognized that the necessary processing can be performed based on the two kinds of binary signals from the normal binary circuit (5). However, it is also possible to interrupt the processing based on all binary signals.

In summary, it is possible to detect a state in which no failure has occurred, and a state in which any one of the binarization circuits has a failure, based on the capture signal in the microcomputer (7). Can be dealt with.

However, although it is not possible to detect that both binarization circuits have failed at the same time, it is almost the case that one of them fails before this state occurs. It is possible to detect the occurrence of a failure in, and there is no inconvenience.

FIG. 2 is a block diagram showing another embodiment of the wheel speed interface circuit relating to the wheel speed signal processing device of the present invention. The FR wheel speed signal and the RL wheel speed signal are respectively protective elements (1) (2). ), And a binary circuit (6) supplied with FL wheel speed signals and FL wheel speed signals and RR wheel speed signals through protective elements (3) and (4), respectively. 2 output from the digitizing circuits (5) and (6)
A custom IC (8) that is supplied with binary signals for each type,
It is composed of a microcomputer (7) to which an output signal from the custom IC (8) is supplied.

More specifically, each of the binarization circuits is composed of an IC that incorporates two comparators, and in a state where a failure such as a wiring error in the power supply or an abnormality in the power supply circuit occurs, A configuration is adopted in which no signal is output from the corresponding binarization circuit. Further, the custom IC (8) has D flip-flops (9) (10) (wherein four kinds of binary signals output from the binarization circuits (5) and (6) are supplied to D input terminals, respectively. 11) (1
2), a timing signal line in which an inverter gate (13) is inserted in a predetermined position, a clear signal line in which an inverter gate (14) is inserted in a predetermined position, and the D flip-flop (from the timing signal line 9) (1
0) a timing signal is supplied to the timing terminal of the D flip-flops (11) (12) from the timing signal line through the inverter gate (13). The inverter gate (16) to be supplied and the D flip-flop (9) from the clear signal line
An inverter gate (17) for supplying a clear signal to the clear terminal of (10), and the inverter gate (14)
An inverter gate (18) for supplying a clear signal to a clear terminal of the D flip-flops (11) (12) from a clear signal line through the timing signal and the clear signal through both the inverter gates (13) (14). Is supplied to the monitoring circuit (19). The monitoring circuit (19) is a circuit for issuing a warning that both the timing signal and the clear signal have become unacceptable.

In the wheel speed interface circuit having the above configuration,
In the state where no failure occurs, the binarizing circuit (5) outputs the FR wheel speed signal and the binary signal obtained by binarizing the RL wheel speed signal, and the binarizing circuit (6).
2 which binarized FL wheel speed signal and RR wheel speed signal from
Since the value signal is output, these binary signals do not become significantly different signals. Further, the timing signal and the clear signal are normally supplied to the monitoring circuit (19).

Therefore, the microcomputer (7) and the monitoring circuit (19) can recognize that the wheel speed interface is normal, and can perform necessary processing based on the four types of binary signals.

When a failure occurs in the binarizing circuit (5), no binary signal corresponding to the FR wheel speed signal and the RL wheel speed signal is output and the FL wheel speed signal and RR wheel speed signal are not output. A binary signal corresponding to the wheel speed signal is output as a value corresponding to the running state of the vehicle. That is, the signal output from the binarization circuit (5) and the signal output from the binarization circuit (6) are significantly different.

Therefore, in the microcomputer (7),
It is possible to recognize that the binarization circuit (5) side of the wheel speed interface is abnormal, and it is necessary based on two kinds of binary signals from the normal binarization circuit (6) side. Processing can be performed. However, it is also possible to interrupt the processing based on all binary signals.

On the contrary, when a failure occurs on the binarization circuit (6) side, in the microcomputer (7), the binarization circuit (6) side of the wheel speed interface is abnormal in the same manner as described above. It can be recognized that the necessary processing can be performed based on the two kinds of binary signals from the normal binary circuit (5). However, it is also possible to interrupt the processing based on all binary signals.

Further, in the custom IC (8), the line upstream of the inverter gate (13) among the timing signal lines is broken (wiring on the IC is broken, timing signal generating circuit (not shown) is stopped, etc.) The same applies hereinafter.), The timing signal is not supplied to the monitoring circuit (19), so it is determined that the monitoring circuit (19) is in a failure state, and the determination signal is sent to the microcomputer (7). ) To stop the wheel speed signal acquisition operation. That is, in this state, since all the D flip-flops (9), (10), (11) and (12) do not operate, the wheel speed signal acquisition operation is stopped as described above.

In the custom IC (8), a timing signal is supplied to the monitoring circuit (19) when a failure occurs in the timing signal line in which the inverter gate (15) is inserted. However, since the signal is supplied to the microcomputer (7) only through the D flip-flops (11) (12), the microcomputer is processed in the same manner as when the failure occurs on the binarization circuit (5) side. The computer (7) can detect the state in which a failure has occurred.

On the contrary, in the custom IC (8), when a failure occurs in the timing signal line in which the inverter gate (16) is inserted, the timing signal is supplied to the monitoring circuit (19). However, since the signal is supplied to the microcomputer (7) only through the D flip-flops (9) and (10), the same procedure as in the case where a failure occurs on the binarization circuit (6) side is performed. The microcomputer (7) can detect a state in which a failure has occurred.

That is, in the case of this embodiment, in the timing signal line through which the inverter gate (13) is inserted, a failure occurs in the line upstream of the inverter gate (13), so that the signals from both systems are simultaneously captured. The monitoring circuit (19) can detect this state and take necessary measures, although it is not performed and the microcomputer (7) cannot detect it.

<Effect of the Invention> As described above, according to the present invention as set forth in claim 1, the system for supplying the wheel speed signal from each wheel to the control device is a system for the front right and rear left wheels and the front. It is possible to reliably detect the occurrence of a failure in any one of the two systems, that is, the left and the rear right wheel systems by dividing the system into two systems. Therefore, a normal signal can be taken in and reliable signal processing can be performed, and simplification of the configuration of the entire apparatus and simplification of a processing program can be achieved. In addition, since the system is divided into two systems, that is, a system of front right and rear left wheels and a system of front left and rear right wheels, it is possible to prevent erroneous detection of a failure based on an imbalance generated in a take-in signal of each wheel. It is effective.

Further, according to the present invention as set forth in claim 2, when there is no acquisition signal from any one of the systems, the system without the output is regarded as a failure, and not only the system but the entire system. The signal-based processing is interrupted. As a result, it is possible to perform reliable control on the safer side.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a wheel speed interface circuit relating to a wheel speed signal processing device of the present invention. FIG. 2 is a block diagram showing another embodiment of the wheel speed interface circuit relating to the wheel speed signal processing device of the present invention. FIG. 3 and FIG. 4 are block diagrams showing the structure of a wheel speed interface circuit which has been conventionally used. (5) (6) …… Binarization circuit, (7) …… Microcomputer, (8) …… Custom IC, (9) (10) (11) (12) ……
D flip-flop, (13) (15) (16) …… Inverter gate, (19) ……
Monitoring circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A 52-8442 (JP, A) JP-A 50-102775 (JP, A) JP-A 48-85976 (JP, A) Actual development Sho-57- 171952 (JP, U) Actual opening 53-132379 (JP, U) Actual opening 57-185003 (JP, U)

Claims (2)

(57) [Claims] 1. Corresponding to a wheel speed signal from each wheel of a four-wheeled vehicle, it is divided into two systems, a system of front right and rear left wheels and a system of front left and rear right wheels, which are independent of each other. Binarization circuit element (5,6) that takes in a signal and a state where signals are output from both binarization circuit elements (5,6) or no signal is output from both binarization circuit elements (5,6) If it is in the state, the system is regarded as normal and the signals of both systems are taken in as signals corresponding to the running state of the vehicle and the wheel speed signal is processed, and either one of the binary circuit elements (5, 6) is processed. If only the signal is output, the system without the output is considered as a failure, and the signal of the binary circuit element (5, 6) system that outputs the signal is the signal corresponding to the running state of the vehicle. And a signal processing means (7) for processing the wheel speed signal. Processing equipment. 2. A system for front right and rear left wheels and a system for front left and rear right wheels are independently divided into two systems corresponding to wheel speed signals from each vehicle of a four-wheeled vehicle. Binarization circuit element (5,6) that takes in a signal and a state where signals are output from both binarization circuit elements (5,6) or no signal is output from both binarization circuit elements (5,6) If it is in the state, the system is regarded as normal and the signals of both systems are taken in as signals corresponding to the running state of the vehicle and the wheel speed signal is processed, and either one of the binary circuit elements (5, 6) is processed. If only the signal is output, the system having no output is regarded as a failure, and signal processing means (7) for interrupting the processing based on the signals of all systems is included. Processing equipment.