JP2549564B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2549564B2 JP2549564B2 JP1271727A JP27172789A JP2549564B2 JP 2549564 B2 JP2549564 B2 JP 2549564B2 JP 1271727 A JP1271727 A JP 1271727A JP 27172789 A JP27172789 A JP 27172789A JP 2549564 B2 JP2549564 B2 JP 2549564B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- insulating plate
- semiconductor wafer
- substrate
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子およびその製造方法に係わり、特
に電極の取り出し構造およびその形成方法に関するもの
である。The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a structure for taking out electrodes and a method for forming the same.
第２図は従来の半導体素子として容量式の圧力センサ
の一例を示す断面図である。同図において、１はシリコ
ン基板、２はシリコン基板１の背面に断面が台形状にエ
ツチング加工されて形成された開口、３はこの開口２の
形成によつてシリコン基板１の表面部分にシリコン薄肉
部により形成された可動部としての起歪部であり、これ
らのシリコン基板1,開口２および起歪部３によりセンサ
チツプ４を構成している。また、５はシリコン基板１の
起歪部３表面に成膜された金属薄膜からなる下部電極、
5aはシリコン基板１の表面端部に設けられた下部電極５
の電極取り出し用パツド、６はシリコン基板１の表面側
に凹部を対向させ起歪部３を被覆して接着配置された上
部キヤツプ、７は上部キヤツプ６の凹部内面に下部電極
５と対向して成膜された上部電極、８は対向配置された
上部電極７と下部電極５との間に一定寸法の空隙幅を有
して形成された容量形成部、９は上部キヤツプ６の端部
に穿設されたコンタクトホール、10はコンタクトホール
９内に充填されかつ下部電極パツド5aと電気的に接続さ
れる導電体、11は導電体10に電気的に接続される外部回
路接続用導電性リードである。FIG. 2 is a sectional view showing an example of a conventional capacitive pressure sensor as a semiconductor element. In the figure, 1 is a silicon substrate, 2 is an opening formed in the back surface of the silicon substrate 1 by etching with a trapezoidal cross section, and 3 is a thin silicon film formed on the surface of the silicon substrate 1 by forming the opening 2. The sensor chip 4 is composed of the silicon substrate 1, the opening 2, and the strain-generating portion 3 as a movable portion formed by the portions. Further, 5 is a lower electrode made of a metal thin film formed on the surface of the strain generating portion 3 of the silicon substrate 1,
5a is a lower electrode 5 provided at the end of the surface of the silicon substrate 1.
Pad for taking out the electrode, 6 is an upper cap which is arranged so as to face the surface side of the silicon substrate 1 so as to face the concave portion and covers the strain-flexing portion 3, and 7 is bonded to the inner surface of the concave portion of the upper cap 6. The formed upper electrode, 8 is a capacitance forming portion formed with an air gap width of a certain size between the upper electrode 7 and the lower electrode 5 which are arranged facing each other, and 9 is formed at the end of the upper cap 6. A contact hole is provided, 10 is a conductor filled in the contact hole 9 and is electrically connected to the lower electrode pad 5a, and 11 is a conductive lead for external circuit connection electrically connected to the conductor 10. is there.
しかしながら、このように構成された圧力センサは、
予め一方の絶縁性基板（例えばパイレツクス）上に多数
個の上部電極７を形成し、さらに多数個のコンタクトホ
ール９をエツチングもしくは放電加工により穿設した
後、他方のシリコンウエハ上に多数組の起歪部３および
下部電極５を形成して両者を対向させて接合し、采の目
状にダイシングを行なつて個々に分割して操作してい
た。このため、上部キヤツプ６にコンタクトホール９を
エツチングにより形成する場合、下部電極パツド5aの表
面積に比べて広いエツチングスペースが必要となり、形
状の小型化が困難であるうえにエツチングに長時間を要
するなどの問題があつた。また、多数個のコンタクトホ
ール９を穿設したトツププレート基板は、破損しやす
く、取り扱いに細心な注意を要するなど生産性を低下さ
せるという問題があつた。さらにコンタクトホール９を
放電加工により形成する場合、穴加工に長時間を要し、
センサの量産性に問題があるうえに穴形状を大きく形成
しなければ、通常のワイヤボンダによる配線はできない
ため、形状の小型化が困難な上にセンサ組み付け時の量
産性にも問題があつた。However, the pressure sensor configured in this way is
After forming a large number of upper electrodes 7 on one insulating substrate (for example, a pyrex) in advance and further forming a large number of contact holes 9 by etching or electric discharge machining, a large number of sets of sets are formed on the other silicon wafer. The strained portion 3 and the lower electrode 5 were formed, and the two were opposed to each other and joined, and dicing was performed in the shape of a grid to individually operate. Therefore, when the contact hole 9 is formed in the upper cap 6 by etching, a larger etching space is required than the surface area of the lower electrode pad 5a, which makes it difficult to miniaturize the shape and requires a long time for etching. There was a problem. In addition, the top plate substrate having a large number of contact holes 9 easily breaks, and requires careful handling to reduce productivity. Further, when the contact hole 9 is formed by electric discharge machining, it takes a long time to form the hole,
In addition to the problem of mass productivity of the sensor, if the hole shape is not made large, wiring with a normal wire bonder is not possible, which makes it difficult to miniaturize the shape and also has a problem of mass productivity when assembling the sensor.
したがつて本発明は、前述した従来の課題を解決する
ためになされたものであり、その目的は電極取り出し部
の構成を簡易化させて量産性および生産性の高い半導体
素子およびその製造方法を提供することにある。Therefore, the present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to provide a semiconductor element having high mass productivity and high productivity by simplifying the configuration of the electrode lead-out portion and a manufacturing method thereof. To provide.
このような課題を解決するために本発明による半導体
素子の製造方法は、表面に多数組の電極および該電極と
連結される電極パッドが形成された半導体ウエハと、各
電極および電極パッドとを対向する部位に凹部が形成さ
れた絶縁プレートとを半導体ウエハ表面に絶縁プレート
凹部側を対向させて接合した後、絶縁プレートのみを電
極パッドと対応する凹部に沿ってダイシングし、引き続
き半導体ウエハと絶縁プレートとの接合体を同時にダイ
シングすることにより、半導体ウエハと絶縁プレートと
の張り合わせにより電極取り出し部がウエハ内部に位置
することになる半導体素子の電極取り出しを容易にした
ものである。In order to solve such a problem, in a method for manufacturing a semiconductor device according to the present invention, a semiconductor wafer having a large number of electrodes and electrode pads connected to the electrodes formed on a surface is opposed to each electrode and the electrode pad. After bonding an insulating plate having a concave portion formed on its surface to the semiconductor wafer surface with the concave side of the insulating plate facing each other, only the insulating plate is diced along the concave portion corresponding to the electrode pad, and then the semiconductor wafer and the insulating plate. By simultaneously dicing the bonded body of the semiconductor wafer and the insulating plate, the electrode extraction of the semiconductor element whose electrode extraction portion is positioned inside the wafer is facilitated.
本発明においては、半導体基板の表面端部に電極パツ
ドが露出して形成される。In the present invention, the electrode pad is formed so as to be exposed at the end of the surface of the semiconductor substrate.
以下、図面を用いて本発明の実施例を詳細に説明す
る。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図（ａ）〜（ｋ）は本発明による半導体素子の製
造方法の一実施例を容量式圧力センサの製造方法に適用
した場合について説明する工程の断面図であり、前述の
図と同一部分には同一符号を付してある。同図におい
て、まず、同図（ａ）に示すようにシリコンウエハ21の
裏面に例えばSi3N4などのエツチングマスク材22を成膜
し、このエツチングマスク材22に前記台形溝２の開口部
分に相当する窓パターン22aをフオトリソグラフイ技術
によりパターニングして形成した後、この窓パターン22
a内を例えばKOHなどのエツチング液により異方性エツチ
ングを行なうと、同図（ｂ）に示すように前述した断面
が台形状の開口２が形成されるとともにシリコンウエハ
21の表面部分にシリコン薄肉部からなる起歪部３が形成
される。次に第１のシリコンウエハ21の裏面側のエツチ
ングマスク材22を除去した後、同図（ｃ）に示すように
シリコンウエハ21の表面に例えばAlなどの金属を蒸着も
しくはスパツタリング法によつて前記下部電極５および
電極パツド5aをパターン形成してセンサチツプ部23を完
成する。一方、同図（ｄ）に示すように例えば板厚が25
0〜500μｍのパイレツクス基板24を用意し、このパイレ
ツクス基板24の表面および裏面に例えばフオトレジスト
膜25を成膜した後、このパイレツクス基板24の表面に前
記電極パツド5aの形成領域と反対向する部分で後述する
ダイシングする際の目印とする窓パターン25aを形成
し、さらにその裏面の前記容量形成部８の形成領域とす
る部分に窓パターン25bおよび電極パツド5aの形成領域
とする部分に窓パターン25cをそれぞれフオトリソグラ
フイ技術により形成する。次に同図（ｅ）に示すように
これらの窓パターン25a,25b,25c内を例えばHFなどのエ
ツチング溶液により異方性エツチングを行なつて同図
（ｅ）に示すように深さが25〜50μｍの断面が台形状の
台形溝26a,26b,26cをそれぞれ形成した後、フオトレジ
スト膜25を除去する。次に同図（ｆ）に示したように台
形溝26b内に例えばAlなどの金属を蒸着した後、パター
ニング（エツチング）を行なつて前記上部電極７を形成
して前記キヤツプ６に相当するものとなるトツププレー
ト部27を完成する。次に同図（ｇ）に示すように前記セ
ンサチツプ部23の表面にトツププレート部27を位置合せ
して陽極接合法により全面接着させる。次に同図（ｈ）
に示すようにトツププレート部27の台形溝26a,26cのみ
をその溝26a,26cの深さ方向に沿つてダイヤモンドブレ
ード28によりダイシングを行なつた後、引き続き同図
（ｉ）に示すようにトツププレート部27とセンサチツプ
部23とを同時にその厚さ方向に沿つてダイシングを行な
い、個々のチツプに分割させて同図（ｊ）に示すように
シリコン基板１の表面がトツププレート12で覆われた構
造の圧力センサが得られる。しかる後、この圧力センサ
を同図（ｋ）に示すようにHIC基板29上に実装し、電極
パツド5aとHIC基板29上の電極パツド29aとの間を導電性
リード11によりワイヤボンドを行なつて完成する。FIGS. 1 (a) to 1 (k) are sectional views of steps for explaining a case where an embodiment of a method for manufacturing a semiconductor device according to the present invention is applied to a method for manufacturing a capacitive pressure sensor, and are the same as the above-mentioned drawings. The same reference numerals are given to the parts. In the figure, first, as shown in FIG. 3A, an etching mask material 22 such as Si 3 N 4 is formed on the back surface of the silicon wafer 21, and the etching mask material 22 has an opening portion of the trapezoidal groove 2. After the window pattern 22a corresponding to is patterned and formed by the photolithography technique, the window pattern 22a is formed.
When anisotropic etching is performed on the inside of a with an etching liquid such as KOH, an opening 2 having a trapezoidal cross section as described above is formed as shown in FIG.
On the surface portion of 21, the strain generating portion 3 composed of a thin silicon portion is formed. Next, after removing the etching mask material 22 on the back surface side of the first silicon wafer 21, metal such as Al is vapor-deposited or sputtered on the surface of the silicon wafer 21 as shown in FIG. The lower electrode 5 and the electrode pad 5a are patterned to complete the sensor chip portion 23. On the other hand, as shown in FIG.
A 0-500 μm pyrex substrate 24 is prepared, and, for example, a photoresist film 25 is formed on the front surface and the back surface of the pyrex substrate 24, and then a portion of the pyrex substrate 24 opposite to the area where the electrode pad 5a is formed. A window pattern 25a is formed as a mark for dicing, which will be described later, and a window pattern 25c is formed on a portion of the back surface thereof where the capacitance forming portion 8 is formed and a portion where the electrode pad 5a is formed. Are formed by the photolithographic technique. Next, as shown in (e) of the figure, anisotropic etching is performed in the window patterns 25a, 25b, 25c with an etching solution such as HF to obtain a depth of 25 degrees as shown in (e) of the figure. After forming trapezoidal grooves 26a, 26b, and 26c each having a trapezoidal cross section of .about.50 .mu.m, the photoresist film 25 is removed. Next, as shown in FIG. 6F, after depositing a metal such as Al in the trapezoidal groove 26b, patterning (etching) is performed to form the upper electrode 7, which corresponds to the cap 6. The top plate portion 27 to be Next, as shown in FIG. 3G, the top plate portion 27 is aligned with the surface of the sensor chip portion 23 and adhered over the entire surface by the anodic bonding method. Next, the same figure (h)
As shown in FIG. 7, after only the trapezoidal grooves 26a, 26c of the top plate portion 27 are diced by the diamond blade 28 along the depth direction of the grooves 26a, 26c, as shown in FIG. The plate portion 27 and the sensor chip portion 23 are simultaneously diced along the thickness direction thereof to be divided into individual chips, and the surface of the silicon substrate 1 is covered with the top plate 12 as shown in FIG. A structure pressure sensor is obtained. Thereafter, this pressure sensor is mounted on the HIC substrate 29 as shown in FIG. 3K, and wire bonding is performed by the conductive lead 11 between the electrode pad 5a and the electrode pad 29a on the HIC substrate 29. Complete.
このような方法によると、シリコンウエハ21が例えば
直径４インチであれば、3mm角程度のチツプサイズでも
シリコンウエハ21の全面をダイシングに要する時間は数
分程度であり、第２図のエツチングや放電加工による方
法が１時間以上要するのに対して大幅に生産性が向上で
きる。また、トツププレート部27となるパイレツクス基
板24の板厚を250〜500μｍとし、その台形溝26a,26cの
深さを25〜50μｍとすると、トツププレート部27とセン
サチツプ部23とを接合し、ダイシングによつて形成され
る電極取り出し部の構造が従来の1/5〜1/10の時間で形
成でき、量産性を大幅に向上させることができた。According to such a method, if the silicon wafer 21 has a diameter of 4 inches, for example, even if the chip size is about 3 mm square, the time required for dicing the entire surface of the silicon wafer 21 is about several minutes, and the etching or electric discharge machining shown in FIG. The method according to (1) requires more than one hour, but the productivity can be significantly improved. If the thickness of the pyrex substrate 24 to be the top plate portion 27 is 250 to 500 μm and the depth of the trapezoidal grooves 26a and 26c is 25 to 50 μm, the top plate portion 27 and the sensor chip portion 23 are joined to each other and the dicing is performed. The structure of the electrode lead-out portion formed by the method can be formed in 1/5 to 1/10 of the time required by the conventional method, and mass productivity can be greatly improved.
また、このような方法により構成された圧力センサ
は、シリコン基板１の表面端部に広い領域にわたつて電
極パツド5aが露出する電極取り出し部が簡単な構成で得
られるとともに通常のワイヤボンダによるボンデイング
ワイヤ11のボンデイングが容易となる。Further, the pressure sensor constructed by such a method can obtain an electrode lead-out portion where the electrode pad 5a is exposed over a wide area at the surface end portion of the silicon substrate 1 with a simple structure and a bonding wire using a normal wire bonder. Bonding of 11 becomes easy.
なお、前述した実施例においては、トツププレート12
をパイレツクス基板で形成した場合について説明した
が、本発明はこれに限定されるものではなく、シリコン
基板で形成しても良く、この場合、接合はフエージヨン
ボンド法が用いられ、また、フユージヨンボンド法では
上部電極５と電極パツド5aとの接続に埋込み拡散リード
などを用いると良い。In the embodiment described above, the top plate 12
However, the present invention is not limited to this, and may be formed by a silicon substrate. In this case, the bonding is performed by the fusion bond method, and the fusion is also performed. In the Yonbond method, a buried diffusion lead or the like may be used to connect the upper electrode 5 and the electrode pad 5a.
以上説明したように本発明によれば、電極取り出し部
が簡単な構成でしかも容易に形成できるので、半導体素
子が量産性および生産性良く得られるという極めて優れ
た効果を有する。As described above, according to the present invention, since the electrode lead-out portion can be easily formed with a simple structure, it has an extremely excellent effect that a semiconductor element can be obtained with high mass productivity and productivity.
第１図（ａ）〜（ｋ）は本発明の一実施例による圧力セ
ンサの製造方法を説明する工程の断面図、第２図は従来
の圧力センサの構成を示す断面図である。 １……シリコン基板、２……開口、３……起歪部、４…
…センサチツプ、５……下部電極、5a……電極パツド、
６……上部キヤツプ、７……上部電極、８……容量形成
部、11……導電性リード、12……トツププレート、21…
…シリコンウエハ、22……エツチングマスク材、22a…
…窓パターン、23……センサチツプ部、24……パイレツ
クス基板、25……フオトレジスト膜、25a,25b,25c……
窓パターン、26a,26b,26c……台形溝、27……トツププ
レート部、28……ダイヤモンドブレード、29……HIC基
板。1 (a) to 1 (k) are sectional views showing steps of a method for manufacturing a pressure sensor according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a structure of a conventional pressure sensor. 1 ... Silicon substrate, 2 ... Aperture, 3 ... Strain element, 4 ...
... Sensor chip, 5 ... Lower electrode, 5a ... Electrode pad,
6 ... Upper cap, 7 ... Upper electrode, 8 ... Capacitance forming part, 11 ... Conductive lead, 12 ... Top plate, 21 ...
… Silicon wafer, 22… Etching mask material, 22a…
… Window pattern, 23 …… Sensor chip, 24 …… Pyrex substrate, 25 …… Photoresist film, 25a, 25b, 25c ……
Window pattern, 26a, 26b, 26c …… trapezoidal groove, 27 …… Top plate part, 28 …… Diamond blade, 29 …… HIC substrate.
Claims (1)
れる電極パッドが形成された半導体ウエハと、前記各電
極および電極パッドとを対向する部位に凹部が形成され
た絶縁プレートとを前記半導体ウエハ表面に前記絶縁プ
レート凹部側を対向させて接合した後、前記絶縁プレー
トのみを前記電極パッドと対向する凹部に沿ってダイシ
ングし、引き続き半導体ウエハと絶縁プレートとの接合
体を同時にダイシングすることにより、前記半導体ウエ
ハと前記絶縁プレートとの張り合わせにより電極取り出
し部が前記半導体ウエハ内部に位置することになる半導
体素子の電極取り出しを容易にしたことを特徴とした半
導体素子の製造方法。1. A semiconductor wafer having a plurality of sets of electrodes and electrode pads connected to the electrodes formed on a surface thereof, and an insulating plate having a recess formed at a portion facing the electrodes and the electrode pads. Bonding the surface of the semiconductor wafer so that the recesses of the insulating plate face each other, and then dicing only the insulating plate along the recess facing the electrode pad, and subsequently dicing the bonded body of the semiconductor wafer and the insulating plate at the same time. According to the above, the method of manufacturing a semiconductor element is characterized in that the electrode extraction of the semiconductor element whose electrode extraction portion is located inside the semiconductor wafer is facilitated by bonding the semiconductor wafer and the insulating plate together.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1271727A JP2549564B2 (en) | 1989-10-20 | 1989-10-20 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1271727A JP2549564B2 (en) | 1989-10-20 | 1989-10-20 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03134570A JPH03134570A (en) | 1991-06-07 |
| JP2549564B2 true JP2549564B2 (en) | 1996-10-30 |
Family
ID=17504001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1271727A Expired - Lifetime JP2549564B2 (en) | 1989-10-20 | 1989-10-20 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2549564B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5721162A (en) * | 1995-11-03 | 1998-02-24 | Delco Electronics Corporation | All-silicon monolithic motion sensor with integrated conditioning circuit |
| DE102005015584B4 (en) | 2005-04-05 | 2010-09-02 | Litef Gmbh | Method for producing a micromechanical component |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CH642461A5 (en) * | 1981-07-02 | 1984-04-13 | Centre Electron Horloger | ACCELEROMETER. |
-
1989
- 1989-10-20 JP JP1271727A patent/JP2549564B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03134570A (en) | 1991-06-07 |
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