JP2543247B2 - Color subcarrier generator - Google Patents

Description

FIELD OF THE INVENTION The present invention relates to an apparatus for producing a color subcarrier with a 25 Hertz offset of a PAL signal.

2. Description of the Related Art As disclosed in Japanese Patent Laid-Open No. 54-44431, a clock that is phase-synchronized with a horizontal synchronizing signal is first created, and then phase-modulated to generate a color subcarrier with a 25 Hz offset. However, there is no method for directly phase-shifting and modulating the horizontal synchronizing signal.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In order to realize a method of directly phase-shifting and modulating a horizontal synchronizing signal to obtain a color subcarrier, when phase-modulating the horizontal synchronizing signal, a phase shift modulation time of a stable circuit method is used. Development is important, and it is also an important issue to have a circuit system suitable for digital integrated circuits.

Means for Solving the Problem To solve this problem, a color subcarrier generating apparatus according to the present invention includes a sync separation means for separating a video signal horizontal and vertical sync signals, and a horizontal and vertical sync signal from the sync separation means. Phase shift signal generating means for generating a phase shift modulated signal α, phase shift means controlled by the phase shift modulated signal α for shifting the horizontal synchronizing signal from the sync separating means, and the phase shift And frequency multiplication means for multiplying the output of the means to obtain a color subcarrier.

Further, the transfer means comprises delay means constituted by connecting N stages of delay units having a minimum unit delay time in cascade, and the delay required to delay a predetermined time T by inputting a reference signal to the delay means. The delay stage number measuring means for measuring the stage number of the delay unit constituting the means, the selecting means for selecting the output of each stage of the delay unit, and the output value K of the delay stage number measuring means are multiplied by the phase shift modulation signal α. And a multiplication means for controlling the selection means according to the multiplication result αK obtained as described above.

Operation With the above configuration, according to the present invention, the phase modulating means is provided with a circuit for measuring the delay time of the delay line by itself in the delay line to which the delay unit having the minimum unit delay time is cascade-connected, and the delay unit is added moment by moment. Is measured, the desired phase shift modulation signal is multiplied by the reciprocal of the delay time of the delay unit, and the number of stages of the delay unit is selected based on this result.

By using this phase shift modulation means, the amount of phase shift for phase shifting the horizontal sync signal becomes stable, and by phase shifting modulating the horizontal sync signal and inputting it to the multiplying means, the PAL system with a 25 Hertz offset It is possible to directly generate the color sub-carrier of the above, and even when the gate delay inside the digital integrated circuit is used as the delay unit that constitutes the phase shift modulation means, the delay unit is affected by the power supply, environmental temperature fluctuations, etc. Even if the delay time changes, the entire phase shift modulator can always have a stable phase shift time, and is a circuit system suitable for digital integrated circuit.

Embodiment FIG. 1 shows an embodiment of a color subcarrier generator in the PAL system. The video signal applied to the input terminal 100 is separated by the sync separator 18 into horizontal and vertical sync signals. The phase shift modulation signal generator 19 generates the phase shift modulation signal α based on the horizontal and vertical synchronization signals. Phase shifter (phase shifting means) 20
Then, phase-shift keying signal α is used to phase-shift the horizontal sync signal,
It is supplied to L (multiplication means) 25.

The PLL 25 includes a phase comparator 21, a low pass filter 22, a voltage controlled oscillator 23, and a frequency divider 24.
The horizontal synchronizing signals from the phase shifter 20 and the frequency divider 24 are phase-compared at 21 and the output of the phase shifter 20 is frequency-multiplied to obtain a color subcarrier.

Here, for example, the clock frequency of the voltage controlled oscillator 23
Divide by 4 times the color subcarrier frequency (fsc) of PAL signal
At 24, this clock is divided by 1135 to obtain the horizontal synchronizing frequency, and the clock is divided by 4 to obtain the color recovery carrier fsc.

In the phase shifter 20, the amount of phase shift of the output terminal 12 with respect to the input terminal 2 starts from a predetermined amount of phase shift at the timing of each vertical synchronizing signal, and gradually increases until the next vertical synchronizing signal. It is set so as to be shifted by one cycle of the color subcarrier cycle in one vertical scanning period.

By doing this, from the color subcarrier output terminal 26,
The PAL color subcarrier obtained by the equation (1) is obtained.

fsc = (284-1 / 4) * fH + 25 (1) Next, the detailed internal structure of the block used in FIG. 1 will be described below. FIG. 2 shows the configuration of the phase shift modulation signal generator 19, which is composed of a counter 193 as an example, and an input terminal 191.
The counter value is reset at the timing of the vertical synchronizing signal (V), and then the horizontal synchronizing signal (H) of the input terminal 192.
And outputs the phase shift modulation signal α to the output terminal 194.

Next, the detailed configuration of the phase shifter 20 will be described. Third
The figure is a detailed configuration diagram of the phase shifter 20. A pulse generator 1 generates a pulse used to measure the delay time of the delay line, and generates a pulse having a predetermined time width T based on a clock from a crystal oscillator, for example. 2 is a signal input terminal, 3 is a switch, 41, 42, 43, ..., 4n is an invertor gate (delay unit), 5 is a delay line (delay means) composed of a delay unit, and 6 is a delay time measuring device. , 71,72,73, ...,
7n is a latch circuit, 8 is an encoder circuit, 9 is a multiplier, 10
Is a delay time set value input terminal, 11 is a switcher, and 12 is a signal output terminal. The delay line 5 is an in-inverter gate (41, 42,
43, ..., 4n) are cascade-connected in n stages. Further, the delay time measuring device 6 includes the above n non-inverter gates 41 to 41.
4n) n latch circuits 71 that use each output as a clock
7n and an encoder circuit 8.

The encoder circuit 8 inspects the output of the latch circuit 7 in the direction from the first stage to the rear stage of the delay units 41 to 4n, and determines the number of stages of the delay units 41 to 4n at the place where the difference from the output of the previous latch circuit 7 appears for the first time. taking measurement.

Here, the operation in the delay time measurement will be described with reference to FIGS. 3, 4, and 5. The switch 3 is normally on the b side and supplies the signal from the signal input terminal 2 to the delay line 5. However, when measuring the delay time, the switch 3 is connected to the a side and the delay time from the pulse generator 1 is measured. A pulse signal S0 having a predetermined time width T is supplied to the delay unit 41 at the first stage and the DATA inputs of all the latch circuits 7. As shown in FIG. 4, as the number of stages of the delay units 41 to 4n becomes deeper, pulse signals S1, S2, S3, ..., Sn having a longer delay time can be obtained. Delay unit 41 to 4n with each latch circuit 71 to 7n
When the input pulse signal S0 is latched at the rising edge of the pulse signal delayed by various times obtained by, when latching with the pulses S1, S2, S3, S4 in Fig. 4, the H level is obtained as the latch result, and the pulse When latched by S5, S6, ..., Sn, the latch result becomes L level. That is, the third
The results of the latch circuits 71, 72, 73, 74 in the figure are H level,
The result of the latch circuits 75, ..., 7n in the subsequent stage becomes L level.

Further, the results obtained by the latch circuits 71 to 7n are supplied to the encoder circuit 8. This encoder circuit 8 is, for example, a parity encoder (for example, Texas Instruments Co., Ltd.) in the TTL-IC shown in FIG. Made of SN74
LS148) consists of single or subordinate connections. In the figure, D1, D2, ..., D8 correspond to the input terminals D1, D2, ..., D8 of the encoder circuit 8 in FIG. 3, and the first stage latch circuit 71
Are sequentially associated with D1, D2, ... In FIG. Also, A0 (LSB), A1 and A2 in FIG. 5 correspond to the output A (predetermined time delay stage number) of the encoder circuit 8 in FIG. 3, and are supplied to the multiplier 9 as multi-bit data. There is. When the latch result of FIG. 4 is input to the input terminals D1, D2, D3, D4, ... Of FIG. 5, A = 4 (A2 =
The result of "H", A1 = "L", A0 = "L") is output. The result A means that it is necessary to connect the delay units in four stages in cascade to form the delay of the predetermined time width T.

After all, in order to obtain the delay of αT time as the entire delay device shown in FIG. 3, the data of the coefficient α is input from the delay time setting input terminal 10, and the multiplier 9 multiplies the predetermined time delay stage number A by the coefficient α. Then, the switch 11 is controlled based on the multiplication result αA. Here, if A = 4 and α = 0.5, αA = 2, and the switcher 11 selects the input of the second P2 terminal (the output of the second stage 42 of the delay unit), and the delay device as a whole has a value of 0.
A delay time of 5T can be realized. Also, if the gate delay characteristics change due to power supply voltage fluctuations and environmental temperature changes, and the delay of the delay unit is halved, A = 8, and when α = 0.5, αA = 4, and the switch 11 is the fourth P4 terminal. The input of (the output of the fourth stage 44 of the delay unit) is selected, and similarly, a delay time of 0.5T can be realized as a phase shifter.

Next, another embodiment of the phase shifter 20 used in FIG. 1 will be described with reference to FIG. FIG. 6 is the same as FIG. 3 in terms of components. However, the connection between the components is different, and the pulse signal S0 of the switch circuit 3 is supplied to the delay unit 41 of the first stage and the clock inputs of all the latch circuits 71 to 7n. Further, the pulse signals S1, S2, S3, ..., Sn output from the delay units 41-4n are respectively latch circuits 71, 72, 73 ,.
It is supplied to the 7n data input terminal D. That is, the clock input and the data input of the latch circuits 71 to 7n are interchanged.

Here, the operation in the delay time measurement will be described with reference to FIGS. 6 and 4. Pulse signals S1 obtained by the delay units 41 to 4n and delayed for various times in the respective latch circuits 71 to 7n
When ~ Sn is latched at the trailing edge of the input pulse signal S0,
In FIG. 4, when latching the pulse signals S1, S2, S3, S4,
As a result of latching, H level is obtained and pulse signals S5, S6,
When latching ..Sn, the latch result becomes L level. That is, the result of the latch circuits 71, 72, 73, 74 in FIG. 6 is H level, and the latch circuits 75, ...
Results in L level. The result obtained here is the third
The same result as the first embodiment of the present invention shown in the figure,
The same operation as that of the first embodiment can be realized as the phase shifter.

As described above, in the delay line in which the delay unit having the minimum unit delay time is connected in cascade, the circuit for measuring the delay time of the delay line is provided and the delay time of the delay unit is measured every moment. , The desired delay time is multiplied by the reciprocal of the delay time of the delay unit and the phase shifter configured to automatically select the number of stages of the delay unit based on this result is always stable. It is possible to obtain a long delay time.

Therefore, in the present invention, by combining this phase shifter, the PLL circuit, and the phase shift modulation signal generator, it becomes possible to create a color subcarrier having a 25 Hz offset like the PAL system from the horizontal synchronizing signal. It was

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a color subcarrier generating device in an embodiment of the present invention, FIG. 2 is a block diagram showing a detailed configuration of a phase shift modulation signal generator in the embodiment, and FIG. FIG. 4 is a block diagram showing a first configuration example of the phase shifter in the embodiment, FIG. 4 is a timing chart for explaining the operation of the phase shifter, and FIGS. 5 (a) and 5 (b) are the phase shifters. 6 is a block diagram showing an example of an encoder circuit used in FIG. 6 and its explanatory view, and FIG. 6 is a block diagram showing a second configuration example of the phase shifter in the same embodiment. 1 ... Pulse generator (pulse generation means), 41 to 4n ... Delay unit, 5 ... Delay line (delay means), 6 ... Delay time measuring device (delay stage number measuring means), 71 to 7n ... Latch Circuit (latch means), 8 ... Encoder circuit (encoding means), 9 ... Multiplier (multiplication means), 11 ... Switching device (selection means), 18 ... Sync separation means, 19 ... Phase shift modulation signal Creating means, 21 ... Phase comparing means, 22 ... Low-pass filter, 23 ... Voltage controlled oscillating means, 25 ... PLL (multiplier means), 26 ... Color subcarrier output terminal, 193 ... Counter.

Claims (4)

(57) [Claims] 1. A sync separation means for separating a horizontal and a sync signal from a video signal, and a phase modulation signal creation means for creating a phase shift modulation signal α based on the horizontal and vertical sync signals from the sync separation means. A phase shift means for controlling the phase of the horizontal synchronizing signal from the sync separating means, which is controlled by the phase shift modulating signal α, and a multiplying means for multiplying the output of the phase shifting means by frequency to obtain a color subcarrier, The phase shift means comprises: delay means configured by cascade-connecting N stages of delay units having a minimum unit delay time; and inputting a reference signal to the delay means and delaying by a predetermined time T. Delay stage number measuring means for measuring the number of stages of the delay unit constituting the delay means, selecting means for selecting an output of each stage of the delay unit, and the phase shift modulation signal for the output value K of the delay stage number measuring means.
And a multiplication means for controlling the selection means by a multiplication result αK obtained by multiplying the color subcarrier generation device. 2. The phase shift modulation signal creating means presets the phase shift modulation signal α to a predetermined value by a vertical synchronization signal, and adds or subtracts a constant value for each horizontal synchronization signal or each clock synchronized with the horizontal synchronization signal. And the phase shift modulation signal α
The color subcarrier generator according to claim 1, wherein 3. A delay stage number measuring means, a pulse generating means for generating a pulse signal having a width of a predetermined time T, a latch means provided for every n delay units, and an output of the latch means. Encoding means, inputting the pulse signal of the pulse generating means to the delay means, and at the same time connecting to the data input terminals of all the latch means, and the outputs of the n delay units corresponding to the respective latch means. It is connected to a clock terminal, the latch means latches the pulse signal of the pulse generating means at the leading edge of the pulse signal of the delay means, and the encode means latches the pulse signal of the latch means in the direction from the first stage to the rear stage of the delay unit. Check the output, and check the output of the delay unit at the place where the first difference from the output of the previous latch means appears. The color subcarrier generator according to claim 1, wherein the number of stages is measured. 4. A delay stage number measuring means, a pulse generating means for generating a pulse signal having a width of a predetermined time T, a latch means provided for every n delay units, and an output of the latch means. Encoding means for inputting the pulse signal of the pulse generating means to the delay means and at the same time connecting to the clock terminals of all the latch means, and the outputs of the n delay units corresponding to the data of the latch means. Connected to an input terminal, the latch means latches the pulse signal of the delay means at the trailing edge of the pulse signal of the pulse generating means, and the encode means outputs the output of the latch means in the direction from the first stage to the latter stage of the delay unit. Is checked, and the number of stages of the delay unit is measured at the place where the first difference from the output of the previous latch means appears. The color subcarrier generator according to claim 1, wherein the color subcarrier generator is configured to measure.