JP2543058B2 - Semiconductor memory device - Google Patents

Description

[Detailed Description of the Invention] [Outline] A MOS capacitor is directly attached to a word line or a column line,
By pushing up through the capacitor,
Reduce the power of the decoder or the power of the clock for push-up.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a word line and column line driving circuit for DRAM.

[Conventional technology]

As shown in FIG. 5, a D (dynamic) RAM has a large number of word lines WL ₁ , WL ₂ , ... And bit lines BL ₁ , BL ₂ ,.
▼ ₁ , ▲ ▼ ₂ , ... 1-transistor 1-capacitor type memory cell MC is arranged at each intersection, and the word line is selected by the word decoder WD at the time of reading, thereby turning on the cell transistor and setting the cell capacitor to the bit. Connected to the line, the bit line voltage is changed according to the cell data, the differential voltage thus generated on the bit line is amplified by the sense amplifiers SA ₁ , SA ₂ , ... And the gate (G ₁ , G ₂ , ... 1) and open the H of the bit line.
(High) and L (low) potentials are taken out to the data bus DB, ▲ ▼.

When writing, according to the write data, data bus DB,
▲ ▼ is set to H, L, _{one of} the column gates G ₁ , G ₂ , ... is turned on according to the column address, and the relevant bit line BL, ▲
▼ is set to H, L, a word line is selected according to the word address, the transistors of all the memory cells belonging to the word line are turned on, and the memory cells belonging to the selected bit line of these memory cells are set to the H, L Write L potential.

The H and L potentials applied to the data bus are H when the power is Vcc and L is Vss.
(0V) In order for Vcc to be written to the selected memory cell, there must be no voltage drop in the column gate transistor and cell transistor, and therefore the gate voltage of these transistors should be pushed above Vcc. Take

FIG. 4 shows a conventional example of a word line drive circuit. In DV word driver, the word line through the transistor Q ₁ WLi (i
= 1,2, ...) is driven. Inverter for DV output line Li
I ₁ , I ₂ and MOS capacitor C ₂ are connected, and transistor Q ₁
A capacitor C ₁ is connected between the drain and the gate of the word decoder, and a word decoder for one word line WD is connected to the gate of the Q _1.
The output end of i is connected. The word decoder consists of NOR gates, and the added address bits A ₀ and ₀ , A _1
If each one of ₁ , ... is L, the output becomes H. The H output charges the capacitor C ₁ to the polarity shown, the transistor Q ₁
Turn on. Thus driven by the word line LWi output through Q ₁ becomes H level driver DV becomes H level, and the delay caused by the inverters I _1, I ₂ because the capacitor C ₂ is charged to the illustrated polarity output H of the DV After that, when the negative side of the capacitor becomes H level, the capacitor outputs the output line Li.
Is pushed above the H level (Vcc) above, the gate of Q ₁ is pushed up further through C ₁ to keep Q ₁ completely on, and word line WLi is pushed above Vcc through this Q _1. increase.

Transistor Q ₂ is for reset and turns on when signal RST is input, connecting the word line to ground. The bootstrap circuit of the column decoder output has the same structure.

[Problems to be solved by the invention]

However, in the conventional circuit of FIG. 4, the word decoder WD
i needs to charge the gate of transistor Q ₁ to about Vcc with its output. The word decoder is a part of the memory that consumes a lot of power, and if the output voltage of the word decoder is high, the power consumption of the entire memory becomes large. Moreover, since the capacitor C ₂ pushes up the transistor Q ₁ and the word line WLi, the capacitance of the capacitor must be large. Further, since the output of the driver DV charges C ₂ , this also needs to be large, which also causes an increase in power consumption. The present invention seeks to improve these points.

[Means for solving problems]

In the semiconductor memory device of the present invention, a common signal line (CX) is provided for a plurality of output lines of the column decoder, and a capacitor is connected between each of the common signal line and the plurality of output lines of the column decoder. Then, after the column decoder output line rises, the signal line (CX) is raised and the column gate output line is pushed up.

[Action]

In this memory device, the output voltage of the word / column decoder can be lowered by a simple means of connecting a MOS capacitor between each word line and signal line and between the column decoder output line and the signal line. Since it is not necessary to connect a large-capacity push-up capacitor to the output line of, the memory power consumption can be reduced, which is extremely effective.

〔Example〕

An embodiment of the present invention is shown in FIG. 1, and the same parts as those in FIG. 4 are designated by the same reference numerals. As is clear from comparison with FIG. 4, in the present invention, the push-up circuit composed of the inverters I ₁ , I ₂ and the capacitor C ₂ is not used for the output line Li of the word driver DV, but instead of each word line WLi, One of the electrodes of the MOS capacitors Ci, Cj is connected to WLj, ... And the other electrodes of these capacitors are connected to the signal line PX.

The operation of FIG. 1 will be described with reference to the waveform diagram of FIG. 3. Now, assuming that the word line WLi is selected (specifically, it is selected), the output of the row (word) decoder WDi is at the H level. become. That is, the node N1 becomes H. The node N1 and H level is Vcc-V _TH fell by the threshold voltage V _TH of the transistor Q _5. The transistor Q ₆ is turned on by receiving the signal PM (= Vcc-V _TH ) at its gate,
N2 is Vcc-2V _TH . The capacitor C ₁ is charged by this voltage. After that, the signal PX goes to L, then the output Li of the word driver DV (here, the same sign is used for the line and its signal) rises, and the word line WLi is passed through the transistor Q _1.
Is launched. At the rising edge of Li, the node N2 is pushed up via C ₁ as shown in the figure, and becomes higher than Vcc. After that, the signal line PX becomes H, and at this time, the word line WLi is pushed up to Vcc or higher by the capacitor Ci as shown in the figure. The unselected word lines WLj and the like are not pushed up by the capacitors Cj and the like.

That is, when the word line WLi is selected and the output Li of the driver DV causes WLi to rise above the threshold value (about 1V) of the MOS capacitor, the capacitor Ci is generated, and the WLi side is charged to + and the PX side is charged to −. The potential of the selected word line does not rise, and the capacitor Cj or the like does not occur. If the signal line PX is started up in this state, the bootstrap pushes up the selected word line.
Only the WLi does not push up the other non-selected word lines WLj and the like, and is at the L level.

The output of the word decoder in the circuit of the FIG. 1 may be a low voltage (Vcc-V _TH), it is not necessary to charge the node N2 (Q ₁ of the gate) a high voltage (or Vcc). Also, the word driver DV only needs to lift the signal line Li, the transistor Q ₁ , and the word line WLi slightly (above the threshold of the MOS capacitor),
It is not necessary to push these above Vcc as shown in FIG. As a result, the power consumption of the memory can be kept low, and the large-capacity capacitor C ₂ becomes unnecessary. Further, in order to completely turn off Q ₁ and enhance the boost effect, a transistor Q ₇ having a gate of PX can be provided as shown in FIG.

 In this case, the movement of N2 in FIG. 3 becomes like a dotted line.

Note CLi, CLj in clamps, it becomes Q ₃ on, Q ₂ off when the word line example WLi is selected, there is no hindrance to the word line selected. When WLi is not selected by the word line this example, Q ₄ on contains a reset signal R, Q _2-one, becomes Q ₃ off, clamps the word line WLi to ground.

FIG. 2 shows an example in which the present invention is applied to the output line of the column decoder. CDi indicates one bit line pair of the column decoder. BLi, ▲ ▼ i is the one bit line pair, and Gi, i is a column gate connecting this bit line pair to the data bus DB, ▲ ▼. The column decoder CDi turns on / off this column gate Gi, i, but in order to transmit Vcc, Vss of DB, ▲ ▼ to BLi, ▲ ▼ i as it is, the gate voltage of Gi, i (MOS transistor) must be higher than Vcc. There is a need to.
Conventionally, the output of the column decoder CDi is set to Vcc or higher, but in this circuit, a signal line CX and a MOS capacitor Ci are provided instead. One electrode of the capacitor Ci is connected to the output line L _C of the column decoder, and the other electrode is connected to the signal line CX.

The operation is the same as in FIG. That is, the column decoder CDi
When the output rises above the threshold voltage of the MOS capacitor, a capacitor Ci is generated, and the capacitor Ci is charged by the column decoder output so that the signal line L _C side is positive and the CX side is negative.
Then, when the signal line CX is raised to Vcc, the signal line L _C is set to V by Ci.
It is activated above cc, and as a result, Gi, i is completely turned on and Vcc level can be transmitted.

〔The invention's effect〕

As described above, according to the present invention, the output voltage of the word / column decoder is lowered by the simple means of connecting the MOS capacitor between each word line and the signal line and between the column decoder output line and the signal line. Therefore, it is not necessary to connect a push-up large-capacity capacitor to the output line of the word driver or the like, and the memory power consumption can be reduced, which is very effective.

[Brief description of drawings]

1 and 2 are circuit diagrams showing an embodiment of the present invention, FIG. 3 is a waveform diagram for explaining the operation, FIG. 4 is a circuit diagram showing a conventional example, and FIG. 5 is a main part configuration of DRAM. It is a circuit diagram shown. In FIGS. 1 and 2, WL is a word line, BL is a bit line, MC is a memory cell, WD is a word decoder, CD is a column decoder,
L _C is an output line of the column decoder, PX and CX are common signal lines, Ci,
Cj is a MOS capacitor.

Claims (1)

(57) [Claims] 1. A column is provided with a common signal line (CX) for a plurality of output lines of a column decoder, and a capacitor is connected between each of the common signal line and the plurality of output lines of the column decoder. A dynamic semiconductor memory device characterized in that after the decoder output line rises, the signal line (CX) is raised and the column gate output line is pushed up.