JP2542582B2 - Inductance load drive circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit, and more particularly to a drive circuit that prevents malfunction and destruction of output transistors when an inductance load is driven at high speed.

[Conventional technology]

In general, an inductance load drive circuit is a circuit for driving a solenoid in an engine control system, a transmission control system, etc. in the field of automobile electrical equipment, and switches an output transistor according to an input signal to supply or cut off a current to a solenoid coil. As a result, the inductance load such as a relay is disconnected and the engine and the transmission are controlled.

FIG. 2 shows an example of a conventional drive circuit. In this inductance load drive circuit, the output of drive element 2 is NP
It is connected to the base of the N-transistor Q _2, the drive element 2
NPN with resistors R ₁ and R ₂ connected between the output and the output terminal 4, the emitter connected to the output terminal 4, the collector connected to the base of the NPN transistor Q ₂ , and the base connected to the intersection of the resistors R ₁ and R _2. includes a transistor Q _1, the collector of the NPN transistor Q ₂ emitter of NPN transistor Q ₂ is the output terminal 4 is connected to a power source 3.

In this drive circuit, the output transistor Q ₂ is driven by the signal applied to the input terminal 1 to drive or cut off the inductance load 5. It should be noted that, when the output terminal 4 is grounded, the current limiting circuit composed of the resistors R ₁ and R ₂ and the transistor Q ₁ increases the output terminal current I _O and causes the transistor Q ₂
The base voltage-emitter forward voltage drop V _BE of the transistor Q ₁ spreads and the base potential V _BI of the transistor Q ₁ increases
₁ conducts, bypasses a part of the drive current of the transistor Q ₂ , and acts to suppress an extreme increase in the output terminal current I _O.

[Problems to be solved by the invention]

In the above-mentioned conventional drive circuit, when driven by high-speed pulses, the following problems occur. That is, when the input signal V _IN as shown in FIG. 3 is applied in FIG. ₂ , the output transistor Q ₂ becomes non-conductive at time t ₁ and the current I _O flowing through the inductance load 5 is cut off. Since the current I _O ′ flows through the clamping diode 6 by the counter electromotive force of 5, the output terminal voltage V _O is clamped by the forward voltage drop V _F6 of the diode 6 and becomes a voltage lower than the ground by V _F6. . Here, the absolute value of the forward voltage drop V _F6 increases due to the current I _O ′ flowing through the diode 6 and the resistance component such as the operating resistance of the diode 6, and V _F6 becomes the forward voltage drop between the base and the emitter of the transistor Q _2. When V _BE 2 units, that is, V _F6 <−1.4 V, the base potential V _B2 of the transistor Q ₂ is V _BE = 0.7 V
_{Since B2} = -1.4V + 0.7V = -0.7V, the collector potential of the transistor Q ₁ which is an N-type semiconductor will be lower than the potential of the substrate of the semiconductor integrated circuit (P-type semiconductor in this case), and the parasitic NPN A transistor Q _N is formed. For example,
As shown in Fig. 3, the frequency of the input signal V _IN is 5 kHz and the duty is 50
%, The period during which the output transistor Q ₂ is non-conducting
Since t _{1 to} t ₂ are as short as 100 μs, the counter electromotive force of the inductance load 5 is not sufficiently discharged. Therefore, the output terminal voltage
V _O will remain -0.7 V, the parasitic transistor Q _N continues to conduct, driving the transistor Q ₂ with a current I _N.

As a result, the transistor Q ₂ does not become non-conductive even when the input signal V _IN changes from low level to high level.
The output terminal current I _O does not become zero, and the current ΔI _O (ΔI _O = I _N × h
_FE Q ₂ ; h _FE flows the DC current amplification factor of transistor Q ₂ , and when the inductance load 5 is driven, the state of this load 5 changes even if the input signal V _IN changes from low level to high level. There are times when you don't. Further, at this time, if the voltage V _{CC of the} power supply 3 becomes high, the output transistor Q ₂ may be destroyed. That is, during the time t _{0 to} t _{1 in} FIG. 3, the collector-emitter voltage of the transistor Q ₂ is
V _CE is a V _CE ≒ 1.2V for the transistor Q ₂ is saturated, but the power consumption of the transistor Q ₂ as an output terminal current I _O = 3A is a P _D = 1.2V × 3A = 3.6W in between times t ₁ ~t _2, when the power supply voltage V _CC = 30 V, the current [Delta] I _O = 0.5A, since V _CE = V _CC -V _O of the output terminal voltage V _O = -1.4V = 30V-
(-1.4V) = 31.4V, P _D = 31.4V x 0.5A = 15.7W. Thus, leading to destruction of the transistor Q ₂ to cross the safe operating area of the transistor Q ₂ becomes overpower (SOA).

[Means for solving problems]

The inductance load drive circuit of the present invention includes: a first transistor having a base to which an input signal is supplied, a collector connected to a first power supply terminal, and an emitter connected to an output terminal; and the output terminal and the second power supply terminal. An inductance load connected between the output terminal and a diode connected between the output terminal and the second power supply terminal, and a voltage corresponding to the difference between the level of the input signal and the level at the output terminal. A second transistor having a collector-emitter path connected between the base and the emitter of the first transistor, and a collector of the first transistor and the collector of the first transistor when the first transistor is driven at high speed. Second
A third transistor which provides the second transistor with a current output by a parasitic transistor formed between the collector of the second transistor and the collector of the second transistor.
Is connected to the base of the transistor of
A third transistor whose base is connected to the power supply terminal of the second transistor and whose base is connected to the collector of the second transistor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, the output of the drive element 2 is connected to the base of the NPN transistor Q ₂ , resistors R ₁ and R ₂ are connected between the output of the drive element 2 and the output terminal 4, and these resistors R ₁ and R ₂ are connected. The base of the NPN transistor Q ₁ is connected to the intersection of ₁ and R ₂ , the emitter of the transistor Q ₁ is connected to the output terminal 4, and the collector of the transistor Q ₁ is connected to the base of the transistor Q ₂ . Here, the resistors R ₁ and R ₂ and the transistor Q ₁ form a current limiting circuit. Further, the emitter of the transistor Q ₂ is connected to the output terminal 4 and the collector is connected to the power supply 3. Also, ground the emitter, base to the collector of transistor Q ₁ and collector to the transistor.
It has a PNP transistor Q ₃ connected to the base of Q ₁ . The inductance load driving circuit configured as described above operates according to the input signal from the input terminal 1, and also drives the inductance load 5 connected to the output terminal 4. Note that reference numeral 6
Is a diode for clamping.

 Next, the operation of one embodiment will be described.

In FIG. 1, when the input signal V _IN as shown in FIG. 3 is applied, the output terminal voltage V ₀ drops to −1.4 V at time t ₁ when the transistor Q ₂ becomes non-conductive as in the conventional circuit. _second base voltage V _B2 = -0.7 V becomes parasitic transistor Q _N is generated. This parasitic transistor Q _N tries to drive the transistor Q ₂ with the current I _N ,
Output terminal voltage V ₀ = -1.4V because transistor Q ₃ exists
At that time, the parasitic transistor Q _N is generated, and at the same time, the transistor Q ₃ becomes conductive, and the transistor Q ₁ is driven by the current I _C3 . This causes transistor Q ₁ to be overdriven and saturated, and transistor Q ₁
Output saturation voltage V _CE (sac) of the base of transistor Q ₂
Since it becomes smaller than the emitter-to-emitter voltage V _{BE and} also draws the current I _N from the transistor Q _N , the transistor Q ₂ does not conduct. After that, the output terminal voltage V ₀ is clamped by the forward voltage drop V _F6 of the clamping diode 6, and is clamped at a voltage lower than the ground by V _F6 , for example, −0.6 V, so that the parasitic parasitic current that has been conducted. Turn off transistor Q _N.

Therefore, the current ΔI _O flowing into the inductance load 5 between times t _{1 and} t ₂ in FIG. 3 becomes negligible. In the case of the conventional circuit shown in FIG. 2, ΔI _O is represented by ΔI _O = I _N × h _FE Q ₂ , and if I _N = 3.3 mA and h _FE Q ₂ = 150, then ΔI _O = 0.50 A . On the other hand, in the case of the above-mentioned embodiment, ΔI _O = I _C Q ₁ + I _B Q ₁ , and I _C Q ₁ = I _N = 3.3 mA
And I _B Q ₁ = I _C Q ₃ , and assuming that transistor Q ₁ is saturated and h _FE in the saturated state is small and h _FE = 10, I _B Q ₁ = I _C
Q ₃ = I _{N /} 10 = 0.33mA. Therefore, in this embodiment, ΔI _O is ΔI _O = 3.3mA + 0.33mA = 3.63mA.
As a result, when comparing the [Delta] I _O of [Delta] I _O and the conventional circuit of this embodiment, a [Delta] I _O is negligible values of the embodiment and 3.63MA (embodiment) "0.50 A (prior art circuit), substantially It doesn't matter if it doesn't flow. Moreover, even if 3.63 mA is considered, the power consumption P _D at that time is P _D = 31.4 V × 3.63 mA
= 0.1W, which does not exceed the safe operating area (SOA).

〔The invention's effect〕

As described above, according to the present invention, the output transistor is driven by the high-frequency input signal, and even if the parasitic transistor is generated due to the back electromotive force of the inductance load, the output transistor is reliably cut off. There is nothing to do. Further, even when the power supply voltage is high, the output transistor is not destroyed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example, and FIG. 3 is a diagram for explaining the operation of the drive circuit shown in FIG. 2 ...... drive element, 3 ...... power, 5 ...... inductive load, Q _1, Q ₃ ...... transistor, Q ₂ ...... output transistor, Q _N ...... parasitic transistor.

Claims (1)

(57) [Claims] 1. A first transistor having a base to which an input signal is supplied, a collector connected to a first power supply terminal, and an emitter connected to an output terminal; and a first transistor connected between the output terminal and a second power supply terminal. The inductance load, a diode connected between the output terminal and the second power supply terminal, and a voltage corresponding to the difference between the level of the input signal and the level at the output terminal is applied to the base. A second transistor having a collector-emitter passage connected between the base and the emitter of the first transistor; and a collector of the first transistor and the second transistor when the first transistor is driven at high speed. A third transistor for providing the second transistor with a current output by a parasitic transistor formed between the collector of the third transistor and the collector of Inductive load driving circuit emitter connected to the base of the second transistor is characterized in that it comprises a third transistor having a base connected to said second power supply terminal is connected to the collector of the second transistor.