JP2541528B2 - LRU error processing method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to an LRU error processing system for a cache storage device.

(Prior Art) In a set-associative cache memory device, the main memory is divided into blocks of 2 ⁿ bytes each. Further, the lower n bits of the memory address represent the address in the block. A set of blocks whose lower m bits of block addresses are the same except for the lower n bits is called a set, and the main memory is divided into 2 ⁿ sets. There are usually multiple blocks in the cache memory for each set, each called a level. That is, if the number of levels is 1, it is possible to have 1 memory blocks in the cache memory in which the lower m bits of the block address are the same for each set and the remaining upper bits are different. The above configuration is shown in FIGS.
Shown in the figure. Since the upper address of the storage block differs for each level of each set, a storage device group for storing these is necessary. This storage device group is called an address array.

Now, when transferring one memory block in the main memory device to the cache memory device, an unused level in the cache memory block of l level corresponding to the set determined by the lower m bits of the block address. If there is not one, it is necessary to replace the block stored in any one level from the cache and replace it. At this time, there are several methods to determine the level to be evicted, but the method to evict the earliest referenced block is LR as it is likely to be least frequently used.
Called the U method, it is widely used today.

In the LRU method, an LRU memory is provided for each set, and a history of the order in which l levels are referred to is stored. At the time of replacement, only one level to be replaced is selected and designated by the LRU logic.

Now, if this LRU logic is instructed to replace 0 or more levels, it is impossible to determine a certain level and the processing is stopped. Influence. However, in order to avoid this, if the LRU memory and LRU logic are duplicated, even if the deterioration of performance can be completely prevented, the increase in the amount of hardware for that and the increase in the cache capacity will be great. The amount of hardware will increase.

(Problems to be Solved by the Invention) In the above-mentioned conventional LRU method, since each bit has an LRU memory, if it is instructed to replace 0 or more levels of LRU logic, However, there is a drawback in that a certain level cannot be determined, which seriously affects the system performance. In order to avoid this, if the LRU memory and the LRU logic are duplicated, there is a drawback in that the amount of hardware will increase even though the deterioration of performance can be prevented.

In order to reduce this drawback as much as possible, LRU
As an error handling method, if a situation occurs where the block to be replaced cannot be determined due to an error in the LRU circuit, one of the associative level blocks that has not been terried is selected. A method has been proposed in which blocks are to be fixedly replayed (Japanese Patent Laid-Open No. 58-45682). This method is effective for intermittent failures, but for fixed failures, cache memory performance , And consequently the instruction processing capability is unavoidable. Moreover, even if fixed failures are less than intermittent failures, they cannot be ignored, so an effective system is expected even when fixed failures occur.

In order to meet such an expectation, an object of the present invention is to determine one storage block to be replaced by the LRU method, and to make it possible to detect an abnormality in the instruction when instructing the abnormality. If a random number is generated, a random number is generated in the random number circuit in consideration of the cache allocation prohibition level and the cache non-implementation level, and a replacement block is generated instead of the above instruction. By providing the LRU error handling method configured to eliminate the above drawbacks and prevent performance degradation in both intermittent and fixed failures without increasing the amount of hardware. To do.

(Means for Solving Problems) The LRU error processing method of the present invention is such that when one storage block to be replaced by the set associative method cache storage device is determined and instructed by the LRA method, the abnormality of the instruction is given. Abnormality detecting means for detecting the error, a random number circuit for generating level numbers of the cache memory with equal probability, and if the abnormality detecting means does not detect an abnormality, the instruction is selected, and the abnormality detecting means detects an abnormality. Then, the selecting means for selecting the output of the random number circuit and outputting it as the target of cache replacement.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment for realizing the LRU error processing system according to the present invention. In FIG.
11 is a requested memory address register, 111 is a memory block address upper bit, 112 is a memory block address lower bit, 113 is an address area in the block, 12 is an address array, 13 is an LRU memory, 14 is an address comparison circuit, 1
5 is an LRU logic circuit, 16 is an error detection circuit, 19 is a random number circuit,
Reference numeral 18 is a first selector for selecting an LRU output or random number circuit 19 output, and 17 is a second selector for selecting an unallocated level or an LRU instruction level.

When a memory access request is sent to the memory control unit from the arithmetic unit or the input / output unit, the lower part of the memory block address in the request address register 11, that is, the contents of the set address 112, is transferred to the address arrays 12 and L.
It is sent to the RU memory 13 and its contents are read out.
The upper address of each cache level of the set read from the address array 12 is compared with the upper address of the request address (memory block address upper bit) 111 in the address comparison circuit 14. As a result of comparison, if there is a match, the level number C is output.

In this case, since the necessary memory data exists in the cache, it is treated as a cache hit, and the requested block is processed as requested. In this case, the data read from the LRU memory 13 is ignored.

When there is no cache hit, that is, when there is no matching level in the address comparison by the address comparison circuit 14, a cache miss occurs and the requested address is sent from the main memory to the cache memory (request memory address area 11 It becomes necessary to transfer a memory block containing At this time, as the transfer destination, only one appropriate level must be selected from the levels of the corresponding sets in the cache memory. However, if there is at least one unallocated level with no valid data written, that level is selected as the transfer destination. If there are a plurality of unassigned levels, either one may be selected, but the lowest level is usually selected. This selection is performed by the address comparison circuit 14 based on the data read from the address array 12,
The number (f) of the selected unused level is output from the second selector 17 as the cache assignment designated level signal (d) by the control signal (e).

Similarly, in the case of a cache miss, if valid data exists at all levels of the relevant set of caches, the contents of the block of any one level must be removed, and the necessary memory data must be transferred after that. I won't.
At that time, which level is selected is determined by the LRU logic circuit 15 based on the contents of the LRU memory 13, and is designated as the cache assignment designated level number (d) through the first selector 18 and the second selector 17. Is output. Further, in the case of either the cache hit or the cache miss, the contents of the LRU memory 13 corresponding to the set are updated, and the level assigned in the memory access is rewritten so as to become the latest access level.

At this time, a failure occurs in the LRU memory 13 or the LRU logic circuit 15, and an unimplemented level is instructed, two or more levels are instructed at the same time, or neither level is instructed. If it falls, the error detection circuit
The above state is detected by 16. Therefore, by switching the first selector 18, the output of the random number circuit 19 is sent to the second selector 17 instead of the signal from the LRU logic circuit 15.

In a normal state, the random number circuit 19 randomly generates all the level numbers of the cache memory with equal probability. However, when any of the cache memory levels is designated to be prohibited by the degradation level designation signal (a), when a random number indicating the level is generated, a number larger than the random number is output. .
Here, if the level selected in this way is also prohibited from being assigned, a further higher level number is designated. If the level with the highest level number is forbidden to assign, the level with the lowest number is selected instead.

Even when a low-cost system with a small number of cache memory levels and a small capacity is configured, unused levels can be dealt with by prohibiting allocation in the same manner as described above.

However, since generally implemented levels are assigned consecutive level numbers, when random numbers indicate unimplemented levels, the lowest number of implemented levels is indicated. That is, for example, if there are 4 levels of mountable levels 0 to 3 and only 2 levels of 0 and 1 are mounted, if a random number of 2 or 3 levels is generated, the designated level is Both of them are level 0, and the probability that level 0 is instructed is 3/4 of the total.

In order to avoid this bias, a method of inputting the cache mounting level number designation signal (b) to the random number circuit 19 and limiting the range of random numbers generated by this signal is adopted.
Specifically, if the mounting level is two levels of 0 to 1 and the generated random number is in the range of 0 to 3, the upper 1 bit of the binary representation of the level number of the generated random number is treated as 0. Thus, the random number in the range of 0 to 3 can be treated as the random number in the range of 0 to 1.

(Effect of the invention) As described above, the present invention determines one memory block to be replaced by the LRU method, and when instructing, it is possible to detect an abnormality after the instruction, If an abnormality is detected, a substitution block is generated instead of the above instruction, so a random number is generated by a random number circuit in consideration of the cache assignment prohibition level and the cache non-implementation level, and either the above instruction or the random number circuit is generated. By selecting the output of, when an LRU error occurs,
The failure has an effect that it can be dealt with without stopping the system.

In addition, even if the error is due to the intermittent failure of the LRU memory or the fixed failure, if the range is limited, it is possible to continue the processing by limiting it to a range where the performance degradation of the memory system can be ignored. There is an effect to say.

Furthermore, the hardware required for this method is extremely small,
Even if the number of cache levels is increased, only a small increase in the amount of hardware is required, which is economical. Further, even when the number of cache levels is reduced and used, the same function can be exerted. Furthermore, LR
U By selecting the replacement target level at the time of failure with a random number, all cache levels can be effectively used even at the time of failure, especially when fixed levels are fixed compared to when replacement is fixed. There is an effect that the performance deterioration of is minimal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an LRU error processing system according to the present invention. FIG. 2 is an explanatory diagram showing memory addresses. FIG. 3 is a conceptual diagram showing cache memory of the set associative system. 11 …… Request memory address register 111 …… Memory block address upper bit 112 …… Memory block address lower bit 113 …… Internal block address 12 …… Address array 13 …… LRU memory 14 …… Address comparison circuit 15 …… LRU logic Circuit 16 …… LRU error detection circuit 17,18 …… Selector 19 …… Random number circuit 31 …… Unit set of memory and cache 32 …… Unit block in cache a ～ f …… Signal

 ─────────────────────────────────────────────────── --- Continuation of the front page (56) Reference JP-A-58-45682 (JP, A) JP-A-60-176156 (JP, A) JP-A-53-109441 (JP, A) JP-A-49- 62047 (JP, A) JP 47-7506 (JP, A) JP 58-35641 (JP, A) JP 56-8426 (JP, B2)

Claims (1)

(57) [Claims] 1. An abnormality detecting means for detecting an abnormality in the instruction when a storage block to be replaced in a set associative cache storage device is determined and instructed by the LRU method, and a cache memory level. A random number circuit that generates numbers with equal probability, and selects the instruction if the abnormality detection unit does not detect an abnormality, and selects the output of the random number circuit when the abnormality detection unit detects an abnormality and selects a cache replacement target. An LRU error processing method, comprising: