JP2541234B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for forming multi-layer wiring on a substrate made of a material having a thermal expansion coefficient equivalent to that of a semiconductor element substrate, in which the distance between conductive holes is small and the semiconductor has a thermal expansion coefficient. A step of forming a through hole penetrating the silicon substrate, and then a step of embedding a conductive layer in the through hole for the purpose of providing a method for forming a multilayer wiring made of a material having a thermal expansion coefficient equivalent to that of the element, A step of forming a first wiring layer electrically connected to the conductive layer via a first insulating film on the surface of the silicon substrate; and a second insulating film covering the surface of the first wiring layer. Step of forming, step of forming conduction hole in the second insulating film by photolithography technique, and second wiring electrically connected to the first wiring layer through the conduction hole The process of forming layers and this The back surface of the emission substrate,
An electrode formed on a substrate of semiconductor particles made of a material having a thermal expansion coefficient equivalent to that of the silicon substrate and a step of electrically connecting the conductive layer are configured.

[Industrial applications]

The present invention relates to a multilayer wiring, and more particularly to a method for forming a multilayer wiring on a substrate made of a material having a coefficient of thermal expansion equivalent to that of a semiconductor element substrate.

A ceramic multilayer wiring board is generally used as the multilayer wiring, but various restrictions and obstacles are caused by the material, structure and manufacturing method used.

Under the circumstances as described above, there has been a demand for a method for forming a multilayer wiring which does not have restrictions or obstacles that occur in the ceramic multilayer wiring board.

[Conventional technology]

As shown in FIG. 6, the conventional ceramic multilayer wiring board is printed with a conductive pattern 25 on the surface of the green sheet 21 by screen printing using a mesh screen 22 and a squeegee 23 using a conductive paste 24, and the green sheet Are aligned and stacked to form a multi-layer, and in that state, while being heated to a hundred and several tens of degrees, a pressure of several hundred kg / cm ² is applied for several tens of minutes to perform a laminated firing process.

As shown in FIG. 7 (b), the structure of the multi-layered ceramic substrate in which the green sheets are laminated through the above-described steps has a surface layer green sheet 32 at the top and an I / O pin green sheet 33 at the bottom. Are placed and the inner layer green sheet in between
Dozens of 31 sheets are sandwiched and stacked.

 The conventional manufacturing process will be described with reference to FIG.

First, as shown in FIG. 7 (a), the inner layer green sheet
A hole 31a for conduction is formed in the hole 31, a conductor pattern 31b is printed, a necessary number of sheets are stacked and laminated, and a firing process is performed.

Next, as shown in FIG. 7 (b), holes for conduction are formed in the green sheet 32 for the surface layer, the conductor pattern 32a is printed, and the green sheet 33 for I / O pins in which the conduction holes are processed is used together with the above-mentioned. Then, a lamination process is performed with the inner green sheet 31 and the firing process is performed.

Further, as shown in FIG. 7C, the I / O pin pads 33a of the I / O pin green sheet 33 are printed and fired.

The above-mentioned baking treatment is heating at a temperature at which the green sheet is completely magnetized.

Due to the processing method, the minimum pitch of the conduction holes of the green sheet that has been fired in this way is limited to 150 μm.

[Problems to be solved by the invention]

A problem with the conventional ceramic multilayer wiring board described above is that the distance between the holes for conduction of the ceramic multilayer wiring board formed by a drill is limited and the difference in the coefficient of thermal expansion is due to the material of the semiconductor element and the ceramic multilayer wiring board. It exists between the wiring board and the material.

That is, since the distance between the holes for conduction cannot be reduced to a certain value or less by the drilling method, a wide area is required, and the difference in thermal expansion coefficient between the electrodes of the semiconductor element and the ceramic multilayer wiring board is required. It requires a strong bond that can withstand stress.

In view of the above circumstances, the present invention has an object to provide a method for forming a multi-layer wiring made of a material having a small distance between the holes for conduction and a coefficient of thermal expansion which is similar to that of a semiconductor element.

[Means for solving problems]

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a through hole penetrating a silicon substrate, a step of embedding a conductive layer in the through hole, and a step of forming a first insulating film on the surface of the silicon substrate. A step of forming a first wiring layer electrically connected to this conductive layer via a step of forming a second insulating film covering the surface of the first wiring layer, and a step of forming the second insulating film by a photolithography technique. A step of forming a conduction hole in the insulating film, and a step of forming a second wiring layer electrically connected to the first wiring layer via the conduction hole,
A structure including a step of electrically connecting, to the back surface of the silicon substrate, an electrode formed on a substrate of semiconductor particles made of a material having a thermal expansion coefficient equivalent to that of the silicon substrate, and the conductive layer. To do.

[Action]

That is, in the present invention, since the conduction holes are formed by the lithography technique, it is possible to greatly reduce the distance between the conduction holes provided in the multilayer wiring.

Further, since the material having the same coefficient of thermal expansion as that of the substrate of the semiconductor element is used, the number of defective connections between the semiconductor element and the multilayer wiring board is small. It becomes possible to mount it.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS.

First, as shown in FIGS. 1 (a) and 1 (b), a resist film 2 coated on the surface of a silicon substrate 1 having a thickness of 1 mm is coated with a pattern of + mark having a width of 2 μm by 1 m by a normal photo process.
Reactive ion etching using carbon tetrachloride (CCl ₄ ) as reaction gas (hereinafter RI
(Abbreviated as E.), a + mark having a depth of 0.3 μm is formed on the silicon substrate 1.

Next, with this mark as a reference, a through hole 1a having a diameter of 5 μm is formed in the silicon substrate 1 at a desired position by chemical etching using an argon laser.

In order to perform this chemical etching, as shown in FIG. 2, the etching bath 4 mounted on the XY stage 3 is filled with an etching solution, for example, an aqueous solution of caustic potassium (KOH), and the wafer holder is filled with picein. The silicon substrate 1 fixed on the substrate 5 is placed, and an argon laser beam with an output of 10 W is applied to the surface of the silicon substrate 1 by a lens to make the thickness 5 μm.
The irradiation is done by narrowing down the diameter.

After forming a hole penetrating the silicon substrate 1 at a desired position on the silicon substrate 1, a 1 μm silicon thermal oxide film 6 is formed on the entire surface of the silicon substrate 1 and the surface of the through hole 1a by wet thermal oxidation at 1,050 ° C.

Next, as shown in FIG. 3A, a polysilicon film 7 doped with phosphorus is formed on the silicon thermal oxide film 6 by the low pressure CVD method. In this case, the through hole 1a needs to be completely filled with polysilicon.

The polysilicon films 7 formed on both surfaces of the silicon substrate 1 are removed by mechanical chemical etching with a polyester polishing pad using ethylenediamine / pyrocatechol, and the silicon substrate 1 is removed as shown in FIG. 3 (b). The silicon thermal oxide film 6 on the surface of is flattened.

Next, an aluminum layer having a film thickness of 1 μm is formed on the surface of the silicon thermal oxide film 6 by a magnetron plasma CVD method (hereinafter abbreviated as MPCVD method) under the following conditions.

Source gas ・ ・ ・ Trimethylaluminum [Al (CH ₃ ) ₃ ] Output of high frequency power source …… 1 W / cm ² Reaction chamber pressure …… ^{2 to} 3 Torr Magnetic field strength …… 780G This aluminum layer as shown in Fig. 3 (c) Is patterned to form a desired first aluminum wiring layer 8, and silylated polymethyl silsesquioxane 9 (hereinafter abbreviated as PMSS) is applied using a spinner.

After the PMSS 9 is heat-treated, a hole 9a for conduction is formed at a desired position by a photo process step.

Embedding aluminum in the conduction hole 9a is a lift
The off method is used.

First, a resist is applied to the surface of PMSS 9 and the inside of conduction hole 9a. Since the resist film is particularly thick inside the conduction hole 9a, it is necessary to lengthen the exposure time.

Post-baking after development is performed when the temperature of the silicon substrate 1 is 100 ° C. when aluminum is deposited by the MPCVD method in the next step.
Since it will be around, it is necessary to perform at 150 ℃.

Alternatively, the resist used for PMSS patterning may be used as it is.

The aluminum deposition conditions of the MPCVD method are the same as those of the first aluminum wiring layer 8, and aluminum does not adhere to the sidewalls of the resist film in the MPCVD method at a low temperature.

In this way, as shown in FIG. 3 (d), the conduction hole 9a
After depositing aluminum to the surface of the PMSS 9, the aluminum layer other than the conduction holes 9a is removed together with the resist film by a resist removing liquid.

In FIG. 3 (e) showing this state, the surface of the PMSS 9 and the aluminum layer in the hole 9a for conduction are substantially flush with each other.

An aluminum layer to be the second aluminum wiring layer 10 is formed on this by MPCVD as in the case of the first aluminum wiring layer 8.
Then, the second aluminum wiring layer 10 is formed by patterning as shown in FIG. 3 (f).

Similarly, the third aluminum wiring layer 11 is formed,
By covering the entire surface with PMSS9, it becomes possible to form a multilayer wiring having a cross section as shown in FIG. 3 (f).

As shown in the lower part of the figure, electrodes 1b (hereinafter abbreviated as bumps) to be connected to the electrodes of the semiconductor element are formed in the polysilicon of the through hole 1a of the silicon substrate 1 and the semiconductor element 12
The electrode 12a of is heated and connected.

Fig. 4 shows bumping of all semiconductor elements 12 to be mounted.
1b shows the state of heating connection.

Around the multi-layer wiring, take-out pad 13 as shown
To provide.

Further, in order to confirm the connection state of the semiconductor element, a measurement pad 14 is formed on the upper part of the multi-layer wiring and measured by a measurement prober to detect connection failure or semiconductor element failure.

FIG. 5 shows a state in which after fixing the multilayer wiring of FIG. 4 with epoxy resin 16, the output pin 15 and the take-out pad 13 are connected by wire bonding, and this connection part is also sealed with epoxy resin. Is shown.

At this time, the heat dissipation plate 17 close to the semiconductor element 12 is embedded in the epoxy resin 16 to dissipate the heat generated by the semiconductor element 12.

In this way, using a material having the same thermal expansion coefficient as that of the semiconductor element 12, a multilayer wiring having an aluminum wiring layer by plasma CVD and an interlayer insulating film made of PMSS9 is formed, and the semiconductor element is heated and connected by a bump provided in the multilayer wiring. Then, by sealing with epoxy resin, it is possible to form an excellent aluminum wiring layer without hillock generation, and obtain a multi-layer wiring connected by conduction holes 9a with a very fine pitch formed by photo process. Therefore, it is possible to obtain a very compact and stable connection in which stress does not occur at the connection between the multilayer wiring and the semiconductor element.

In addition, as a method of forming the etching groove of + mark, which is used as a reference when forming the through hole 1a at a desired position of the silicon substrate 1 by photochemical etching with an argon laser, a method of directly providing the above-mentioned silicon substrate 1 is used. Alternatively, a method of forming a 1 μm CVD silicon oxide film on the entire surface of the silicon substrate 1, patterning the desired + mark by a photo process step, and etching this CVD silicon oxide film by RIE using CHF ₃ is also possible. Is.

Further, as a method of filling the through hole 1a provided in the silicon substrate 1, in addition to the method of forming the doped polysilicon film 7 described above, a method of forming a metal film by plating with nickel, copper or the like is also possible. is there.

[Effects of the Invention] As is clear from the above description, according to the present invention, the distance between the holes for conduction in the conventional ceramic multilayer wiring substrate was about 150 μm due to processing restrictions, whereas in the present invention, It is possible to reduce this value to 1/10 or less,
Therefore, the present invention requires several layers, whereas the present invention requires only several layers.

Further, by using a material having a coefficient of thermal expansion equivalent to that of the semiconductor element, poor connection between the semiconductor element and the electrodes of the multilayer wiring board is reduced.

Since PMSS is used for the plasma CVD aluminum wiring layer and the interlayer insulating film, it is possible to manufacture a highly reliable multilayer wiring without hillocks.

As mentioned above, there are various advantages, and it is extremely economical and
The effect of improving reliability can be expected, and it is extremely useful industrially.

[Brief description of drawings]

FIG. 1 is a diagram showing a state in which a + pattern is formed on a resist film according to one embodiment of the present invention, and FIG. 2 shows a through hole formation state by chemical etching using an argon laser according to one embodiment of the present invention. Fig. 3, Fig. 3 is a side sectional view showing one embodiment according to the present invention in the order of steps, Fig. 4 is an outline outline drawing of one embodiment according to the present invention, and Fig. 5 is a completed outline drawing of one embodiment according to the present invention. FIG. 6 is a cross-sectional view showing a method of applying a conductive paste to a green sheet of a conventional ceramic multilayer wiring board, and FIG. 7 is a perspective view showing a method of manufacturing a conventional ceramic multilayer wiring board in the order of steps. In the figure, 1 is a silicon substrate, 1a is a through hole, 1b is a bump, 2 is a resist film, 3 is an XY stage, 4 is an etching tank, 5 is a wafer holder, 6 is a silicon thermal oxide film, and 7 is polysilicon. Film, 8 first aluminum wiring layer, 9 PMSS, 9a conductive hole, 10 second aluminum wiring layer, 11 third aluminum wiring layer, 12 semiconductor element, 12a electrode, 13 extraction pad , 14 is a measuring pad, 15 is an output pin, 16 is an epoxy resin, and 17 is a heat sink.

Claims (1)

(57) [Claims] 1. A step of forming a through hole penetrating a silicon substrate, a step of embedding a conductive layer in the through hole, and a step of embedding a conductive layer on the surface of the silicon substrate via a first insulating film. A step of forming a first wiring layer electrically connected to the first wiring layer, a step of forming a second insulating film covering the surface of the first wiring layer, and a step of forming a second insulating film on the second insulating film by a photolithography technique. Forming a common hole; forming a second wiring layer electrically connected to the first wiring layer through the conduction hole; and forming a second wiring layer on the back surface of the silicon substrate with the silicon substrate. A method of manufacturing a semiconductor device, comprising: a step of electrically connecting an electrode formed on a substrate of a semiconductor element made of a material having an equivalent thermal expansion coefficient to the conductive layer.