JP2540195B2 - Electronic control unit for engine - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an electronic control unit for an engine that time-divisionally processes input data acquisition, control data output, and arithmetic processing.

[Prior Art] In recent years, electronic technology has been introduced into vehicles such as automobiles, and various controls, that is, power train control of engines and transmissions, vehicle control of suspensions, brakes, and car air conditioners have been electronically controlled. . The electronic control of this automobile is performed by, for example, a microcomputer, and in the engine, the electronic control by the microcomputer has achieved the improvement of exhaust emission and the improvement of fuel consumption.

The electronic control of the engine by the microcomputer is usually performed by a microprocessor (CPU) 50, a read-only memory (see FIG. 7) as disclosed in, for example, Japanese Patent Laid-Open No. 60-93150. ROM) 51, read / write memory (RAM) 52, input interface 53,
And an output interface 54 and the like are connected via a bus line 55, and are realized by an electronic control unit 56 centered on a microcomputer.

Input interface 53 of the above microcomputer
Various sensors 57 for detecting the operating state of the engine are connected to the output interface 54 via a waveform shaping circuit and the like, and actuators 59 such as an ignition coil and an injector 59 are connected to the output interface 54 via a drive circuit 58. Are connected. The CPU 50 fetches various input data from various sensors 57 indicating the state of the engine according to a control program stored in the ROM 51 at a predetermined timing via the input interface 53, and temporarily stores the data in the RAM 52. The various input data stored in the RAM 52 is read by the CPU 50 at a predetermined timing, the fuel injection amount, the ignition timing, etc. are calculated based on the various data, and the driving circuit 58 is operated via the output interface 54. Is output. As a result, the actuators 59 such as injectors and ignition coils are driven to control the air-fuel ratio and the ignition timing.

By the way, generally, the calculation of the fuel injection amount or the ignition timing is performed in synchronization with the rotation of the engine.
Since various processes cannot be performed at one time, first, for example, the latest input data from the various sensors 57 is read, and the basic amount of fuel injection amount is calculated at regular time intervals based on this input data. Next, the ignition timing is calculated for each predetermined crank angle, and further, the fuel injection amount or the correction amount of the ignition timing is calculated to obtain the final fuel injection amount, the control amount such as the ignition timing, and the control amount. The corresponding signal is output to the drive circuit 58 via the output interface 54. This procedure is repeated in synchronization with engine rotation.

However, the input data from the sensors 57 or the control data stored in the RAM 52 is usually taken into the register of the CPU 50 once at a predetermined timing,
Then, the data is output from the CPU 50 to the RAM 52 or the actuators 59. That is, an external device such as the sensor 57 or the actuator 59 and the RA
Data is input to and output from the M52 via the CPU 50. For example, when the input data from the sensors 57 are stored in the RAM 52, the operation of the CPU 50 is such that the fetch cycle for reading the instruction to input the input data through the execution cycle for fetching the input data in the register Following the fetch cycle for reading the instruction for outputting data, the execution cycle for finally outputting the input data fetched in the register to the predetermined address of the RAM 52 is reached. Therefore, the above
It takes a lot of machine cycles to store the input data from the sensors 57 in the RAM 52, and if the amount of input / output data or the input / output frequency increases, the time spent for this input / output processing cannot be ignored. .

That is, when there is no processing time, such as during high-speed engine operation, the CPU 50 causes an increase in the overhead due to input / output processing of the various sensors 57 and actuators 59, and the original fuel injection amount, ignition timing, etc. There is a risk that the arithmetic processing will not be in time, and the load on the CPU will increase, which will interfere with air-fuel ratio control or ignition timing control.

In order to deal with this, Japanese Patent Laid-Open No. 59-108847 discloses that an electronic control unit for an engine is provided with a plurality of CPUs to share functions, one CPU performs I / O control, and the other CPU internally operates. A technique is disclosed in which control and data processing are performed to simplify control of individual CPUs, improve efficiency, and shorten execution time by parallel operation.

[Problems to be Solved by the Invention] However, in the above-described prior art example, it is necessary to appropriately and individually take timings of access to RAMs in a plurality of CPUs.
That is, if one CPU for I / O control is writing input data to RAM and the other CPU for internal control accesses the RAM and reads the input data, the input data in the middle of rewriting is read. As a result, appropriate input data cannot be obtained, and as a result, the control data calculated by the CPU for internal control based on this input data will also be inadequate. Will get worse.

Conversely, if one CPU accesses the RAM and the control data is read while the other CPU is writing the control data to the RAM, appropriate control data cannot be obtained even at this time and the control target As a result, an appropriate control amount cannot be obtained for the engine operation control means such as the injector and the ignition device, and the engine controllability deteriorates.

In addition, since multiple CPUs are used, the cost is relatively increased, and in order to share the functions among multiple CPUs, synchronize the CPUs and
Since it is necessary to perform data communication between PUs, there is also a disadvantage that the load of software and programs increases correspondingly and the program execution load of the CPU becomes heavy.

In view of the above circumstances, the present invention can distribute each data at high speed by distributing the input / output processing and the arithmetic processing.
Provided is an electronic control device for an engine, which can reduce the load on the CPU, can always obtain input data and control data properly, improve reliability of each data, and improve engine controllability. The purpose is to do.

[Means for Solving the Problems] In order to achieve the above object, the electronic control unit for an engine according to the first aspect of the present invention calculates control data for the engine operation control means based on input data from the engine operation state detection means, In an electronic control unit for an engine that controls the engine by operating the engine operation control means based on control data, the input data stored in the storage means is read to calculate various control data, and the various control data are stored in the storage means. And the operation processing means for storing the input data input from the engine operating state detection means to the storage means or stored in the storage means. Data transfer processing means for executing data transfer of the control data to the engine operation control means. It is characterized by

The electronic control unit for an engine according to the second aspect of the present invention calculates control data for the engine operation control means based on the input data from the engine operation state detection means, and causes the engine operation control means to operate based on the control data to operate the engine. In the electronic control unit of the engine for controlling
Arithmetic processing means for reading input data stored in the storage means to calculate various control data, storing the various control data in the storage means, and permitting direct memory access for each cycle in which the storage means is not accessed;
By the direct memory access permission by the arithmetic processing means, the data transfer of the input data input from the engine operating state detection means to the storage means or the data transfer of the control data stored in the storage means to the engine operation control means. And a data transfer processing means for executing.

Further, it is desirable that the data transfer processing means in the first invention or the second invention is constituted by a direct memory access controller.

[Operation] In the first invention, the arithmetic processing unit reads the input data from the storage unit, calculates various control data based on the input data, stores the control data in the storage unit, and the engine operating state detection unit. The storage of the input data input from the storage means and the data transfer of the control data stored in the storage means by the arithmetic processing means to the engine operation control means are performed by the data transfer processing means.
The operation of the arithmetic processing means is stopped at every predetermined timing, and is performed during this period.

In the second aspect of the invention, the arithmetic processing unit reads the input data from the storage unit, calculates various control data based on the input data, stores the control data in the storage unit, and in each cycle in which the storage unit is not accessed. Direct memory access is permitted to the data transfer processing means. The storage of the input data input from the engine operating state detection means in the storage means and the data transfer of the control data stored in the storage means by the arithmetic processing means to the engine operation control means are directly performed by the arithmetic processing means. When the memory access is permitted, it is performed by the data transfer control means.

Embodiments of the Invention Embodiments of the present invention will be described below with reference to the drawings.

1 to 5 show a first embodiment of the present invention, FIG. 1 is a functional block diagram of an electronic control unit, FIG. 2 is a schematic diagram of an engine control system, and FIGS. 3 and 4 are arithmetic operations. FIG. 5 is a flowchart showing the control procedure of the processing means, and FIG. 5 is a flowchart showing the data transfer procedure.

In FIG. 2, reference numeral 1 is an engine body, and in the figure, a horizontally opposed four-cylinder engine is shown. The intake port formed in the cylinder head 2 of the engine body 1
An intake manifold 3 and an exhaust manifold 4 are connected to the exhaust port 2a and the exhaust port 2b, respectively. Further, the cylinder head 2 is equipped with a spark plug 5 exposing its ignition part to the combustion chamber 1a.

A throttle chamber 7 is connected to the upstream side of the intake manifold 3 via an air chamber 6, and the upstream side of the throttle chamber 7 is connected to an air cleaner 9 via an intake pipe 8.

Further, an intake air amount sensor (a hot wire type air flow meter in the figure) 10 is provided immediately downstream of the air cleaner 9 in the intake pipe 8, and a throttle valve 7a provided in the throttle chamber 7 is provided with a throttle valve 7a. The position sensor 11 and the idle switch 11a are connected in series.

Further, the combustion chamber of each cylinder of the intake manifold 3
An injector 12 is arranged immediately upstream of each suction port 2a communicating with 1a. Further, a cooling water temperature sensor 13 is exposed to a cooling water passage (not shown) formed in the intake manifold 3.

A crank rotor 14 is fixedly mounted on the crank shaft 1b of the engine body 1.
A crank angle sensor 15 is provided opposite to the outer circumference of 14.

Further, an O2 sensor 17 is exposed to the exhaust pipe 16 communicating with the exhaust manifold 4. Reference numeral 18 is a catalytic converter.

On the other hand, reference numeral 19 is an electronic control unit, which includes a microprocessor (CPU) 20, a read-only memory (ROM) 21, a read / write memory (RAM) 22, and an input / output (I / O) interface 24 via a bus line 25. And a peripheral circuit such as a drive circuit 26, and a direct memory access controller (DMAC) 23 is connected to the above-mentioned micro computer via a bus line 25. . The input ports of the I / O interface 24 are connected to the sensors and switches described above.
10, 11, 11a, 13, 15, 15 are connected, and the injector 12 and the ignition coil 27 are connected to the output port of the I / O interface 24 via a drive circuit 26.
A distributor 28 is provided on the secondary side of the ignition coil 27.
The spark plug 5 is connected via.

Fixed data such as a control program is stored in the ROM 21, and the RAM 22 stores each sensor,
Input data from the switches 10, 11, 11a, 13, 15, 17 and various control data calculated by the CPU 20 based on the input data are stored.

The CPU 20 calculates control data (control amount) such as the fuel injection amount and the ignition timing based on the input data stored in the RAM 22 according to the control program stored in the ROM 21.

On the other hand, the above-mentioned DMAC23 is the above-mentioned each sensor and switch 10,1.
Transfer of input data from 1,11a, 13,15,17 to the RAM22,
Alternatively, by controlling the transfer of various control data from the RAM 22 to the injector 12 and the ignition coil 27,
Data is transferred without going through the CPU 20.

Next, the functional configuration of the electronic control unit 19 will be described with reference to FIG. As shown in FIG. 1, the electronic control unit 19 is composed of a data transfer processing means 30, a storage means 31, an arithmetic processing means 32, and a drive circuit 26.

The data transfer processing means 30 is specifically realized by the DMAC 23 and the I / O interface 24 shown in FIG. 2, and includes an intake air amount sensor 10, a throttle position sensor 11, an idle switch 11a, a cooling water temperature sensor. 1
3, crank angle sensor 15, each sensor such as O2 sensor 17, engine operating state detection means 33 including switches
Storing input data from the storage means 31 and outputting various control data stored in the storage means 31 to the engine operation control means 34 including actuators such as the injector 12 and the ignition coil 27. To control. That is, the data transfer processing means 30 stops the operation of the arithmetic processing means 32 at every predetermined timing, and during this period, the storage means 31 for the input data from the engine operating state detecting means 33.
The control data stored in the storage means 31 by the arithmetic processing means 32 is transferred to the engine operation control means 34. The storage means 31 is specifically
It is composed of RAM22.

The arithmetic processing means 32 is specifically realized by, for example, the CPU 20 shown in FIG.
The input data from the engine operating state detecting means 33 stored in 1 is read out, various control data are calculated from this input data, and stored in the storing means 31.

Therefore, the input / output processing and the arithmetic processing of the signal are shared by the data transfer processing means 30 and the arithmetic processing means 32, respectively, and as described above, the input / output processing that conventionally consumes many machine cycles in the CPU 20 is The data transfer processing means 30 shortens the data transfer speed and enables high-speed data transfer.

Next, the control procedure in the electronic control unit 19 will be described with reference to the flowcharts of FIGS.

(Arithmetic processing procedure) In the arithmetic processing means 32, the system is first initialized in step S100 according to the flowchart shown in FIG. 3, and then the process proceeds to step S101, in which the CPU 20 registers the RAM 22 or the I / O interface in the register of the DMAC 23. Write the 24 data transfer start address, the number of bytes of data to be transferred, the transfer direction, etc. After that, if there is a data transfer request (DMA request), the CPU 20 operates according to the procedure shown in FIG. 4 after the end of the execution cycle at that time.

In step S102, the CPU 20 receives the input data from the engine operating state detecting means 33 stored in a predetermined address of the RAM 22 from the I / O interface 24 and the bus line 2
Read through 5, and go to step S103.

In step S103, based on the read input data, for example, control data such as the fuel injection amount is calculated,
Proceed to S104.

When the process proceeds to step S104, the control data calculated in step S103 is stored in another address of the RAM 22, the process returns to step S102, the above procedure is repeated, and the next control data, for example, the ignition timing is returned. Start calculation of control data such as.

Here, after the step S101 and thereafter, when a DMA request is made from the DMAC 23 to the CPU 20, the CPU 20 is
Control is transferred to the procedure shown in the figure, and in step S110, immediately after the end of the execution cycle at that time, the bus line 25 is released and the DMA permission signal is output.

Next, when proceeding to step S111, the CPU 20 stops its operation and waits at step S112 until the DMA end signal is input.

When the DMA end signal is input in step S112, the routine shown in FIG. 4 is exited, and the operation is restarted from the cycle next to the execution cycle at the time when the DMA request signal is input.

(Data Transfer Procedure) Next, the data transfer procedure by the DMAC 23 will be described with reference to the flowchart of FIG.

In step S200, the timing of output of control data to the engine operation control means 34 such as the injector 12 and the ignition coil 27 is determined, and when the predetermined output timing of the control data is reached, step S202 proceeds, and if it is not the output timing,
Proceed to step S201.

In step S201, each sensor, the input signal from the engine operating state detection means 33 consisting of switches is input to the I / O interface 24, and the DMA start trigger signal is input to the DMAC 23, the process proceeds to step S202, and the input is performed. If there is no signal, the process returns to step S200 to wait for output of control data or input of data.

On the other hand, in step S202, the output of control data from the RAM 22 to the engine operation control means 34 is started or the RAM 22 of the input data of the engine operation state detection means 33 is output.
DM that indicates the start of storing data in the disk, that is, the start of data transfer
A request signal is output from the DMAC 23 to the CPU 20 and step S203
Go to.

In step S203, the DMA output in step S202 above
When the CPU 20 responds to the request signal and a DMA permission signal for releasing the bus line 25 that was exclusively used by the CPU 20 is output, the DMAC 23 receives this signal and starts DMA from a preset address. The signal is output to the I / O interface 24. Then, in step S204, the input data from the engine operating state detecting means 33 to the RAM22, or the engine operating control means 3 from the RAM22.
A certain number of bytes of data such as control data for 4 are
It is directly transferred through the I / O interface 24 and the bus line 25 without passing through the PU 20.

When the data transfer ends in step S205, the DMAC 23 outputs a DMA end signal to the CPU 20 to release the bus line 25, and the process returns to step S200.

That is, the engine operating state detection means 33 and the storage means 31
Data transfer between the storage means 31 and the engine operation control means 34 is performed by the data transfer processing means 30 during time division and is performed while the arithmetic processing means 32 is stopped, so that the overhead for the arithmetic processing is reduced. It

(Second Embodiment) FIG. 6 shows a second embodiment of the present invention, and FIG. 6 is a flowchart showing a data transfer procedure. The same steps as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

In the second embodiment, the data transfer processing unit 30 is allowed to perform the direct memory access in each cycle in which the arithmetic processing unit 32 does not access the storage unit 31. Perform data transfer when allowed.

 First, the calculation processing procedure will be described.

When the CPU 20 receives the DMA request signal, the CPU 20 does not stop at step S111 of the flowchart shown in FIG. 4 of the first embodiment and does not use the bus line 25 in the operation cycle of the CPU 20, that is, an instruction decoding cycle or the like. For each cycle that does not access ROM21 or RAM22,
The DMA enable signal is output to allow direct memory access to the DMAC23. The other operations of the CPU 20 are similar to those of the first embodiment, and the description thereof will be omitted.

Explaining the data transfer procedure, as in the first embodiment, the process proceeds to step S206 of FIG. 6 through step S200 or step S201, and when the DMAC 23 receives the DMA permission signal output from the CPU 20 in each operation cycle. If it is determined whether or not, and the above DMA permission signal is received,
On the other hand, if the DMA enable signal from the CPU 20 is not received, the CPU 20 determines that the bus line 2
Since it occupies 5, it returns to step S206 and waits for the above DMA permission signal.

When the DMA permission signal is received, in step S207, data that can be transferred onto the bus line 25 at one time, for example, 1-byte data is transferred, and the process proceeds to step S208.

In step S208, it is checked whether or not the transfer of the predetermined number of bytes of data has been completed, and when the transfer is not completed, the process returns to step S206 again, and waits for the DMA permission signal from the CPU 20, On the other hand, when the transfer is completed,
Proceed to step S209.

In step S209, a DMA end signal is output to the CPU 20, the process returns to step S200 again, and the above procedure is repeated.

That is, in the above-described first embodiment, when there is a DMA request, the CPU 20 stops and a predetermined number of bytes of data are transferred at once, so-called burst mode transfer is performed, whereas in the second embodiment, In an embodiment, the DMAC23
By the so-called cycle steal mode in which the CPU 20 outputs a DMA enable signal for each operation cycle that does not use the bus line 25, for example, data transfer of 1 byte is repeated until a predetermined number of bytes is reached. Be done. The DMA in these two modes is the number of bytes of input or output data, the data interval, and the CPU2
0 is appropriately selected depending on the processing being executed.

In the present embodiment, the data transfer between the RAM 22, the engine operating state detecting means 33, and the engine operating control means 34 has been described, but for example, the data transfer from the ROM 21 to the RAM 22 and further to the RAM other than the RAM 22. Data transfer, etc.
It goes without saying that the present invention can be applied to data transfer between memories.

According to the first aspect of the present invention, the arithmetic processing unit reads the input data from the storage unit, calculates various control data based on the input data, and stores the control data in the storage unit. The data transfer processing means stores the input data stored and input from the engine operating state detection means in the storage means and the control data stored in the storage means by the arithmetic processing means to the engine operation control means. Thus, the operation of the arithmetic processing means is stopped at every predetermined timing, and the operation is performed during this period. Therefore, while the storage means is being accessed by the data transfer processing means, access to the storage means by the arithmetic processing means is substantially prohibited. Accurate input data is always given to the arithmetic processing means,
The control data read out from the storage means by the data transfer processing means and transferred to the engine operation control means can always obtain an appropriate value, and the reliability of each data is improved, so that the engine control accuracy and the engine control can be improved. It is possible to improve the property.

Further, since the input / output processing of signals and the arithmetic processing are shared by the data transfer processing means and the arithmetic processing means, respectively,
Since each data can be transferred at high speed, the load on the CPU constituting the above arithmetic processing means is reduced, and the reliability of each data is high, the input / output processing and the arithmetic processing of the control data are always appropriate. Is performed, it is possible to maintain the engine operating state optimal, the improvement of engine output performance,
It is possible to improve exhaust emission and fuel efficiency.

According to the second aspect of the present invention, the arithmetic processing unit reads the input data from the storage unit, calculates various control data based on the input data, and stores the control data in the storage unit. Direct memory access is permitted to the data transfer processing means for each cycle in which no access is made to. The storage of the input data input from the engine operating state detection means in the storage means and the data transfer of the control data stored in the storage means by the arithmetic processing means to the engine operation control means are directly performed by the arithmetic processing means. When the memory access is permitted, it is performed by the data transfer processing means.
During the access to the storage means by the arithmetic processing means, the access to the storage means by the data transfer processing means is substantially prohibited, and the input data is always given to the arithmetic processing means and stored by the data transfer processing means. The control data read from the means and transferred to the engine operation control means can always obtain an appropriate value, and the reliability of each data is improved, so that the engine control accuracy and the engine controllability can be improved. it can.

Further, similarly to the first aspect of the invention, since the signal input / output processing and the arithmetic processing are shared by the data transfer processing means and the arithmetic processing means, it becomes possible to transfer each data at a high speed. Since the load on the CPU that constitutes the arithmetic processing means is reduced and the reliability of each data is high,
Input / output processing and control data arithmetic processing are always performed properly, making it possible to keep the engine operating state optimal.
It is possible to improve engine output performance, exhaust emission, and fuel efficiency.

Further, according to the third invention of claim 3, the first
In addition to the effect of the invention or the second invention, since the data transfer processing means is constituted by the direct memory access controller, compared to the case of using a plurality of CPUs as in the prior art,
The cost can be relatively reduced, a data transfer program is not required, and data communication between CPUs required when multiple CPUs share functions is not required. There is no increase in the load on the software and programs, and the program execution load on the CPU is reduced.

[Brief description of drawings]

1 to 5 show a first embodiment of the present invention, FIG. 1 is a functional block diagram of an electronic control unit, FIG. 2 is a schematic diagram of an engine control system, and FIGS. 3 and 4 are arithmetic operations. FIG. 5 is a flowchart showing a data transfer procedure, FIG. 6 is a flowchart showing a data transfer procedure, and FIG. 7 is a circuit showing a conventional example. It is a block diagram. 19 …… Electronic control device, 20 …… CPU, 23 …… Direct memory access controller (DMA
C), 30 ... Data transfer processing means, 31 ... Storage means, 32 ... Arithmetic processing means, 33 ... Engine operating state detecting means, 34 ... Engine operating control means.

Claims (3)

(57) [Claims] 1. An electronic control unit for an engine, which calculates control data for an engine operation control means on the basis of input data from an engine operation state detection means and operates the engine operation control means on the basis of the control data to control the engine. In which the input data stored in the storage means are read out, various control data are calculated, and the various control data are stored in the storage means, and the operation of the above-mentioned arithmetic processing means is stopped at every predetermined timing. Data transfer processing means for executing data transfer of the input data input from the engine operating state detection means to the storage means or data transfer of the control data stored in the storage means to the engine operation control means. An electronic control unit for an engine, characterized in that 2. An electronic control device for an engine, which calculates control data for an engine operation control means on the basis of input data from the engine operation state detection means and operates the engine operation control means based on the control data to control the engine. In which the input data stored in the storage means are read to calculate various control data, the various control data are stored in the storage means, and the direct memory access is permitted for each cycle in which the storage means is not accessed. And, by permitting direct memory access by the arithmetic processing means, data transfer of the input data input from the engine operating state detecting means to the storage means or control data stored in the storage means to the engine operation control means. Equipped with data transfer processing means for executing data transfer Electronic engine control apparatus wherein the Rukoto. 3. The electronic control unit for an engine according to claim 1, wherein the data transfer processing means is constituted by a direct memory access controller.